Amplifier Circuit and Method for Increasing Linearity of the Amplifier Circuit

The present invention relates, in general, to amplifiers and, more particularly, to power amplifier circuits.

Portable communication devices include cellular phones and two-way radios. An important component of these devices is the power amplifier circuit. Performance parameters of the power amplifier circuit include linearity and efficiency. The linearity of the power amplifier circuit affects the quality of a signal transmitted by the portable communication device. The efficiency of a power amplifier circuit affects battery life, size, and weight of the portable communication device. Thus, it is desirable for a power amplifier circuit used in these devices to have a large linear range of operation. However, power amplifier circuits having a large linear range of operation are inherently inefficient.

Accordingly, it would be advantageous to have a power amplifier circuit that is both linear and efficient. It would be of further advantage for the power amplifier circuit to be area and cost efficient.

The present invention provides an Envelope Elimination and Restoration (EER) amplifier for amplifying a Radio Frequency (RF) signal having a phase modulated component and an amplitude modulated component. The EER amplifier includes a RF amplifier, an envelope detector, a delay compensation circuit, and an envelope amplifier.

FIG. 1 is a block diagram of an amplifier in accordance with the present invention;

FIG. 2 illustrates an amplitude modulated time-varying sinusoidal signal;

FIG. 3 illustrates a phase modulated signal;

FIG. 4 illustrates an envelope signal;

FIG. 5 illustrates a lead envelope phase signal;

FIG. 6 illustrates an amplified envelope signal;

FIG. 7 is a schematic diagram of an amplifier circuit in accordance with an embodiment of the present invention; and

FIG. 8 is a schematic diagram of an amplifier circuit in accordance with another embodiment of the present invention.

Generally, the present invention provides an amplifier circuit and a method for improving the linearity of the amplifier circuit. More particularly, the present invention uses a technique known as Envelope Elimination and Restoration (EER) to provide an efficient and linear amplifier circuit. A typical EER amplifier circuit amplifies an RF signal by separately amplifying the phase modulated component and the amplitude modulated component of the RF signal. A disadvantage with a typical EER amplifier circuit is the time delay associated with amplifying the amplitude modulated component of the RF signal because it can adversely affect the linearity of the amplified output signal. In accordance with the present invention, a delay compensation circuit is coupled to an EER amplifier circuit to provide an improved EER amplifier circuit. The improved EER amplifier circuit has greater linearity and less distortion than a typical EER amplifier circuit.

FIG. 1 is a block diagram of an amplifier circuit 10 having an input terminal 11 and an output terminal 12 in accordance with the present invention. Amplifier circuit 10 has two paths for amplifying a Radio Frequency (RF) input signal. The first path of amplifier circuit 10 includes a limiter 13 and an RF amplifier 14. The second path of amplifier circuit 10 includes an envelope detector 16, a delay compensation circuit 17, and an envelope amplifier 18. The input of limiter 13 is connected to input terminal 11 and the output of limiter 13 is connected to the RF input of RF amplifier 14. The output of RF amplifier 14 is connected to output terminal 12. The input of envelope detector 16 is connected to input terminal 11 and the output of envelope detector 16 is connected to the input of a delay compensation circuit 17. The input of envelope amplifier 18 is connected to the output of delay compensation circuit 17 and the output of envelope amplifier 18 is connected to the bias input of RF amplifier 14.

The operation of amplifier circuit 10 will be described with reference to FIGS. 1-6. In operation, input terminal 11 is coupled for receiving an RF input signal such as RF input signal 20 illustrated in FIG. 2.

Briefly referring to FIG. 2, RF input signal 20 is an amplitude modulated time-varying sinusoidal signal having an amplitude modulated component 21 and a phase modulated component 22. Amplitude modulated component 21 of RF input signal 20 is also referred to as an envelope of RF input signal 20.

Referring to FIGS. 1-3, the input of limiter 13 receives RF input signal 20 via input terminal 11. Limiter 13 removes amplitude modulated component 21 from RF input signal 20 and generates a phase modulated signal 30 (FIG. 3) in accordance with phase modulated component 22 of RF input signal 20. Phase modulated signal 30 is transmitted to the RF input of RF amplifier 14 from the output of limiter 13.

The input of envelope detector 16 receives RF input signal 20 via input terminal 11. Envelope detector 16 removes phase modulated component 22 from RF input signal 20 and generates an envelope signal 40 (FIG. 4) in accordance with amplitude modulated component 21 of RF input signal 20.

Briefly referring to FIG. 4, envelope signal 40 contains amplitude modulated component 21 of RF input signal 20 but not phase modulated component 22. Envelope signal 40 has an amplitude and a phase. T1 and T2 denote time along the TIME axis. Vo denotes a voltage value along the VOLTAGE axis. At time T2, the amplitude of envelope signal 40 has a voltage value of Vo.

Envelope signal 40 is transmitted to the input of delay compensation circuit 17 from the output of envelope detector 16. Delay compensation circuit 17 advances or increases the phase of envelope signal 40 with respect to time, generating a lead phase envelope signal 50 illustrated in FIG. 5.

Briefly referring to FIG. 5, lead phase envelope signal 50 has a phase and an amplitude. Lead phase envelope signal 50 is similar to envelope signal 40 (FIG. 4) except that the phase of lead phase envelope signal 50 is increased or shifted with respect to time compared to the phase of envelope signal 40. This is illustrated by referring to FIGS. 4 and 5 and noting that the amplitude of lead phase envelope signal 50 has a voltage value of Vo at time T1. Because time T1 occurs before time T2, lead phase envelope signal 50 has a leading phase compared to envelope signal 40.

Lead phase envelope signal 50 is transmitted to the input of envelope amplifier 18. Envelope amplifier 18 amplifies the amplitude of lead phase envelope signal 50 and delays or decreases the phase of lead phase envelope signal 50 with respect to time, generating an amplified envelope signal 60 illustrated in FIG. 6. Briefly referring to FIG. 6, amplified envelope signal 60 has a phase and an amplitude. Amplified envelope signal 60 is similar to envelope signal 40 (FIG. 4) in that the amplitude of amplified envelope signal 60 has a voltage value of Vo at time T2. Amplified envelope signal 60 has a lagging phase compared to lead phase envelope signal 50 (FIG. 5). Amplified envelope signal 60 is also referred to as a bias signal.

Referring to FIGS. 1-6, envelope amplifier 18 introduces the phase delay of lead phase envelope signal 50 and delay compensation circuit 17 introduces a phase increase of envelope signal 40. Preferably, the phase delay of lead phase envelope signal 50 is approximately equal to the phase increase of envelope signal 40. Therefore, amplified envelope signal 60 will not have a phase shift or time delay with respect to envelope signal 40. In accordance with the present invention, the time delay associated with the phase lagging characteristic of envelope amplifier 18 is compensated for by the phase leading characteristic introduced by delay compensation circuit 17. Preferably, the amplitude of amplified envelope signal 60 is greater than the amplitude of envelope signal 40. Amplified envelope signal 60 is transmitted to the bias input of RF amplifier 14 from the output of envelope amplifier 18. Amplified envelope signal 60 provides a modulated power supply signal to the bias input of RF amplifier 14 that is proportional to amplitude modulated component 21 of RF input signal 20. RF amplifier 14 amplifies phase modulated signal 30 in accordance with amplified envelope signal 60 and generates an amplified RF signal having envelope and phase modulated components. The amplified RF signal is similar to RF input signal 20 except that the amplitude of the envelope of the amplified RF signal is greater than the amplitude of envelope 21 of RF input signal 20. The amplified RF signal is transmitted to output terminal 12 from the output of RF amplifier 14. Since phase modulated signal 30 is a signal without a time-varying amplitude, RF amplifier 14 can be a highly efficient amplifier such as, for example, a class A/B amplifier. The linearity of amplifier circuit 10 is greater than a typical EER amplifier circuit because delay compensation circuit 17 compensates the time delay of envelope amplifier 18.

It should be noted that including limiter 13 is not a limitation of the present invention. Amplifier circuit 10 can be manufactured without limiter 13.

FIG. 7 is a schematic diagram of an amplifier circuit 70 in accordance with an embodiment of the present invention. Amplifier circuit 70 includes RF amplifier 14, envelope detector 16, delay compensation circuit 17, and envelope amplifier 18.

By way of example, RF amplifier 14 includes capacitors 81, 83, 88, 89, and 91, inductors 82, 86, and 87, a resistor 84, and a Field Effect Transistor (FET) 85. The first terminal of capacitor 81 is connected to the RF input of RF amplifier 14 and the second terminal of capacitor 81 is connected to the first terminal of inductor 82. The second terminal of inductor 82 is commonly connected to the first terminal of capacitor 83, the first terminal of resistor 84, and the gate of FET 85. The second terminal of capacitor 83 is coupled for receiving a power supply voltage such as, for example, ground. The second terminal of resistor 84 is coupled for receiving a power supply voltage such as, for example, Vgg. The drain of FET 85 is commonly connected to the first terminal of inductor 86 and the first terminal of inductor 87. The source of FET 85 is coupled for receiving a power supply voltage such as, for example, ground. The second terminal of inductor 86 is commonly connected to the bias input of RF amplifier 14 and the first terminal of capacitor 88. The second terminal of capacitor 88 is coupled for receiving a power supply voltage such as, for example, ground. The second terminal of inductor 87 is commonly connected to the first terminal of capacitor 89 and the first terminal of capacitor 91. The second terminal of capacitor 91 is connected to the output of RF amplifier 14 and the second terminal of capacitor 89 is coupled for receiving a power supply voltage such as, for example, ground. Although transistor 85 is shown as a FET, this is not a limitation of the present invention. For example, transistor 85 can be a bipolar transistor. It should be noted that the gate of a FET is referred to as a control electrode and the drain and source of a FET are referred to as current carrying electrodes. Likewise, the base of a bipolar transistor is referred to as the control electrode and the collector and emitter electrodes of the bipolar transistor are referred to as current carrying electrodes.

Envelope detector 16 includes capacitors 92, 96, and 98, resistors 93 and 97, and a diode 94. The first terminal of capacitor 92 is connected to the input of envelope detector 16 and the second terminal of capacitor 92 is commonly connected to the first terminal of resistor 93 and the anode of diode 94. The second terminal of resistor 93 is coupled for receiving a power supply voltage such as, for example, Vcc. The cathode of diode 94 is commonly connected to the first terminal of capacitor 96, the first terminal of resistor 97, and the first terminal of capacitor 98. The second terminal of capacitor 96 and the second terminal of resistor 97 are coupled for receiving a power supply voltage such as, for example, ground. The second terminal of capacitor 98 is connected to the output of envelope detector 16.

Delay compensation circuit 17 is comprised of a phase compensation circuit 101 and a gain stage 102. Phase compensation circuit 101 is comprised of resistors 103 and 106 and a capacitor 104. Gain stage 102 is comprised of an operational amplifier 107 and resistors 108 and 109. The input of phase compensation circuit 101 is connected to the input of delay compensation circuit 17 and the output of phase compensation circuit 101 is connected to the input of gain stage 102. The output of gain stage 102 is connected to the output of delay compensation circuit 17. The first terminal of resistor 103 and the first terminal of capacitor 104 are commonly connected to the input of phase compensation circuit 101. The second terminal of resistor 103 is commonly connected to the second terminal of capacitor 104, the first terminal of resistor 106, and the output of phase compensation circuit 101. The second terminal of resistor 106 is coupled for receiving a power supply voltage such as, for example, ground. The non-inverting input of operational amplifier 107 is connected to the input of gain stage 102 and the output of operational amplifier 107 is connected to the output of gain stage 102. The inverting input of operational amplifier 107 is commonly connected to the first terminal of resistor 108 and the first terminal of resistor 109. The second terminal of resistor 109 is connected to the output of operational amplifier 107 and the second terminal of resistor 108 is coupled for receiving a power supply voltage such as, for example, ground.

Envelope amplifier 18 is comprised of a pulse width modulator 111 and a filter 112. Pulse width modulator 111 is comprised of a comparator 113 and transistors 114 and 116. Filter 112 is a four-pole low-pass filter and includes inductors 117 and 119 and capacitors 118 and 120. The input of pulse width modulator 111 is connected to the input of envelope amplifier 18 and the output of pulse width modulator 111 is connected to the input of filter 112. The output of filter 112 is connected to the output of envelope amplifier 18. The input of pulse width modulator 111 is connected to the comparison input of comparator 113. The reference input of comparator 113 is coupled for receiving a power supply voltage such as, for example, a sampling voltage Vs. Transistor 114 is a P-channel FET and transistor 116 is an N-channel FET, each having a gate, a drain, and a source. The gate of FET 114 is connected to the first output of comparator 113 and the source of FET 114 is coupled for receiving a power supply voltage such as, for example, Vcc. The gate of FET 116 is connected to the second output of comparator 113 and the source of FET 116 is coupled for receiving a power supply voltage such as, for example, ground. The drain of FET 114 is commonly connected to the drain of FET 116 and the output of pulse width modulator 111. The first terminal of inductor 117 is connected to the input of filter 112. The second terminal of inductor 117 is commonly connected to the first terminal of capacitor 118 and the first terminal of inductor 119. The second terminal of inductor 119 is commonly connected to the first terminal of capacitor 120 and the output of filter 112. The second terminal of capacitor 118 and the second terminal of capacitor 120 are coupled for receiving a power supply voltage such as, for example, ground.

In operation, phase compensation circuit 101 receives an envelope signal such as, for example, envelope signal 40 of FIG. 4 and increases the phase of the envelope signal with respect to time as described hereinbefore. Gain stage 102 recovers signal losses from phase compensation circuit 101. It should be noted that including gain stage 102 is not a limitation of the present invention. The following equations are for the gain response (Av) and phase response (PR) of phase compensation circuit 101.

fz is the zero frequency of phase compensation circuit 101;

fp is the pole frequency of phase compensation circuit 101;

R.sub.103 is the resistance value of resistor 103;

R.sub.106 is the resistance value of resistor 106; and

C.sub.104 is the capacitance value of capacitor 104.

A lead phase characteristic for phase compensation circuit 101 is accomplished by designing the zero frequency (fz) of phase compensation circuit 101 to be lower than the pole frequency (fp) of phase compensation circuit 101. Preferably, the phase increase of phase compensation circuit 101 is approximately equal to the phase delay of filter 112. Phase compensation circuit 101 can be placed in series with a similar circuit shown in phase compensation circuit 101 to generate a cascaded network of phase compensation circuits.

The comparison input of pulse width modulator 111 receives a lead phase signal having a time-varying amplitude such as, for example, lead phase envelope signal 50 of FIG. 5 from the output of delay compensation circuit 17. Sampling voltage Vs is a sampling signal such as, for example, a triangle wave signal, and is compared to the amplitude of the lead phase signal appearing at the comparison input of comparator 113. Preferably, the frequency of sampling voltage Vs is greater than the frequency of the lead phase signal. Comparator 113 cooperates with FETs 114 and 116 to generate a pulse width signal having a plurality of pulses. The plurality of pulses of the pulse width signal have pulse widths that may vary with respect to the amplitude of the lead phase signal signal. The pulse width signal is transmitted to the input of filter 112 from the output of pulse width modulator 111. Filter 112 filters the pulse width signal to recover the original envelope of the lead phase signal appearing at the comparison input of comparator 113 and delays the phase of the pulse width signal with respect to time. In addition, filter 112 filters sampling components in the pulse width signal arising from sampling voltage Vs. Pulse width modulator 111 cooperates with filter 112 to provide an efficient circuit for amplifying a signal with a time-varying amplitude. Although filter 112 is described as a four-pole filter, this is not a limitation of the present invention. A filter having any number of poles can be used for filter 112.

FIG. 8 is a schematic diagram of an amplifier circuit 130 in accordance with another embodiment of the present invention. It should be understood that the same reference numerals are used in the figures to denote the same elements. Amplifier circuit 130 includes RF amplifier 14, envelope detector 16, a delay compensation circuit 137, and envelope amplifier 18. Amplifier circuit 130 is similar to amplifier circuit 70 except for the embodiment of delay compensation circuit 137. Delay compensation circuit 137 is comprised of an operational amplifier 138, a capacitor 139, and a resistor 141. The input of delay compensation circuit 137 is connected to the output of envelope detector 16 and the output of delay compensation circuit 137 is connected to the input of envelope amplifier 18. The non-inverting input of operational amplifier 138 is connected to the input of delay compensation circuit 137 and the output of operational amplifier 138 is connected to the output of delay compensation circuit 137. The inverting input is commonly connected to the first terminal of capacitor 139 and the first terminal of resistor 141. The second terminal of resistor 141 is connected to the output of operational amplifier 138 and the second terminal of capacitor 139 is coupled for receiving a power supply voltage.

The operation of delay compensation circuit 137 is similar to the operation of delay compensation circuit 17 of FIG. 7 except that an active circuit is used to increase the phase with respect to time of a signal appearing at the input of delay compensation circuit 137. Preferably, the amount of phase increase of delay compensation circuit 137 is approximately equal to the amount of phase delay of filter 112.

By now it should be appreciated that an amplifier circuit and a method for improving the linearity of the amplifier circuit have been provided. An advantage of the present invention is that it provides an improved EER amplifier circuit than has greater linearity than a typical EER amplifier circuit.