Dynamic Multiplexer Circuits, Systems, and Methods Having Three Signal Inversions From Input to Output

The present embodiments relate to domino logic technology, and are more particularly directed to dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output.

In many modern circuit applications, it is often desirable to increase the speed of operation of the circuit application. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.

To increase the speed of microprocessors, as well as other circuits where speed is important, dynamic or so-called "domino" logic transistor circuits are currently used because they often provide increased speed as compared to static logic transistor circuits. A domino logic circuit is characterized by operating in two phases. First, a precharge node is set to a first potential during a precharge phase. Second, during an evaluate phase, if the logic condition represented by the circuit is satisfied, the precharge node is discharged, thereby changing the logic output of the circuit. In other words, at the conclusion of the precharge phase, the precharge node causes a first logic state to be output by the domino logic circuit. Thereafter, if the precharge node is discharged during the evaluate phase, the output of the domino logic circuit represents a second logic state differing from the first logic state. Moreover, the act of discharging to change states, when accomplished using one or more n-channel transistors to gate the transition from precharge to discharge, represents a speed increase over the prior operation of static circuits which in one instance accomplished a transition with a network of n-channel transistors while in another instance accomplished the opposite transition with a network of p-channel transistors.

One specific example of domino logic transistor circuits is known in the prior art as a dynamic multiplexer. In some contexts, the dynamic multiplexer is sometimes also referred to as a cascode multiplexer or cascode multiplexer logic. In any event, as presented in detail below, operation of the dynamic multiplexer generally follows the principles set forth above as characteristic of domino logic circuits. Additionally the dynamic multiplexer performs a multiplexer function in that any one of multiple data inputs may be selected by asserting a select signal to an input corresponding to the data input. More specifically, the dynamic multiplexer connects each data input to a source of a respective transistor, and a given data input is selected by asserting a signal to the gate of one of the respective transistors. While this implementation provides the functionality set forth above, it is shown below that it includes various drawbacks. For example, as a data transition is connected to a domino logic input, and then selected to an output of the dynamic multiplexer, it incurs a total of four inversions along its path. These four inversions necessarily introduce several drawbacks. For example, naturally there are hardware requirements to construct the inverting circuitry. As another example, each inversion introduces delay to the circuit. As yet another example, there is a financial cost in building each inverter as well as the space required to form the inverter on the semiconductor device used to form the dynamic multiplexer. The inventor of the present embodiments has recognized these above considerations aid below sets forth various embodiments which reduce the above-described drawbacks and improve performance as compared to the prior art.

In the preferred embodiment, there is a dynamic multiplexer circuit comprising an integer number N of data providing circuits, wherein the integer number N is greater than one. Each of the plurality of data providing circuits comprises a precharge node to be precharged to a precharge voltage during a precharge phase, and a conditional series discharge path connected to the precharge node. Each discharge path is operable in response to at least one enabling input signal to discharge the precharge voltage at the precharge node during an evaluate phase thereby providing a first monotonic transitioning data signal at the precharge node. Each of the plurality of data providing circuits further comprises an inverter coupled to the precharge node and having an output for providing a second monotonic transitioning data signal. The second monotonic transitioning data signal is complementary of the first monotonic transitioning data signal. The dynamic multiplexer further comprises the integer nunber N of data select paths. Each of the data select paths comprises a select transistor, the transistor having a source coupled to receive the second monotonic transitioning data signal and a gate connected to receive a select signal. A drain of the select transistor in each of the data select paths is coupled to conditionally discharge an output precharge node. Lastly, the dynamic multiplexer includes an output inverter having an input connected to the output precharge node. In a given evaluate phase of operation, in response to assertion of a select signal corresponding to one of the data select paths, the transistor receiving the asserted select signal at its gate and the second monotonic transitioning data signal at its source conducts for providing an output data signal at an output of the output inverter, wherein the output data signal represents three signal inversions of the at least one enabling input signal. Other circuits, systems, and methods are also disclosed and claimed.

FIG. 1 illustrates a schematic of a prior art dynamic multiplexer;

FIG. 2 illustrates a timing diagram of the operation of the dynamic multiplexer of FIG. 1, and more particularly illustrates the output of a signal corresponding to an asserted input signal;

FIG. 3 illustrates a timing diagram of the operation of the dynamic multiplexer of FIG. 1, and more particularly illustrates the output of a signal corresponding to a de-asserted input signal;

FIG. 4 illustrates a schematic of a dynamic multiplexer in accordance with the preferred embodiment;

FIG. 5 illustrates a timing diagram of the operation of the inventive dynamic multiplexer of FIG. 4, and more particularly illustrates the output of a signal corresponding to an asserted input signal;

FIG. 6 illustrates a timing diagram of the operation of the inventive dynamic multiplexer of FIG. 4, and more particularly illustrates the output of a signal corresponding to a de-asserted input signal; and

FIG. 7 illustrates a schematic of an alternative dynamic multiplexer in accordance with the present embodiments, where the alternative implements various transistors of complementary conductivity type in comparison to the embodiment of FIG. 4.

FIG. 1 illustrates a schematic of a prior art dynamic multiplexer designated generally at 6. Dynamic multiplexer 6 includes data providing circuitry 8 for providing data signals as well as data selection circuitry 10 for then selecting one of the data signals to be presented at an output. As a matter of introduction and for purposes of later discussion, a vertical dashed line generally separates data generating circuitry 8 from data selection circuitry 10 with the former to the left of the dashed line and the latter to the right of the line. Each of these circuits is discussed below.

Looking to data generating circuitry 8 as shown to the left of the vertical dashed line in FIG. 1, this includes three separate dynamic logic circuits shown generally at 12, 14, and 16. Data generating circuitry 8 generally may include any integer number of dynamic logic circuits and, therefore, three circuits 12, 14, and 16, are shown in FIG. 1 merely by way of example. Each of circuits 12, 14, and 16 shares various common attributes, as will be appreciated by one skilled in the art from the following discussion directed to circuit 12. Circuit 12 is a known domino logic circuit stage, which includes a precharge transistor 12.sub.PT, a precharge node 12.sub.PN, an output inverter 12.sub.INV, and a discharge path including both a logic circuit 21.sub.L and a discharge transistor 12.sub.DT. Additionally, dynamic multiplexer 6 includes a conductor for providing a CLOCK signal, and the CLOCK signal is connected to the gate of precharge transistor 12.sub.PT and to the gate of discharge transistor 12.sub.DT.

Looking more specifically to the connections of circuit 12, precharge transistor 12.sub.PT is a p-channel transistor which is typically smaller than the n-channel transistors shown in FIG. 1. Precharge transistor 12.sub.PT has a source connected to a source of the system voltage level (e.g., V.sub.DD) and a drain connected to precharge) node 12.sub.PN. As noted above, the CLOCK signal is connected to the gate of precharge transistor 12.sub.PT and is also connected to the gate of discharge transistor 12.sub.DT. Discharge transistor 12.sub.DT is an n-channel having its source connected to a low reference voltage (e.g., ground) and its drain connected to a node 12.sub.N. Between precharge node 12.sub.PN and node 12.sub.N is connected logic circuit 12.sub.L. The particular logic of logic circuit 12.sub.L may implement any type of logic equation. For example, often logic circuit 12.sub.L will include numerous transistors connected in various fashions to implement such a logic equation, and the logic function is determined based on the particular transistor configuration as well as the respective input signals connected to the gates of those transistors. For purposes of the present discussion, the particular logic equation and inputs are not important and, thus, the legend INPUTS.sub.12 is generally shown with it understood that such signals may come from any of various other circuits, being static, dynamic, or both. What is noteworthy, however, is that once the logic equation formed by logic circuit 12.sub.L is true, at least one conductive path is formed through logic circuit 12.sub.L, thereby connecting precharge node 12.sub.PN node 12.sub.N (i.e., to the drain of discharge transistor 12.sub.DT). Further, recall that the CLOCK signal is connected to the gate of discharge transistor 12.sub.DT. Thus, when the CLOCK is high then the discharge transistor 12.sub.DT is also conducting; if this conduction occurs while the logic equation implemented by logic circuit 12.sub.L is true, then the conducting series path along the source/drains of the transistors forms a discharge path from precharge node 12.sub.PN to ground such that the precharge voltage (i.e., V.sub.DD) at precharge node 12.sub.PN is permitted to discharge to ground.

Returning to precharge node 12.sub.PN, it is further connected to the input of output inverter 12.sub.INV. The output of output inverter 12.sub.INV provides an output signal for circuit 12 (i.e., the result of the logic equation of logic circuit 12.sub.L). Note that output inverter 12.sub.INV is shown as having a short diagonal line in the upper half of the inverter symbol. For purposes of this document, the upper diagonal line of this symbol is included as a convention to demonstrate that a p-channel transistor (not expressly illustrated) is connected in a feedback manner from the output of the inverter to its input. With respect to the p-channel feedback transistor, its gate is connected to the output of the corresponding inverter, the source of the feedback panel transistor is connected to V.sub.DD, and the drain of the feedback p-channel transistor is connected to the input of the corresponding inverter. One skilled in the art will there fore appreciate that once the precharge voltage is no longer connected to a given precharge node in FIG. 1 (e.g., during the evaluate phase described below), the feedback p-channel transistor will maintain a high signal at the input of the inverter so long as the precharge node is not discharged by its corresponding discharge path.

With respect to circuits 14 and 16, note that their circuit elements are generally connected in the same manner as circuit 12 detailed above, with the exception of the inputs to, and transistors within, logic circuit 14.sub.L and 16.sub.L, as well as the output of inverters 14.sub.INV and 16.sub.INV as detailed later. Thus, these inputs and outputs are discussed below while the remainder of the circuit details are not re-stated here and the reader is referred to the above discussion of circuit 12 for comparable details.

Having discussed the connections to circuits 12, 14, and 16, later in FIGS. 2 and 3 are presented timing diagrams demonstrating their detailed operation; as an overview, however, note at this point the two phases of operation of those circuits, as is common for dynamic logic. The first phase of operation is referred to as the precharge phase of operation; in the embodiment of FIG. 1, this precharge phase occurs when the CLOCK signal is low. More particularly, note that the low CLOCK signal is enabling to each of precharge transistors 12.sub.PT, 14.sub.PT, and 16.sub.PT. Note that the statement that a signal is "enabling", such a the CLOCK signal in the current example, is a term known in the art and indicates that the gate-to-source potential is sufficient to cause conduction along the conductive path (i.e., the source/drain) of the transistor to which the gate potential is connected. Conversely, if the signal is "disabling", then the gate-to-source potential is insufficient to cause conduction along the source/drain of the transistor to which the gate potential is connected. These terms are used in various locations through the remainder of this document. Returning to the effect of the enabling low (CLOCK signal, the conduction of each of precharge transistors 12.sub.PT, 14.sub.PT, and 16.sub.PT couples V.sub.DD to each of precharge nodes 12.sub.PN, 14.sub.PN, and 16.sub.PN, respectively, thereby precharging those nodes to a voltage of V.sub.DD. Next, the second phase of operation occurs, which is known as the evaluate phase of operation. During the evaluate phase, input signals are provided to INPUTS.sub.12, INPUTS.sub.14, and INPUTS.sub.16, and the CLOCK signal transitions from low to high such that each of the discharge transistors 12.sub.DT, 14.sub.DT, and 16.sub.DT are enabled and each of the precharge transistors 12.sub.PT, 14.sub.PT, and 16.sub.PT are disabled. Thus, if any of logic circuits 12.sub.L, 14.sub.L, and 16.sub.L are realized as true based on their corresponding INPUTS and internal transistor configurations, then the respective precharge node is discharged. For example, looking to circuit 12, if logic circuit 12.sub.L realizes its logic function as true, then a conductive path is formed from precharge node 12.sub.PN to the drain of discharge transistor 12.sub.DT. Moreover, because discharge transistor 12.sub.DT is concurrently conducting due to the high CLOCK signal, then a complete discharge path is formed which includes both the conductive path through logic circuit 12.sub.L and the source/drain of discharge transistor 12.sub.DT. Consequently, this discharge path discharges the precharged voltage of V.sub.DD at precharge node 12.sub.PN to ground. In response, the output from inverter 12.sub.INV changes state, that is it transitions from low (as it was after the precharge voltage of V.sub.DD was connected to 12.sub.PN) to high. Thus, the precharge voltage at precharge node 12.sub.PN may be thought of as data to be presented during the evaluate phase and, therefore, is indicated as D1 in FIG. 1; specifically, during the evaluate phase of operation, this voltage is conditionally discharged, meaning it either remains at a constant state if a discharge path is not enabled during the that phase, or changes state should such a discharge path be enabled by a true logic finding in logic circuit 12.sub.L.

From the above, one skilled in the art will appreciate that the three dynamic logic circuits of data providing circuitry 8 to the left of the vertical dashed line in FIG. 1 present a total of three data signals D1, D2 and D3, and each of these passes through a respective inverter to provide complementary signals D1, D2 and D3, to data selection circuitry 10 to the right of the vertical dashed line in FIG. 1. Turning then to data selection circuitry 10, it includes data inputs I.sub.1, I.sub.2, and I.sub.3 for receiving each of the complementary data signals D1, D2 and D3, respectively. Each data input I.sub.1, I.sub.2, and I.sub.3 is connected to an input of an inverter INV.sub.1, INV.sub.2, and INV.sub.3, respectively. The outputs of inverters INV.sub.1, INV.sub.2, and INV.sub.3 are connected to the source of n-channel transistors T1, T2 and T3, respectively. The gates of n-channel transistors T1, T2 and T3 are connected to corresponding select signals, designated SEL1, SEL2, and SEL3, respectively. Lastly with respect to transistors T1, T2 and T3, their drains are all connected to a single precharge node SEL.sub.PN. Precharge node SEL.sub.PN is connected to the drain of a p-channel precharge transistor SEL.sub.PT, which has its gate connected to the CLOCK signal and its source connected to V.sub.DD. Precharge node SEL.sub.PN is also connected to the input of an inverter INV.sub.OUT, which provides the DATA OUTPUT for dynamic multiplexer 6. Lastly, note that inverter INV.sub.OUT, in a manner discussed above, has a short diagonal line in the upper half of the inverter symbol; again, this indicates that INV.sub.OUT has a p-channel transistor (not expressly illustrated) connected in a feedback manner from the output of the inverter to its input.

FIG. 2 illustrates a timing diagram of the operation of dynamic multiplexer 6 of FIG. 1, with a particular example where D1 is selected as the data for the DATA OUTPUT. Before proceeding, note for purposes of simplification that various delays are not shown in FIG. 2 when in actuality the transitions shown are not instantaneous. Additionally, certain transitions in FIG. 2 are triggered by other transitions rather than occurring at the immediate same time as shown. With respect to these triggered transitions, the causation is clear from the following discussion and the short delay in those instances need not be shown nor described for purposes of understanding the general operation of dynamic multiplexer 6. Looking then to FIG. 2 and starting at its top, the first signal is the CLOCK signal as connected to various precharge and discharge transistors in dynamic multiplexer 6. Following the CLOCK, signal, the next three signals illustrate the voltage levels at precharge nodes 12.sub.PN, 14.sub.PN, and 16.sub.PN, respectively. Again, because the voltage on these nodes is defined earlier as representing data to be provided during the evaluate phase, then these signals are labeled with both the identifier of the precharge node and the corresponding data signal (e.g., 12.sub.PN /D1 indicates the voltage on precharge node 12.sub.PN, which corresponds to the data signal D1). The fifth signal in FIG. 2 shows the voltage at precharge node SEL.sub.PN of data selection circuitry 10. The sixth signal in FIG. 2 shows the assertion a select signal to choose D1 since that is the example assumed to occur for FIG. 2; thus, this sixth signal shows the value of SEL1 which, as appreciated from the connections of FIG. 1 and the following discussion, is the select signal which is asserted to cause the value of D1 to be connected to the DATA OUTPUT. The seventh and final signal of FIG. 2 shows the value of the DATA OUTPUT.

At t0, the CLOCK signal is low. Therefore, the four precharge transistors in FIG. 1, namely, 12.sub.PT, 14.sub.PT, 16.sub.PT, and SEL.sub.PT, are enabled. The conduction of these transistors causes each of the corresponding precharge nodes 12.sub.PN, 14.sub.PN, 16.sub.PN, and SEL.sub.PN, to charge to a high voltage (i.e., to V.sub.DD). By definition, data selection circuitry 10 is not to be enabled to make any selection during the precharge phase of operation. Therefore, at t0 (i.e., during precharge), all select signals are not enabling. Because FIG. 2 pertains only to the selection of D1, only SEL1 is shown; moreover, since the selection signals are non-enabling during precharge, then at to SELL1 is shown low which is non enabling to T2.

At t1, the CLOCK signal transitions from low to high. Therefore, the three precharge transistors of data providing circuitry 8, namely, 12.sub.PT, 14.sub.PT, and 16.sub.PT are disabled as is precharge transistor SEL.sub.PT of data selection circuitry 10. In addition, the high CLOCK signal enables each of the discharge transistors of data providing circuitry 8, namely, 12.sub.DT, 14.sub.DT, and 16.sub.DT, and also at this time the inputs signals INPUTS.sub.12, INPUTS.sub.14, and INPUTS.sub.16 are asserted to each of logic circuits 12.sub.L, 14.sub.L, and 16.sub.L, respectively. Thus, based on the values of these input signals, any of these logic circuits may conduct. For the sake of example, assume that the values of INPUTS.sub.12 and INPUTS.sub.16 are at levels such that logic circuits 12.sub.L and 16.sub.L conduct (i.e., at least one conductive path is formed), while assume further that the values of INPUTS.sub.14 are at levels such that logic circuit 14.sub.L does not conduct. The operation of the three logic circuits under this assumption cause precharge nodes 12.sub.PN and 16.sub.PN to discharge to ground, while precharge node 14.sub.PN remains charged to V.sub.DD. Thus, at t1, FIG. 2 illustrates a transition from high to low for precharge nodes 12.sub.PN and 16.sub.PN, while no such transition is shown for precharge node 14.sub.PN.

Shortly after t1, when the precharge nodes have had time to sufficiently discharge in response to the values of the INPUTS, if they are to discharge given those values, then up to one of the three select signals SEL1, SEL2, or SEL3 may be asserted. Recall that FIG. 2 is directed to an example of asserting SEL1. Thus, at a time t2 shortly after t1, SEL1 is shown to be asserted by transitioning from low to high. Note now the effect of this high signal. More particularly, recall that SEL.sub.PN has been precharged to V.sub.DD. Therefore, when SEL1 is asserted, both the drain and gate of n-channel transistor T1 are high. However, at the same time, the level of D1, which is then low, is connected through inverters 12.sub.INV and INV.sub.1 to thereby present a low signal to the source of n-channel transistor T1. In other words, at this point, the gate-to-source voltage of n-channel transistor T1 is positive and is larger than the threshold voltage for n-channel transistor T1 and, therefore, n-channel transistor T1 conducts. Since transistor T1 conducts, the precharged voltage of V.sub.DD at precharge node SEL.sub.PN is discharged, as shown in FIG. 2 at t2. Moreover, this falling signal is inverted by inverter INV.sub.OUT and, thus, at the same time (or with some delay which is not shown) DATA OUTPUT concurrently transitions from low to high as shown in the bottom signal of FIG. 2. Thus, the transition at the DATA OUTPUT concludes the last action of the evaluate phase which represents the selection of D1 to the output of dynamic multiplexer 6.

Lastly, note that the last transition of FIG. 2 is shown at t3, and here the CLOCK signal returns from high to low. Accordingly, one skilled in the art will appreciate that once again the precharge phase of operation has commenced, and thus steps such as following from t0 forward may once again occur to once again select one or none of the data signals, D1, D2, or D3, during the evaluate phase to occur in response to the next transition of the CLOCK cycle.

FIG. 3 illustrates a timing diagram of an operational example of dynamic multiplexer 6 in a similar manner to that of FIG. 2, but in FIG. 3 the value of D2 is selected rather than the value of D1. Otherwise, the examples remain the same and, therefore, it is assumed that D1 and D3 are true as realized by logic circuits 12.sub.L and 16.sub.L, respectively, while the value of D2 is false as realized by logic circuit 14.sub.L. Thus, from t0 to t1, the signals are the same as shown above in connection with FIG. 2 and the reader is referred above for additional details. The following discussion, therefore, focuses on the effect starting at t1 given the selection of D2 for output by data selection circuitry 10.

Looking to t1 in FIG. 3, the fifth signal from the top shows that SEL2 is asserted shortly after t1 (again, having given the precharge nodes time to discharge if they are to do so given the values of the INPUTS to logic circuits 12.sub.L, 14.sub.L, and 16.sub.L). Since only up to one select signal may be asserted for an evaluate phase of operation, then it is assumed although not shown that neither SEL1 nor SEL3 is asserted at t1. Returning to FIG. 1 to examine the effect of asserting SEL2 at t1, recall that precharge node SEL.sub.PN has been precharged to V.sub.DD. Therefore, when SEL2 is asserted, both he drain and gate of T2 are high. Moreover, at the same time, the level of D2, which is then also high, is connected by inverter INV.sub.2 to the source of n-channel transistor T2. In other words, at this point, both the gate-to-drain voltage and the gate-to-source voltage of n-channel transistor T2 is less than the threshold voltage for transistor T2; therefore, transistor T2 does not conduct. Since transistor T2 does not conduct, the precharged voltage of V.sub.DD at precharge node SEL.sub.PN is unaffected, as shown in FIG. 3. Consequently, this constant high signal remains inverted by inverter INV.sub.OUT and, thus, continuing after t2 DATA OUTPUT remains low as shown in the bottom signal of FIG. 3. Thus, the assertion of select signal SEL2 and the lack of a transition at the DATA OUTPUT concludes the last action of the evaluate phase which represents the selection of D2 to the output of dynamic multiplexer 6.

Given the above, recall from the earlier Background Of The Invention section of this document that numerous drawbacks exist in the prior art. These drawbacks are perhaps better appreciated having now detailed in FIGS. 1 through 3 the structure and operation of the prior art dynamic multiplexer. Specifically, it was discussed earlier that the prior art configuration includes a total of four signal inversions of data. These four inversions may now be seen given an understanding of FIG. 1. As an example, consider the situation of FIG. 2, where D1 is enabled and is selected for connection to the DATA OUTPUT. Initially, at least one positive transitioning signal must be input to logic circuit 12.sub.L. Note that this signal is sometimes referred to in the art as a monotonic rising signal, meaning is it low during the precharge phase and then rises high during the evaluate phase if the signal is to be considered asserted. The four inversions are then as follows. First, in response to the rising transition in the INPUT, and assuming logic circuit 12.sub.L fully conducts (i.e., assuming that if there are other input signals they also combine to form a conductive path through logic circuit 12.sub.L), there is a falling transition of the voltage at precharge node 12.sub.PN thereby representing a first inversion of the INPUT. Second, the falling transition of the voltage at precharge node 12.sub.PN is inverted by inverter 12.sub.INV to provide a rising transition, thereby representing a second inversion of the INPUT. Third, the rising transition from inverter 12.sub.INV is inverted by inverter INV.sub.1 to provide a falling transition, thereby representing a third inversion of the INPUT. Fourth, the falling transition from inverter INV.sub.1 causes the discharge of precharge node SEL.sub.PN which is then inverted by inverter INV.sub.OUT to provide a rising transition, thereby representing a fourth inversion of the INPUT. Given these four inversions, there arises the problems as discussed earlier as well as additional complexities as will be appreciated by one skilled in the art. In contrast, below are presented inventive embodiments which improve upon these drawbacks while providing a dynamic multiplexer functionality.

FIG. 4 illustrates a schematic of a preferred embodiment of a dynamic multiplexer designated generally at 20 and in accordance with the present inventive scope. Dynamic multiplexer 20 includes data providing circuitry 22 for providing data signals and data selection circuitry 24 for then selecting one of the data signals. As with FIG. 1, therefore, a vertical dashed line generally separates data generating circuitry 22 from data selection circuitry 24 with the former to the left of the dashed line and the latter to the right of the line. Each of these circuits is discussed below.

Data generating circuitry 22 is the same as the prior art data generating circuitry shown in FIG. 1, above. Thus, data generating circuitry 22 includes three separate dynamic logic circuits. However, to facilitate a discussion later of dynamic multiplexer 20 as a whole, new reference numerals are used to discuss the preferred embodiment of FIG. 4. Accordingly, the three dynamic logic circuits of data generating circuitry 22 are labeled 26, 28, and 30. Note that data generating circuitry 22 may include any number of dynamic logic circuits and, therefore, three circuits 26, 28, and 30, are shown in FIG. 4 only by way of example. Given that circuits 26, 28, and 30 are the same as circuits 12, 14, and 16, above, the reader is invited to review the earlier discussion for details which also apply to circuits 26, 28, and 30, while only some of those details are restated below. Also, once again each of circuits 26, 28, and 30 shares various common attributes. Looking to circuit 26 by way of example, it is a known domino logic circuit stage, which includes a precharge transistor 26.sub.PT, a precharge node 26.sub.PN, an output inverter 26.sub.INV, and a discharge path including both a logic circuit 26.sub.L and a discharge transistor 26.sub.DT. Additionally, dynamic multiplexer 20 includes a conductor for providing a CLOCK signal, and the CLOCK signal is connected to the gate of precharge transistor 26.sub.PT and to the gate of discharge transistor 26.sub.DT.

Looking more specifically to the connections of circuit 26, in the preferred embodiment precharge transistor 26.sub.PT is a p-channel transistor which is typically smaller than the n-channel transistors shown in FIG. 4. As discussed later, however, the conductivity type of certain transistors in FIG. 4 may be reversed within the inventive scope. Staying with the current illustration of FIG. 4, precharge transistor 26.sub.PT has a source connected to a source of the system voltage level (e.g., V.sub.DD) and a drain connected to precharge node 26.sub.PN. As noted above, the CLOCK signal is connected to the gate of precharge transistor 26.sub.PT and is also connected to the gate of discharge transistor 26.sub.DT. Discharge transistor 26.sub.DT is an n-channel having its source connected to a low reference voltage (e.g., ground) and its drain connected to a node 26.sub.N. Between precharge node 26.sub.PN and node 26.sub.N is connected logic circuit 26.sub.L. The particular logic of logic circuit 26.sub.L may implement any type of logic equation. For example, often logic circuit 26.sub.L will include numerous transistors connected in various fashions to implement such a logic equation, and the logic function is determined based on the particular transistor configuration as well as the respective input signals connected to the gates of those transistors. For purposes of the present discussion, the particular logic equation and inputs are not important and, thus, the legend INPUTS.sub.26 is generally shown with it understood that such signals may come from any of various other circuits, being static, dynamic, or both. Indeed, note further that if it is known that INPUTS.sub.26 will be disabling during the precharge phase of operation (i.e., and therefore logic circuit 26.sub.L will not conduct during that time), then discharge transistor 26.sub.DT may be eliminated from circuit 26. In any event, once the logic equation formed by logic circuit 26.sub.L is true, at least one conductive path is formed through logic circuit 26.sub.L connecting precharge node 26.sub.PN to node 26.sub.N. Further, recall that the CLOCK signal is connected to the gate of discharge transistor 26.sub.DT, which has its drain also connected to node 26.sub.N. Thus, when the CLOCK is high then discharge transistor 26.sub.DT is also conducting; if this conduction occurs while the logic equation implemented by logic circuit 26.sub.L is true, then the conducting series path along the source/drains of the transistors forms a discharge path from precharge node 26.sub.PN to ground such that the precharge voltage (i.e., V.sub.DD) at precharge node 26.sub.PN is permitted to discharge to ground. Alternatively, if discharge transistor 26.sub.DT is eliminated as suggested above in the case where the INPUTS.sub.26 are known to be non-enabling during the precharge phase of operation, note also that once those INPUTS.sub.26 become enabling, and provided the logic equation formed by logic circuit 26.sub.L is true, then a conductive path is formed through logic circuit 26.sub.L and connects precharge node 26.sub.PN directly to ground, thereby discharging the precharge voltage of V.sub.DD at precharge node 26.sub.PN.

Returning to precharge node 26.sub.PN, it is further connected to the input of output inverter 26.sub.INV. For purposes of noting additional aspects of the preferred embodiment, note that FIG. 4, unlike FIG. 1, illustrates specific details about this output inverter 26.sub.INV (in contrast to inverter 12.sub.INV which is only generally shown in FIG. 1). Specifically, inverter 26.sub.INV is constructed in a known fashion and, therefore, includes a p-channel transistor 26.sub.PINV and an n-channel transistor 26.sub.NINV. More specifically, the source of p-channel transistor 26.sub.PINV is connected to V.sub.DD while its drain is connected to drain of n-channel transistor 26.sub.NINV. These connected drains form the output of inverter 26.sub.INV. The gates of p-channel transistor 26.sub.PINV and an n-channel transistor 26.sub.NINV are connected to one another and therefore provide the input to inverter 26.sub.INV. Lastly, the source of n-channel transistor 26.sub.NINV is connected to ground. Given the configuration of inverter 26.sub.INV, one skilled in the art will appreciate that a low input enables p-channel transistor 26.sub.PINV and thereby causes a high output, while a high input enables n-channel transistor 26.sub.NINV and thereby causes a low output.

Lastly with respect to precharge node 26.sub.PN, note that it is further connected to a p-channel feedback transistor 26.sub.FB from the output of inverted 26.sub.INV. Specifically addressing the connections of p-channel feedback transistor 26.sub.FB, its gate is connected to the output of inverter 26.sub.INV, its source is connected to V.sub.DD, and its drain is connected to the input of inverter 26.sub.INV. Once again, therefore, one skilled in the art will therefore appreciate that once the precharge voltage is no longer connected to precharge node 26.sub.PN, feedback p-channel transistor 26.sub.FB will maintain a high signal at the input of inverter 26.sub.INV so long as precharge node 26.sub.PN is not discharged by its corresponding discharge path.

With respect to circuits 28 and 30, note that their circuit elements are generally connected in the same manner as circuit 26 detailed above, with the exception of the inputs to, and the transistor configurations of, logic circuit 28.sub.L and 30.sub.L, as well as the output of inverters 28.sub.INV and 30.sub.INV as detailed later. Thus, the inputs and outputs are discussed below while the remainder of the circuit details are not re-stated here and the reader is referred to the above discussion of circuit 26 for comparable details.

From the above, one skilled in the art will appreciate that the three dynamic logic circuits of data providing circuitry 22 to the left of the vertical dashed line in FIG. 4 present a total of three data signals. To distinguish these signals from those discussed in connection with the prior art in FIGS. 1 through 3, FIG. 4 (and FIGS. 5 and 6 discussed later) identify these three data signals as D4, D5 and D6, corresponding to circuits 26, 28, and 30, respectively. Each of these data signals D4, D5 and D6 passes through a corresponding inverter to provide complementary signals D4, D5 and D6, to data selection circuitry 24 to the right of the dashed line in FIG. 4.

Turning then to data selection circuitry 24, it includes data inputs I.sub.4, I.sub.5, and I.sub.6 for receiving each of the complementary data signals D4, D5 and D6, respectively. Unlike the prior art, each data input I.sub.4, I.sub.5, and I.sub.6 is not connected to an input of an inverter (e.g., see inverters INV.sub.1, INV.sub.1, and INV.sub.3, of FIG. 1). Instead, and importantly for reasons discussed later, note that each data input I.sub.4, I.sub.5, and I.sub.6 is connected directly to the source of a respective p-channel transistor T4, T5 and T6. The gates of p-channel transistors T4, T5 and T6 are connected to corresponding select signals, designated SEL4, SEL5, and SEL6, respectively. Lastly with respect to transistors T4, T5 and 16, their sources are connected to a precharge node DSEL.sub.PN. Precharge node DSEL.sub.PN is connected to the drain of an n-channel precharge transistor DSEL.sub.PN, which has its gate connected to the output of an inverter INV.sub.CLK, where the input of that inverter receives the CLOCK signal. Also, the source of precharge transistor DSEL.sub.PT is connected to ground. Precharge node DSEL.sub.PN is also connected to the input of an inverter INV.sub.DOUT, which provides the DATA OUTPUT for dynamic multiplexer 20. Lastly, note that INV.sub.DOUT, in opposite fashion to various inverters discussed above, has a short diagonal line in the lower half of the inverter symbol; here, this indicates that inverter INV.sub.DOUT has an n-channel transistor (not expressly illustrated) connected in a feedback manner from the output of the inverter to its input. With respect to the n-channel feedback transistor, its gate is connected to the output of the corresponding inverter, the source of the feedback n-channel transistor is connected to ground, and the drain of the feedback n-channel transistor is connected to the input of the corresponding inverter. One skilled in the art will therefore appreciate that once the precharge voltage of ground (as discussed below) is no longer connected to precharge node DSEL.sub.PN by precharge transistor DSEL.sub.PT (e.g;., during the evaluate phase described below), the feedback n-channel transistor will maintain a low signal at the input of inverter INV.sub.DOUT so long as the precharge node is not discharged to high by its corresponding discharge path.

FIG. 5 illustrates a timing diagram of the operation of dynamic multiplexer 20 of FIG. 4, with a particular example where D4 is selected as the data for the DATA OUTPUT. Before proceeding, as with the earlier timing diagrams note for purposes of simplification that various delays are not shown in FIG. 5 when in actuality the transitions therein are not instantaneous and also note that certain transitions are triggered by other transitions rather than occurring at the immediate same time as shown. Looking then to FIG. 5 and starting at its top, the first signal is the CLOCK signal as connected to various precharge and discharge transistors in dynamic multiplexer 20. Following the CLOCK signal, the next three signals illustrate the voltage levels at precharge nodes 26.sub.PN, 28.sub.PN, and 30.sub.PN, respectively. Again, because the voltage on these nodes is defined earlier as representing data to be provided during the evaluate phase, then these signals are labeled with both the identifier of the precharge node and the corresponding data signal (e.g., 26.sub.PN /D4 indicates the voltage on precharge node 26.sub.PN, which corresponds to the data signal D4). The fifth signal in FIG. 5 shows the voltages at precharge node DSEL.sub.PN of data selection circuitry 24. The sixth signal in FIG. 5 shows the assertion a select signal to choose D4 since that is the example assumed to occur for FIG. 5; thus, this sixth signal shows the value of SEL4 which, as appreciated from the connections of FIG. 4 and the following discussion, is the select signal which is asserted to cause the value of D4 to be connected to the DATA OUTPUT. The seventh and final signal of FIG. 5 shows the value of the DATA OUTPUT.

At t0, the CLOCK signal is low. Therefore, the four precharge transistors in FIG. 5, namely, 26.sub.PT, 28.sub.PT, 30.sub.PT, and DSEL.sub.PT, are enabled. The conduction of the first three of these four transistors causes each of the corresponding precharge nodes, 26.sub.PN, 28.sub.PN, and 30.sub.PN to charge to a high voltage (i.e., to V.sub.DD). In contrast to the prior art, however, note that that the conduction of precharge transistor DSEL.sub.PT causes its corresponding precharge node, DSEL.sub.PN, to precharge to a low voltage (i.e., to ground) rather than to a high voltage (e.g., V.sub.DD). In this regard, note that the term "precharge" is not intended to suggest a non-zero potential, but instead is to indicate a potential, be it positive, negative, or zero, which is brought upon a node during a precharge phase of operation. Thus, the CLOCK signal and the resulting potential at each given precharge node actually defines the precharge phase of operation in the embodiment of FIG. 4, and this phase occurs when the CLOCK signal is low. Given the above, this phase precharges nodes 26.sub.PN, 28.sub.PN, and 30.sub.PN to V.sub.DD and further precharges nodes DSEL.sub.PN to ground. In the preferred embodiment, data selection circuitry 22 may rot be enabled to make any selection during the precharge phase of operation. Therefore, at t0 (i.e., during precharge), all select signals (i.e., SEL4 through SEL6) are not enabling. Because FIG. 5 pertains only to the selection of D4, only SEL4 is shown; moreover, since the selection signals are non-enabling during precharge, then at t0 select signal SEL4 is shown high which is non-enabling to p-channel transistor T4.

At t1, the CLOCK signal transitions from low to high. Therefore, the three precharge transistors of data providing circuitry 22, namely, transistors 26.sub.PT, 28.sub.PT, and 30.sub.PT are disabled. Additionally, this CLOCK transition is inverted by inverter INV.sub.CLK and thereby also provides a disabling low signal to precharge transistor DSEL.sub.PT of data selection circuitry 24. Still further, the high CLOCK signal enables each of the discharge transistors of data providing circuitry 22, namely, transistors 26.sub.DT, 28.sub.Dt, and 30.sub.DT, and also at this time the inputs signals INPUTS.sub.26, INPUTS.sub.28, and INPUTS.sub.30 are asserted to each of logic circuits 26.sub.L, 28.sub.L, and 30.sub.L, respectively. Thus based on the values of these input signals, any of these logic circuits may conduct. For the sake of example, assume that the values of INPUTS.sub.26 and INPUTS.sub.30 are at levels such that logic circuits 26.sub.L and 30.sub.L conduct, while assume further that the values of INPUTS.sub.28 are at levels such that logic circuit 28.sub.L does not conduct. The operation of the three logic circuits under this assumption causes precharge nodes 26.sub.PN and 30.sub.PN to discharge to ground, while precharge node 28.sub.PN remains charged to V.sub.DD. Thus, at t1, FIG. 5 illustrates a transition from high to low for precharge nodes 26.sub.PN and 30.sub.PN, while no such transition is shown for precharge node 28.sub.PN.

Shortly after t1, when the precharge nodes have had time to sufficiently discharge in response to the values of the INPUTS, if they are to discharge given those values, then up to one of the three select signals SEL4, SEL5, or SEL6 may be asserted. Recall that FIG. 5 is directed to an example of asserting SEL4. Thus, at a time t2 shortly after t1, SEL4 is shown to be asserted by transitioning from high to low. Note that SEL4 is an active low signal, meaning it is "asserted" by presenting it low because it is coupled to the gate of a p-channel transistor; thus, note now the effect of this asserted low signal. Particularly, recall that precharge node DSEL.sub.PN has been precharged to ground. Therefore, when SEL4 is asserted low, both the drain and gate of p-channel transistor T4 are low. However, at the same time, the level of D4, which is then low, is inverted by inverter 26.sub.INV and therefore a high signal is connected to the source of p-channel transistor T4. In other words, at this point, the gate-to-source voltage of p-channel transistor T4 is negative, and its absolute value is larger than the absolute value of the negative threshold voltage for p-channel transistor T4; therefore, p-channel transistor T4 conducts. Since p-channel transistor T4 conducts, the precharged voltage of ground at precharge node DSEL.sub.PN is discharged to V.sub.DD, as shown in FIG. 5 at t2. In this regard, note that the term "discharge" is not intended to suggest a resulting zero potential, but instead is to indicate a potential, be it positive, negative, or zero, which may be brought upon a node during an evaluate phase of operation so as to change the potential at that node as compared to its potential resulting from the precharge phase of operation. In any event, given the discharge to a voltage of V.sub.DD, this rising signal is inverted by inverter INV.sub.DOUT and, thus, at the same time (or with some delay which is not shown) DATA OUTPUT concurrently transitions from high to low as shown in the bottom signal of FIG. 5. Thus, the transition at the DATA OUTPUT concludes the last action of the evaluate phase which represents the selection of D4 to the output of dynamic multiplexer 20.

FIG. 6 illustrates a timing diagram of an operational example of dynamic multiplexer 20 in a similar manner to that of FIG. 5, but in FIG. 6 the value of D5 is selected rather than the value of D4. Otherwise, the examples remain the same and, therefore, it is assumed that D4 and D6 are true as realized by logic circuits 26.sub.L and 30.sub.L, respectively, while the value of D5 is false as realized by logic circuit 28.sub.L. Thus, from t0 to t1, the signals are the same as shown above in connection with FIG. 5 and the reader is referred above for additional details. The following discussion, therefore, focuses on the effect starting at t1 given the selection of D5 for output by data selection circuitry 24.

Looking to t1 in FIG. 6, the fifth signal from the top shows that select signal SEL5 is asserted active low at t2, again, having given precharge nodes 26.sub.PN, 28.sub.PN, and 30.sub.PN, time to discharge if they are to do so given the values of the INPUTS to logic circuits 26.sub.L, 28.sub.L, and 30.sub.L, respectively. Since only up to one select signal SEL4 through SEL6 may be asserted for an evaluate phase of operation, then it is assumed although not shown that neither SEL4 nor SEL6 is asserted at t1. Returning to FIG. 4 to examine the effect of asserting SEL5 low at t2, recall that precharge node DSEL.sub.PN has been precharged to ground. Therefore, when SEL5 is asserted low, both the drain and gate of transistor T5 are low. Moreover, at the same time, the level of D5, which is then also high, is inverted by inverter 28.sub.INV and thus a low level is connected to the source of p-channel transistor T5. In other words, at this point, both the gate-to-drain voltage and the gate-to-source voltage of p-channel transistor T5 are zero, and therefore are not negative as is required to cause the p-channel transistor T5 to conduct. Since p-channel transistor T5 does not conduct, the precharged voltage of ground at precharge node DSEL.sub.PN is unaffected, as shown in FIG. 5. Consequently, this constant low signal remains inverted by inverter INV.sub.DOUT and, thus, continuing after t2 DATA OUTPUT remains high as shown in the bottom signal of FIG. 6. Thus, the assertion of the SEL5 signal and the lack of a transition at the DATA OUTPUT concludes the last action of the evaluate phase which represents the selection of D5 to the output of dynamic multiplexer 20.

Given the above, note now various attributes of dynamic multiplexer 20 and its contrast to the earlier-described prior art of FIGS. 1 through 3. Specifically, note that dynamic multiplexer 20 only gives rise to a total of three signal inversions to produce its output whereas, as shown above, the prior art requires four signal inversions. The three inversions of the preferred embodiment may now be seen given an understanding of FIG. 4. As an example, consider the situation of FIG. 5 where D4 is enabled and is selected for connection to the DATA OUTPUT. Initially, at least one positive transitioning signal must be input to logic circuit 26.sub.L. Recall that this signal is referred to in the art as a monotonic rising signal. The three inversions of the preferred embodiment are then as follows. First, in response to the transition in the INPUT, and assuming logic circuit 26.sub.L fully conducts (i.e., assuming that if there are other input signals they also combine to form a conductive path through logic circuit 12.sub.L), there is a falling transition of the voltage at precharge node 26.sub.PN thereby representing a first inversion of the INPUT. Second, the falling transition of the voltage at precharge node 26.sub.PN is inverted by inverter 26.sub.INV to provide a rising transition, thereby representing a second inversion of the INPUT. Importantly, however, note that this rising transition provides a monotonic rising signal which may be used to directly drive the source of p-channel transistor T4; thus, unlike the prior art, an additional inversion is not inserted at this point. Thus, as the third and final inversion of the signal, the rising transition from inverter 26.sub.INV causes the discharge of precharge node DSEL.sub.PN to V.sub.DD, which is then inverted by inverter INV.sub.DOUT to provide a rising transition, thereby representing a third inversion of the INPUT. Given these three inversions, note that they represent a twenty-five percent reduction in the drawbacks of the prior art as described above. For example, there is a reduction in the need to include additional circuitry, and a reduction in the delay and cost of such circuitry. As another example, there is less space required on the semiconductor device used to form dynamic multiplexer 20. Still other advantages will be appreciated by one skilled in the art.

As another consideration of the present embodiment note also that certain prior art considerations actually teach away from the approach of the preferred embodiment. More specifically, it is generally urged in the design of dynamic logic stages that it is undesirable to have series-connections of p-channel transistors, that is, to have the source/drain of one p-channel transistor connected directly to the source/drain of another p-channel transistor. This principle is typically thought to provide better speed performance, or to reduce the size required to construct p-channel transistors. However, note in the preferred embodiment that each connection between a circuit in data providing circuitry 22 and a corresponding circuit in data selection circuitry 24 gives rise to such a series connection of p-channel transistor transistors. For example, recall that inverter 26.sub.INV was earlier detailed, and it was explained that later the purposes for such detail would be explored. It as at the current point that such an illustration is helpful. More particularly, looking to the connection between circuit 26 and the corresponding circuit in data selection circuitry 24, note that the source/drain of p-channel transistor 26.sub.PINV from inverter 26.sub.INV is connected directly to the source/ drain of p-channel transistor T4. Thus, against the teaching of the prior art, there is a direct series connection between the source/drains of two p-channel transistor transistors. However, the present inventor has recognized that such an approach is desirable and beneficial in that it provides the reduced signal inversions described above, and therefore the generally accepted directive against such an approach, as discussed above, is outweighed by the advantages provided by the preferred embodiment.

To provide an alternative embodiment consistent with the present inventive scope, recall it was earlier noted that the conductivity type of various transistors in FIG. 4 may be reversed. Given the detailed operational discussion provided for FIGS. 5 and 6, this aspect may now be better developed and is illustrated in FIG. 7 which depicts an alternative dynamic multiplexer designated generally at 40, and once again having a vertical dashed line separating data providing circuitry 22a to the left of the line from data selection circuitry 24a to the right of the line. In dynamic multiplexer 40, note that the three inversion benefit described above with respect to FIGS. 4 through 6 is once again achieved, but here the conductivity type of each precharge transistor and transistor in the discharge path for all of the dynamic logic paths is changed in contrast to the comparable transistors in FIG. 4. For sake of comparison each of the reference numerals from FIG. 4 are carried forward into FIG. 7 where no change is made to the component, and where an alternative is created by changing the conductivity type of a transistor, the letter "a" is added to the reference numeral as used in FIG. 4. For example, the conductivity type of the transistors in circuits 26, 28, and 30 of FIG. 4 are changed in FIG. 7. As a particular example, circuit 26a includes an n-channel transistor precharge transistor 26a.sub.PT, a p-channel transistor discharge transistor 26a.sub.DT, a logic circuit 26a.sub.L which is understood to include one or more transistors of the same conductivity type as the discharge transistor 26a.sub.DT (i.e., p-channel conductivity type), and an n-channel transistor feedback transistor 26a.sub.FB. The remaining examples for data providing circuitry 22a will be ascertainable by one skilled in the art. Similarly, changes are made to the conductivity types of the precharge transistor and the transistors in the discharge paths of data selection circuitry 24, again adding the letter "a" to demonstrate the alternative in contrast to FIG. 4. For example, the precharge transistor of data selection circuitry 24a is a p-channel transistor DSELa.sub.PT. As another example, the three transistors in the three discharge paths of data selection circuitry 24a are n-channel transistors T4a, T5a, and T6a. Given the change in conductivity types for dynamic multiplexer 40, one skilled in the art will also appreciate that the precharge and discharge voltages are reversed in FIG. 7. In other words, with respect to circuits 26a, 28a, and 30a, the corresponding precharge nodes 26a.sub.PN, 28a.sub.FN, and 30a.sub.PN, respectively, are connected to precharge to ground, and with respect to data selection circuitry 24a, its precharge node DSELa.sub.PN is connected to precharge to V.sub.DD.

Given the above, the operation of dynamic multiplexer 40 may be derived from the comparable operation of dynamic multiplexer 20 of FIG. 4 and, therefore, need not be detailed to the level as shown in FIGS. 5 and 6. Instead, one skilled in the art will appreciate that a discharge in any of circuits 26a, 28a, and 30a causes a precharge node to rise from ground to V.sub.DD, and a discharge of precharge node DSELa.sub.PN causes that node to fall from V.sub.DD to ground. Given these connections, note again that only three inversions are incurred by a data signal passing from any of circuits 26a, 28a, and 30a and then selected to the output of data selection circuitry 24a. This again occurs because any of circuits 26a, 28a, and 30a provides two inversions of the signal as output by a corresponding inverter 26.sub.INV, 28.sub.INV, or 30.sub.INV, but the resulting signal at that point is already configured to provide the correct monotonic transition (i.e., a falling transition in this embodiment) for the source of any of n-channel transistors T4a, T5a, or T6a. Thus, there is no requirement of an additional transition prior to connecting to the source of such a transistor, as was present in the prior art.

As yet another aspect of the present embodiments, and looking to both FIGS. 4 and 7, note another consideration with respect to transistor threshold voltages, as indicated in that some of the transistors of those Figures have an asterisk located by the corresponding transistor symbol while other transistors in those Figures do not. In this regard and looking by way of example to FIG. 4, consider the following. With respect to data providing circuitry 22, note that an asterisk is placed by each of logic circuits 26.sub.L, 28.sub.L, and 30.sub.L to thereby apply to all of the n-channel transistors of these circuits. Conversely, note that no such designation is placed by each of the corresponding discharge transistors (i.e., 26.sub.DT, 28.sub.DT, and 30.sub.DT). With respect to data selection circuitry 24, each of discharge transistors T1, T2 and T3 is marked with an asterisk.

Regarding the meaning of the asterisk, note that in the preferred embodiment the threshold voltage ("V.sub.T ") of each of these asterisk-marked transistors is lower than that of the like conductivity type transistors in the circuit which are not designated with an asterisk. For example, the V.sub.T of p-channel transistors T1, T2, and T3 is lower than the V.sub.T of n-channel transistor 26.sub.PINV. Before detailing the significance of the use of a low threshold voltage transistor versus a high threshold voltage transistor, note that these terms are used to designate the relative values of one transistor's threshold voltage versus another like-conductivity transistor's threshold voltage and are not necessarily limiting those terms to certain absolute values. Particularly, it is known in the art that a transistor's threshold voltage may be determined by measuring its current-voltage characteristics to determine a gate-to-source voltage where the transistor conducts a small amount of current. To demonstrate the relative nature of threshold voltages, consider the following for transistors of like conductivity types. For a first transistor with a first threshold voltage, it will provide a first amount of drive current at a given drain-to-source voltage (with its gate connected to its drain). For a second transistor with a second threshold voltage lower than that of the first transistor, the second transistor will provide a second amount of drive current at the given drain-to-source voltage (with its gate connected to its drain), and which drive current is larger than the first amount of drive current provided by the first transistor at that same drain-to-source voltage. For the remainder of this discussion, a transistor of the first type will be referred to as an HVT transistor (i.e., a transistor with a relatively high V.sub.T) while a transistor of the second type will be referred to as an LVT transistor (i.e., a transistor with a relatively low V.sub.T). Further, note that an HVT transistor preferably has a V.sub.T on the order of that for transistors which are now used throughout a circuit where all transistors share the same V.sub.T, and where that V.sub.T was determined to be high enough to avoid unacceptably large leakage currents. Note also that although an LVT transistor provides the benefit of a higher drive current as opposed to an HVT transistor, in contrast it gives rise to the detriment that it provides a greater leakage current (i.e., when not conducting) than an HVT transistor. Indeed, the typical leaking by an LVT transistor may be greater than that of an HVT transistor by two or three orders of magnitude or more. Lastly, note that the transistor V.sub.T considerations just described as well as additional results from those considerations as detailed below are further explored in U.S. patent application Ser. No. 08/687,800 (Attorney Docket TI-22618), entitled "Dynamic Logic Circuits Using Transistors Having Differing Threshold Voltages", having the same inventor as the current application, and filed Jul. 19,1996, and which is hereby incorporated herein by reference.

Turning now to the effects of including different V.sub.T transistors in the same circuit, the benefits of the mixing of differing threshold voltages may be realized by once again examining the operation of dynamic multiplexer 20, but by now looking more specifically to the effects on that operation due to the differing threshold voltages. Thus, once again the following discussion first involves the precharge phase of operation and then discusses the evaluate phase of operation.

During the precharge phase of operation (i.e., when the CLOCK signal is low in the example of FIG. 4), consider first the transistors in circuit 26. Specifically, discharge transistor 26.sub.DT is off while p-channel precharge transistor 26.sub.PT causes precharge node 26.sub.PN to charge toward a precharge voltage of V.sub.DD. Depending on the values of INPUTS.sub.26, the remaining n-channel transistors of logic circuit 26.sub.L may be on or off. Regardless of those transistors, however, note that discharge cannot occur from precharge node 26.sub.PN to ground because discharge transistor 26.sub.DT is off. Note further that discharge transistor 26.sub.DT is an HVT transistor (it is not marked with an asterisk). As a result, because an HVT transistor has a lower leakage current when off (as opposed to an LVT transistor), then the HVT n-channel discharge transistor 26.sub.DT provides a limit to how much current can leak from precharge node 26.sub.PN, through its corresponding discharge path, to ground. Consequently, even though the discharge path contains some LVT transistors (i.e., the n-channel transistors connected between precharge node 26.sub.PN and ground other than transistor 26.sub.DT), the amount of possible leakage current is limited by the HVT n-channel discharge transistor 26.sub.DT during the precharge phase of operation. Note that the same principle also applies to circuits 28 and 30 as well. Still further, with respect to p-channel transistors, a similar result also occurs. For example, consider the path from precharge node DSEL.sub.PN to p-channel transistor 26.sub.PINV of inverter 26.sub.INV. During the precharge phase of operation, it is known that p-channel transistor 26.sub.PINV receives a non-enabling signal at its gate and, therefore, it does not conduct. Note further that p-channel transistor 26.sub.PINV is an HVT transistor and, thus, it will limit current leakage to a lower level than would an LVT transistor of like conductivity type, such as any of transistors T1, T2, or T3. Thus, to the extent that there is leakage between precharge node DSEL.sub.PN which is precharged to ground and the source of p-channel transistor 26.sub.PINV which is connected to V.sub.DD, this leakage will be lower than if each of the p-channel transistors in this path were LVT transistors.

During the evaluate phase of operation (i.e., when the CLOCK signal is high in the example of FIG. 4), consider again the n-channel transistors in circuit 26. Now, transistor 26.sub.DT is on as may be a series path through logic circuit 26.sub.L (i.e., provided the value(s) of INPUTS.sub.26 are sufficient to enable that path). In other words, recall that precharge node 26.sub.PN at the end of the precharge phase represents a precharged logic state which, in the example of FIG. 4, is a logic high. However, once the evaluate phase begins, the combination of INPUTS.sub.26 may cause all of the transistors, in combination with discharge transistor 26.sub.DT, to electrically connect precharge node 26.sub.PN to ground. In response the charge at precharge node 26.sub.PN discharges to ground and the output connected to the discharged precharge node rises from high to low. During this instance, the transistors making up the discharge path may be thought of as resistors. Note, therefore, since the transistors in logic circuit 26.sub.L are LVT transistors, the resistance of those transistors is significantly less than the resistance of the HVT transistor 26.sub.DT. Since these two resistances are in series, the overall resistance of the discharge path is reduced as compared to a path which included all HVT transistors. Indeed, note this benefit could be accomplished by having only some of transistors in each path (if there are multiple paths) of logic circuit 26.sub.L be an LVT transistor. However, by making all of them LVT transistors, the overall series resistance is still lower than if only one were an LVT transistor while the other(s) were an HVT transistor. In any event, because the overall series resistance is reduced, the time needed to discharge the circuit (and, therefore, change the logic state of the corresponding output) is reduced as well. Once again, note further that a similar result also occurs with respect to p-channel transistors. For example, consider once more the path from precharge node DSEL.sub.PN to p-channel transistor 26.sub.PINV of inverter 26.sub.INV. During the evaluate phase of operation, if both p-channel transistor 26.sub.PINV and transistor T3 are conducting, then a discharge path is formed such that precharge node DSEL.sub.PN may discharge from ground to V.sub.DD. Once again, this path includes transistors of both LVT and HVT types. Thus, the overall resistance of this path is less than it would be if the path included only HVT transistors. Consequently, the discharge speed of the path is improved over a prior art approach of including all HVT transistors.

Given the above configuration, one skilled in the art will readily appreciate that the mixing of transistors with differing threshold voltages provides various benefits. During the precharge phase of operation, the benefit of an HVT transistor in the discharge path is realized in that leakage current is reduced over a circuit having only LVT transistors. Indeed, this leakage should approximate, or be the same as, the leakage of circuits which include only HVT transistors. In opposite fashion, during the evaluate phase of operation, the benefit of one or more LVT transistors in the discharge path is realized in that the speed at which the logic state of the circuit may transition is increased. Lastly, note further some of these benefits also may be achieved through the use of series-connected LVT transistors known to be non-enabled during the precharge phase of operation. For example, returning to circuit 26 of FIG. 4, assume that discharge transistor 26.sub.DT is an LVT transistor, and assume further that one of the transistors in logic circuit 26.sub.L is also an LVT transistor and has its gate connected to an input which is known to be non-enabling during the precharge phase of operation. Given these assumptions, during the precharge phase of operation it is further known that the CLOCK signal is non-enabling to discharge transistor 26.sub.DT ; thus, both discharge transistor 26.sub.DT (assumed to be LVT in the current example) and the LVT transistor in logic circuit 26.sub.L are series connected, and are both off during the precharge phase. Consequently, the amount of leakage current which may pass through this path is less than what would pass if it were to include only a single non-enabled LVT transistor. For a more detailed discussion of the principles and concepts surrounding this aspect, the reader is referred to U.S. patent application Ser. No. 08/683,996 (Attorney Docket TI-23246), entitled "Dynanmic Logic Circuits Using Cascode Transistors Having Low Threshold Voltages", having the same inventor as the current application, and filed Jul. 19, 1996, and which is hereby incorporated herein by reference.

From the above, it may be appreciated that the above embodiments provide numerous advantages. For example, a dynamic multiplexer constructed according to the above inventive scope may be used in various different types of devices, including microprocessors, signal processors, and application specific integrated circuits. As another example, while the above FIGS. 4 and 7 illustrate the electrical connection of two different embodiments, they and are not intended to necessarily limit the physical placement of the schematic components of those embodiments. Thus, in one approach, each of the components of those Figures may be in relative close proximity to one another, while in an alternative approach some of the components may be relatively distant from one another. In this latter regard, by way of example, the components to the left side of the illustrated dashed line may be at one location on an integrated circuit while the components to the right side of the illustrated dashed line may be at a different and relatively remote location on an integrated circuit Indeed, note that the source input connection of the components to the right side of the dashed line provides greater noise immunity and, therefore such connections better withstand longer conductor distances and may thus give rise to distances between the components on both sides of the illustrated dashed line. As still another example, the present embodiments reduce costs associated with prior art configurations, and improve performance as well. Additional advantages have been set forth earlier, and as yet another advantage note that while the present embodiments have been described in detail, various substitutions, modifications or alterations could be made to the descriptions set forth above as demonstrated by the various earlier examples, and still additional considerations as ascertainable by one skilled in the art. Thus, these aspects and the described embodiments are all considered within the inventive scope, as defined by the following claims.