Transconductor for Processing a Very High Frequency Signal

The present invention relates to a transconductor for processing analog signals in the range of very high frequency ("VHF").

Generally, a conventional transconductor for processing audio signals uses Switched-Capacitor of the characteristics of voltage controlled voltage source ("VCVS") to acquire high precision performance. However, in order to process mobile communication signals or VHF image signals, an operational amplifier having a wide bandwidth is needed so that the area of the integrated circuit is increased for this large operational amplifier.

As one of the conventional solutions to the above mentioned problem, a transconductance which uses a voltage controlled current source ("VCCS") is suggested. FIG. 1 shows a circuit diagram of the conventional VCCS transconductor.

However, the overall dynamic range of the conventional transconductor is narrow because the operating point of input terminals of the transconductor is unstable. Further, since the output resistance of the transconductor is small, when this transconductor is used in, for example, a filter, the characteristics of the filter is degraded. Still further, the transconductance of the conventional transconductor can not be adjusted by users.

Therefore, the present invention has been made in view of the above mentioned problem, and the present invention provides a transconductor for allowing a user to adjust the transconductance of the transconductor having wide linear input range and large output resistance.

In accordance with an aspect of the present invention, there is disclosed a transconductor for processing high frequency signals includes an input portion for receiving at least one input signal and generating a primary current in response to the input signal; a programmable bias unit for providing a bias current to the input portion; a current mirror unit for generating a secondary current by mirroring the primary current; and at least one output terminal for providing one or more of output signals in response to the secondary current.

A further understanding of the nature and advantage of the present invention will become apparent by reference to the remaining portions of the specification and drawings, in which:

FIG. 1 is a circuit diagram of a conventional transconductor;

FIG. 2 is a schematic circuit diagram of a transconductor according to the present invention;

FIGS. 3a to 3d are circuit diagrams of a transconductor according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a unit voltage gain amplifier to which the transconductor of the present invention is applied; and

FIG. 5 is a graph which shows the operation characteristic of the unit voltage gain amplifier of FIG. 4.

A detailed description of an embodiment according to the present invention will be given below with reference to the attached drawings.

Now, referring to FIG. 2, FIG. 2 is a schematic circuit diagram of a transconductor according to the present invention. As shown in FIG. 2, the transconductor 200 includes an input portion 202 for receiving input signals Vinp and Vinn, a programmable bias unit 204 for providing bias currents to the input portion 202 in order to implement a linear input characteristic, a current mirror unit 206 for mirroring currents from the input portion 202 in response to the input signals Vinp and Vinn, output terminals 208 for providing output signals Vop and Von in response to the currents generated by the current mirror unit 206 and a feedback unit 210 for feedbacking the output signals Vop and Von to the input portion in order to stabilize the operating point.

Now, with reference to FIGS. 3a to 3d, a preferred embodiment of the transconductor 200 is described in detail, hereinafter.

Referring to FIG. 3a, FIG. 3a is a detailed circuit diagram of the input portion 202. As shown in FIG. 3a, the input portion 202 includes two (2) PMOS transistors P1 and P3 for receiving an input signal Vinp at the gates of them and two (2) PMOS transistors P5 and P7 for receiving an inverted input signal Vinn at the gates of them. The drains of the PMOS transistor P1 and the PMOS transistor P5 are coupled together and the drains of the PMOS transistor P3 and the PMOS transistor P7 are coupled together. The sources of four (4) PMOS transistors P1, P3, P5 and P7 are coupled to the programmable bias unit 204 so that the bias currents generated by the programmable bias unit 204 are provided to them. Further, drains of the PMOS transistors P1, P3, P5 and P7 are coupled to the current mirror unit 206 so that a primary currents I1 is provided to the current mirror unit 206, wherein the primary current I1 is generated by the input portion 202 in response to the input signals Vinp and Vinn.

Referring to FIG. 3b, FIG. 3b is a detailed circuit diagram of the programmable bias unit 204. As shown in FIG. 3b, the programmable bias unit 204 includes a load device portion 300 and a programmable current controlling means 302. The load device portion 300 includes PMOS transistors P9, P11, P13 and P15 of which the sources are coupled to a power supply. The gates of the PMOS transistors P9, P11, P13 and P15 are controlled by a bias current control signal Vbias generated by the programmable current controlling means 302.

The programmable current controlling means 302 is used to allow a user to adjust the transconductance of the transconductor 200 (refer to FIG. 2) of the present invention. As shown in the drawing, the programmable current controlling means 302 includes a variable current generator 304 for generating a current of which the amount is variable in response to a program state defined by a plurality of programming signal pwdn1, pwdn2, pwdn3, . . . , pwdnN provided by the user. Further, the programmable current controlling means 302 also includes a current mirror 306 for generating bias current control signal Vbias by mirroring the current generated by the variable current generator 304.

The variable current generator 304 includes a plurality of NMOS transistors nr1, nr2, nr3, . . . , nrN for respectively receiving the plurality of programming signals pwdn1, pwdn2, pwdn3, . . . , pwdnN at the gates of the NMOS transistors nr1, nr2, nr3, . . . , nrN, wherein the sources of the NMOS transistors nr1, nr2, nr3, . . . , nrN are coupled together. Further, the variable current generator 304 also includes a plurality of PMOS transistors pr1, pr2, pr3, . . . , prN respectively coupled between the NMOS transistors nr1, nr2, nr3, . . . , nrN and the power supply, wherein the drains and the gates of the PMOS transistors pr1, pr2, pr3, . . . , prN are coupled together.

The current mirror 306 of the programmable bias unit 204 is configured as e.g. a conventional Cascode current mirror circuit. The bias current control signal Vbias is generated by a PMOS transistor P17 coupled between the cascode current mirror circuit and the power supply, wherein the gate and the drain of the PMOS transistor P17 are coupled together.

Referring to FIG. 3c, FIG. 3c is a detailed circuit diagram of the current mirror unit 206 includes a plurality of current mirrors 400, 402, 404 and 406 for converting the primary current I1 generated by the input portion 202 into output signals Vop and Von of the output terminals 208. As shown in FIG. 3c, the current mirror unit 206 includes a first current mirror 400 coupled to the drains of the PMOS transistors P1 and P5 of the input portion 202 for generating a secondary current I2 by mirroring the primary current I1, a second current mirror 402 also coupled to the drains of the PMOS transistors P3 and P7 of the input portion 202 for generating a secondary current I2 by mirroring the primary current I1, a third current mirror 404 for providing a current to the output terminal Von by mirroring the secondary current I2 generated by the first current mirror 400, and a fourth current mirror 406 for providing a current to the output terminal Vop by mirroring the secondary current I2 generated by the second current mirror 402. Further, the current mirror unit 206 also includes NMOS transistors N9 and N11 of which the gates are coupled to the first current mirror 400 and NMOS transistors N29 and N31 of which the gates are coupled to the second current mirror 402.

Now, referring to FIG. 3d, FIG. 3d is a detailed circuit diagram of the feedback unit 210. As shown in FIG. 3d, the feedback unit 210 includes a common voltage generator 508 for receiving the output signals Vop and Von of the output terminals 208 as input signals. The common voltage generator 508 includes a first buffer 500 for receiving the output signal Vop, a first resistor 504 coupled to the output terminal of the first buffer 500, a second buffer 502 for receiving the inverted output signal Von and a second resistor 506 coupled to the output terminal of the second buffer 502. The first and second resistors 504 and 506 are coupled together at node N1, so that a common voltage is generated at the node N1.

Further, the feedback unit 210 also includes a voltage comparator 510 for comparing the common voltage with a reference voltage Vref. As shown in FIG. 3d, the voltage comparator 510 includes a PMOS transistor P35 for receiving the bias current control signal Vbias at the gate of it, the source of the PMOS transistor P35 being coupled to the power supply, two (2) PMOS transistors P37 and P43 of which the gates are coupled to the common voltage node N1 and the sources are coupled to the drain of the PMOS transistor P35, and two (2) PMOS transistors P39 and P41 of which the gates are coupled to the reference voltage Vref and the sources are coupled to the drain of the PMOS transistor P35. Further, the voltage comparator 510 includes four (4) NMOS transistors N33, N35, N37 and N39 of which the drains are respectively coupled to the drains of the PMOS transistors P37, P39, P41 and P43 and the gates are coupled together, and four (4) NMOS transistors N41, N43, N45 and N47 of which the sources are respectively coupled to the drains of the NMOS transistors N33, N35, N37 and N39 and the gates are coupled together. Still further, the voltage comparator 510 includes two (2) PMOS transistors P47 and P51 of which the gates are respectively coupled to the drains of the NMOS transistors N43 and N45 and the drains are coupled to the ground and two (2) PMOS transistors P45 and P49 of which the gates are respectively coupled to the drains of the PMOS transistors N35 and N37 and the drains are respectively coupled to the sources of the PMOS transistors N35 and N37. The sources of the PMOS transistors P47 and P51 are respectively coupled to the drains of the PMOS transistors P1 and P5 and P3 and P7 in order to form a feedback loop to the input terminal 202 (refer to FIG. 3a).

Now, the operation of the transconductor 200 is described in detail.

The input terminal 202 of the transconductor 200 of the present invention receives complementary inputs Vinp and Vinn in order to implement linear input characteristic. The inputs Vinp and Vinn should meet the conditions defined as follows;

i) Vinn=-Vinp or

ii) Vinp=V0+vi and Vinn=V0-vi (V0 is a constant)

When the inputs which meet one of the above conditions are provided to the input terminal 202, the currents generated by the programmable bias unit 204 are converted into the primary currents I1. Since the inputs are complementary, the primary current I1 is equal to the difference between the current corresponding to the input Vinp and the current corresponding to the input Vinn, such that both of the currents corresponding the inputs are generated by the PMOS transistors P1, P3, P5 and P7. Therefore, the primary current I1 has the characteristic where the nonlinear elements of the inputs Vinp and Vinn are removed.

Since the amount of bias currents provided to the input terminal 202 can vary as the programmed state of the programmable bias unit 204, the amount of the primary current I1 can also vary as the programmed state. Therefore, the user can change the transconductance of the transconductor 200 by changing the programmed state of the programmable bias unit 204.

Then, the secondary current I2 is generated by the current mirror unit 204 by mirroring the primary current I1 and provided to the output terminals 208 to generate the output signals Vop and Von. If the current generated by the programmable bias unit 204 is increased by the user, the operating point of the output signals Vop and Von rise. Since this rise of the operating point may result in the degradation of the characteristics of the transconductor 200, a reference voltage is needed to maintain the operating point in a proper level. This feature can be accomplished by the feedback unit 210. When the output voltage level is higher than the reference voltage level, the drain voltage of the NMOS transistors N35, N37, N43 and N45 of the feedback unit 210 rises. Therefore, the amount of the currents which flow through the PMOS transistors P45, P47, P49 and P51 is increased and the output voltage level becomes lower and lower so that the operating point is maintained in a proper level.

Now, referring to FIGS. 4 and 5, FIG. 4 is a schematic circuit diagram of a unit voltage gain amplifier to which the transconductor of the present invention is applied, and FIG. 5 is a graph which shows the operation characteristic of the unit voltage gain amplifier of FIG. 4. In this example, the programmable bias unit 204 is programmed to generate a bias current of 80 .mu.A, the power supply is 5V and a sine wave of 1 MHz is used as input signal.

As described above, according to the present invention, a transconductor for allowing a user to adjust the transconductance of the transconductor having wide linear input range and large output resistance is provided.

Although the preferred embodiment of the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and the spirit of the present invention as disclosed in the accompanying claims.