Method for Configuring an FPGA for Large FFTs and Other Vector Rotation Computations

The present invention relates generally to the field of digital signal processing (DSP) in field programmable gate arrays (FPGAs) and more specifically to a method of carrying out complex vector rotation computations, such as large fast Fourier transforms (FFTs), in a single FPGA.

The use of FPGAs for carrying out high speed DPS arithmetic computations has gained recognition in recent years. FPGAs having architectures which include logic blocks having multiple look-up-table function generators, such as the XC4000.TM. family of devices from XILINX, Inc., the assignee herein, are particularly suited for such computations. However, many of the important DSP algorithms are multiply-intensive, and even the FPGAs having the largest number of logic blocks, normally can't embed the multiplier circuits and the attendant control and support circuits in a single chip. It becomes incumbent on the designer to choose efficient DSP algorithms and to realize them with efficient circuit designs. The FFT is an outstanding example of an efficient DSP algorithm and distributed arithmetic is a well established design approach that replaces gate-consuming array multipliers with efficient shift and add equivalent circuits that offer comparable performance.

FFT--The discrete Fourier transform (DFT) of a sampled time series is closely related to the Fourier transform of the continuous waveform from which the time samples were taken. The DFT is thus particularly useful for digital power spectrum analysis and filtering. The FFT is a highly efficient procedure for computing the DFT of a time series and was reported by Cooley and Tukey in 1965 ("AN ALGORITHM FOR THE MACHINE CALCULATION OF COMPLEX FOURIER SERIES" by J. W. Cooley and J. W. Tukey, Math of Comput., Vol. 19, pp. 297-301, April 1965).

It takes advantage of the fact that the calculation of the coefficients of the DFT can be carried out interactively, which results in a considerable savings of computation time. If the time series contains N=2.sup.n samples, then for the N Fourier coefficients the FFT entails 2nN=2N log.sub.2 N multiply operations (assuming a radix 2 butterfly). In contrast, the DFT algorithm requires N.sup.2 multiply operations. The FFT advantage grows as N increases. Thus an 8 point DFT and FFT require 64 and 48 multiply operations, respectively, while an 8192 point DFT and FFT require 67.1.times.10.sup.6 and 212,384 multiply operations, respectively.

Distributed Arithmetic (DA)--Distributed Arithmetic was developed as an efficient computation scheme for digital signal processing (DSP). A United States patent describing this scheme is 1974 (U.S. Pat. No. 3,777,130 issued Dec. 3, 1974 entitled "DIGITAL FILTER FOR PCM ENCODED SIGNALS" by Croisier, D. J. Esteban, M. E. Levilion and V. Rizo. A comprehensive survey of DA applications in signal processing was made by White ("APPLICATIONS OF DISTRIBUTED ARITHMETIC TO DIGITAL SIGNAL PROCESSING: A TUTORIAL REVIEW" by S. A. White, IEEE ASSP Magazine, July 1989).

The distributed arithmetic computation algorithm is now being effectively applied to embed DSP functions in FPGAs, particularly those with coarse-grained look-up table architecture. Practical FIR, IIR and small size FFT designs have been developed. DA enables the replacement of the array multiplier, central to all these applications, with a gate-efficient serial/parallel multiplier with little or no reduction in speed.

DA makes extensive use of look-up tables (LUT's), thereby fully exploiting the LUT-based architecture of the Xilinx and other similarly structured FPGAs. The LUT used in a DA circuit will hereafter be called a DALUT. One can use a minimum set of DALUTs and adders in a sequential implementation to minimize cost. However, speed/cost tradeoffs can be made. Specifically, for higher speed, more DALUTs and adders may be employed. With enough DALUTs and adders, the range of tradeoffs extends to full parallel operation with all input bits applied simultaneously to the DALUTS and an output response generated at each system clock.

Distributed arithmetic differs from conventional arithmetic only in order in which it performs operations. The transition from conventional to distributed arithmetic is illustrated in FIGS. 1, 2 and 3. In FIG. 1 which illustrates conventional arithmetic, the sum of products equation, S=A.cndot.K+B.cndot.L+C.cndot.M+D.cndot.N is implemented with 4 serial/parallel multipliers operating concurrently to generate partial products. The full products are then summed in an adder tree to produce the final result, S. The functional blocks of the serial/parallel multiplier shown in the box of FIG. 1 include an array of 2-input AND gates with the A input derived from a parallel to serial shift register and the K input applied bit-parallel to all AND gates. A P bit parallel adder accepts the AND gate outputs addend inputs and passes the sum to an accumulator register. A divide by 2 block feeds back the register output to the augend inputs of the adder. In each clock cycle one bit of the serially organized data (Ai, Bi, Ci, Di) is ANDed with parallel operands (K, L, M, N) and four partial products are generated. Starting with the least significant serial bits, the partial products are stored in the four accumulator registers. On the next clock cycle, the next least significant bits again form partial products which are then added to the scaled by 1/2 previous partial product. The process repeats on successive clock cycles until the most significant bits have been shifted. When all the partial products, appropriately scaled, have been accumulated, they are fed to the adder array to produce the final output, S. Distributed arithmetic adds the partial products before, rather than after, scaling and accumulating them.

FIG. 2 shows the first embodiment of the distributed arithmetic technique. The number of shift and add circuits is reduced to one and is placed at the output of the array of simple adders, the number of simple adders remains the same. The two-input AND gates now precede the adders.

In a very important class of DSP applications known as linear, time-invariant systems the coefficients (K, L, M and N in our example) are constants. Consequently, the data presented to the shift-and-add circuit; namely, the output of the AND gates and the three simple adders depend only on the four shift register output bits. Replacing the AND gates and simple adders with a 16 word look-up table (DALUT) provides the final form (FIG. 3) of the distributed arithmetic implementation of the sum of products equation.

The DALUT contains the pre-computed values of all possible sums of coefficients weighted by the binary variables of the serial data (A, B, C and D) which previously constituted the second input to the AND gates. Now, with the four serial data sources serving as address lines to the DALUT, the DALUT contents may be tabulated as follows:

In general, the length or number of words in the DALUT is 2.sup.a where "a" is the number of address lines. The width, or number of bits per word cannot be precisely defined; it has an upper limit of b+log 2a due to computation word growth where the coefficients are summed, as the content of the DALUT indicates (wherein b is the number of coefficient bits). The width of the table defines the coefficient accuracy and may not match the number of signal bits (e.g., the bits of A, B, C, and D) which define the dynamic range or linearity of the computation process.

Large FFTs in a Single FPGA--Now that the array multiplier has been replaced by a gate-efficient distributed circuit, there remains a second obstacle to overcome before a large size FFT can be practically embedded in a single FPGA, namely, the large memory required for the sine/cosine basis functions. An 8192 point FFT, for example, requires 8192 basis words and a look-up table capacity of 65,536 is needed for 16 bit accuracy. The Xilinx XC4000.TM. FPGA family with configurable logic blocks (CLBs) articulated as 32.times.1 look-up tables would require 131072/32 or 4096 CLBs. This number is almost double the CLB capacity (2,304) of the XC4062XL.TM. chip, currently the largest device in the XC400.TM. family.

It would be economically advantageous to provide a method for configuring smaller, less costly FPGAs such as the Xilinx XC4025.TM. device to perform 8192 or larger point FFTs and other vector rotations.

Those having skill in the relevant arts, will recognize that the invention hereinafter disclosed has some aspects which may be considered related to vector rotation iterations used in CORDIC processors, wherein CORDIC stands for Coordinate Rotation Digital Computer as disclosed in U.S. Pat. No. 5,371,753, assigned to Kuenemund et al. The CORDIC algorithm is similar to the invention disclosed in that both compute vector rotations 4096 words and cannot be reduced by any known interpolation scheme. A CORDIC FFT processor cannot be realized in a single FPGA.

This invention comprises the gate array implementation of the complex multiplication (x+jy)e-j.theta. where x and y are rectangular coordinates of a complex vector and .theta. is an angle of rotation. Since .theta. is expressed as increments of a basic, resolution angle, .theta.o, it may be written as k.theta.o, where k is an integer. In many applications, k takes on a multitude of values. In the case of the 8192 point FFT, k assumes 4092 values from 0 to 4091, and .theta.o=2.pi./8192. There are accordingly, 4096 values of sine and cosine required for the complex multiplication which constitutes the preponderant FFT butterfly load. A single, large sine/cosine look-up table cannot be embedded in the largest FPGA. By decomposing .theta.(k) into sums of increasingly smaller angle segments, and by using DA computation techniques, the single large sine/cosine look-up table can be reduced to a set of small tables that can be embedded in a mid-size FPGA, such as the Xilinx XC4025.TM. device. The reduced DA look-up tables (DALUTs) of TABLE I bear this out. The complex multiply computations are iterative and are performed in pipelined DA stages that are nearly identical save for their look-up tables which reflect the angle segments.

It is therefore a principal object of the present invention to provide a method for configuring a unitary FPGA to carry out large fast Fourier transforms without requiring off-chip sine/cosine memory.

It is another object of the invention to provide a method for configuring a unitary FPGA with a look-up-table to facilitate the computation of the complex products of vector rotation operations involving a large number of angle values between 0 and 2.pi. radians.

It is still another object of the invention to provide a successive interpolation method for carrying out butterfly computations so that a sine/cosine look-up table and distributed arithmetic circuits could all be embedded in a unitary FPGA and produce large, fast Fourier transforms.

It is still another object of the invention to provide a successive interpolation method for carrying out complex multiplication computations so that a sine/cosine look-up table and distributed arithmetic circuits could all be embedded in a unitary FPGA and produce vector rotations.

The aforementioned objects and advantages of the present invention as well as additional objects and advantages thereof will be more fully understood hereinafter as a result of the detailed description of a preferred embodiment when taken in conjunction with the following drawings in which:

FIG. 1 is a block diagram of a conventional four-product multiply and accumulate circuit;

FIG. 2 is a block diagram of the multiply and accumulate circuit of FIG. 1, but reorganized to reduce the number of shift and add operations;

FIG. 3 is a block diagram of a multiply and accumulate circuit in which a look-up-table replaces AND gates and adders of the circuit of FIG. 2;

FIG. 4 is an FFT Radix 2 Butterfly diagram or computation flow diagram referred to as a Butterfly computation because of the shape of the diagram;

FIG. 5 is a block diagram of the distributed arithmetic data path blocks of an FPGA for computing a Radix 2 Butterfly for a 16 point FFT; and

FIG. 6 is a block diagram of the distributed arithmetic data path blocks of a FPGA for computing a Radix 2 Butterfly for a 8,192 point FFT.

The invention may be understood by first referring to the radix 2 butterfly of FIG. 4. It should be noted, however, that for large transforms, higher order radices (e.g. 4 or 8) may offer greater efficiency--these, too, are amenable to DA implementation. The radix 2 butterfly computations can be expressed as follows:

expanding W.sup.k ;

where X.sub.m and X.sub.n are complex input variables and A.sub.m and A.sub.n are the products of the butterfly configurations.

By substituting Equation 2 into Equation 1b, a sum of products expression amenable to DA solution can be observed in Equation 3b below.

The sum-of-products (or vector dot product) equation wherein each term has a constant (e.g. coefficient) and variable (data) factors, defines the response of linear, time-invariant networks. Notable examples are FIR, and IIR filters and the discrete Fourier transform (DFT) and its efficient offspring--the fast Fourier transform (FFT). Distributed arithmetic is a scheme for computing this sum-of-products without resorting to a full array multiplier. The derivation of the DA algorithm and a FIR filter design example is presented in an article entitled "A DISTRIBUTED ARITHMETIC APPROACH TO DESIGNING SCALABLE DSP CHIPS" by Bernie New in EDN magazine, page 107, Aug. 17, 1995. The multiplier is replaced by shift and add operations--a computation that is serial by multiplier bit (data) and parallel by multiplicand word (the constant factors). This technique is, of course, reminiscent of the software multiply technique of early computers. All of the serially multiplied product terms are computed concurrently; i.e., the partial product is the sum of the partial products of all the terms. The arithmetic sum of all partial products, namely, the sum of all the constant factors logically ANDed with their respective multiplier bits (1's and 0's) for all possible combinations of the multiplier its is stored in a DALUT. A single DALUT serves all multiplier its. Starting with the least significant data bits the DALUT is addressed and its contents stored in an accumulator register. he next significant bits address the same DALUT and its new contents are now added to one-half the previously stored value. The process repeats until the sign bits address the DALUT; its contents are subtracted from the stored sum yielding the response of the network. Thus, DA offers the gate efficiency of serial implementation with performance approaching that of an array multiplier accumulator chip.

The dot product structure amenable to DA solution can be discerned in Equation 3. The x's are the input variables and the sin.THETA..sub.k, cos.sup..THETA..sub.k represent the constant factors. If X.sub.R =(X.sub.Rm -X.sub.Rn) and X.sub.I =(X.sub.Im -X.sub.In) and both serve as address inputs to the DALUT, then the DALUT for the real component of Equation 3b contains all possible combinations of X.sub.Rb COS.sup..THETA..sub.k +X.sub.Ib SIN.sup..THETA..sub.k while the DALUT for the imaginary component contains all possible combinations of X.sub.Rb (-SIN.sup..THETA..sub.k)+X.sub.Ib COS.sup..THETA..sub.k. Here the Xb's denote the multiplier bit values. Thus, for each value of k there are 4 words stored in each DALUT. Consequently, the 32 word CLB can provide the partial product contents for 8 values of .THETA., i.e., k=0, 1 . . . , 7-a 16 point FFT. The DA functional blocks for this 16 point FFT butterfly computer are shown in FIG. 5. The functional blocks consisting of serial adders and subtractors, parallel adders, shift registers, parallel-to-serial-registers, and truth tables (DALUTs) can all be readily configured in Xilinx CLBs. Excluding routing constraints, a total of 104 CLBs is needed. With a 50 MHZ system clock and 16 bit data, a butterfly is computed in 320 nsecs. And with N/2 log 2 N butterflies per FFT, the 16 point FFT can be computed in 10.24 usecs.

Large FFTs

The values of .THETA..sub.k cover the range of 0 to .pi. in increments of 2.pi./N. Thus the 16 point FFT requires only 8 sin/cos values. These values are easily accommodated in a 32 word DALUT by allocating 3 address bits to .THETA..sub.k and 2 address bits to the real and imaginary data components. The .THETA..sub.k address bits cannot be scaled up without an exponential increase in DALUT size. However, by successive interpolation with increasingly smaller increments the DALUT is reduced to manageable size for even 8192 point FFTs. Let .THETA..sub.k =.THETA..sub.k1 +.THETA..sub.k2 +.THETA..sub.k3 +. . . +.THETA.kp with 8 values for each term; i.e., k=0-7 where .THETA..sub.k1 covers 0 to .pi. in .pi./8 increments; .THETA..sub.k2 covers 0 to .pi./8 in .pi./64 increments; .THETA..sub.k3 covers 0 to .pi./64 in .pi./512 increments, etc.

The complex multiply, Equation 1b, now becomes: (((. . . ((X.sub.m -X.sub.n) e.sup.-j.THETA.k1) . . . ) e.sup.-j.THETA.kp. This recursive expression can be implemented as a set of pipelined DA stages similar to the 16 point FFT (FIG. 5). A 16 bit data path (and sin/cos constants) and control functions can be realized with less than 100 CLBs per stage. An 8192 point FFT with 4096 values of .THETA..sub.k (12 address bits) requires only 12/3 or 4 stages--less than one half the CLB capacity of the Xilinx XC4025.TM. FPGA having 1024 CLBs. While one additional DA stage provides the capability to compute a 64K point FFT, the word growth due to computation gain and coefficient accuracy may set this as the practical upper limit for the Xilinx XC4025.TM. chip. However, there are presently several FPGAs having larger CLB capacity including the Xilinx XC4036EX.TM., XC4044EX.TM., XC4052XL.TM. and XC4062XL.TM. devices, as examples.

The data path functional blocks of the 4 stages are shown in FIG. 6. By using flip-flop registers resident in the CLBs, the combinational data flow can be limited to two CLB stages, thereby minimizing interstage timing uncertainties. The CLB count for each stage is indicated. With the total less than 400 CLBs, there are ample gate resources available for all system timing and data path controls as well as all off-chip data buffer address generation.

The basic computation for each successive interpolation stage of FIG. 6 is:

where the first stage is defined by Equation 3 wherein X.sub.R =X.sub.Rm -X.sub.Rn and X.sub.I =X.sub.Im -X.sub.In. For all other stages, the x's are the outputs of preceding stages. With pipelining and with limited combination propagation delays, the 50 MHZ system clock can be retained with the same 320 nsec butterfly computation as the 16 point FFT. Thus, an 8192 point FFT can be computed in 17 msecs.

Distributed Arithmetic, when applied to replace array multipliers and to reduce trigonometric look-up tables by a novel successive interpolation scheme, affords a designer the opportunity to embed large FFTs in a single FPGA. Furthermore, these techniques may also be applied to the synthesis of precision sinusoids and to the design of complex mixers. It will now be understood that the present invention comprises a novel method for performing certain complex computations in FPGAs and other digital signal processing devices. A single FPGA configured for performing large (i.e., N=8,192) FFTs has been disclosed and is implemented by use of a series of successive interpolations with increasingly smaller angular increments for storing values and sums of trigonometric constants in look-up-tables. It will be also understood that the disclosed embodiments are of an exemplary nature and that the inventive method is conducive to even larger and more complex computations not explicitly disclosed herein. Accordingly, the present invention is to be limited only by the appended claims and their equivalents.