System for Transmission and Recovery of Digital Data Using Video Graphics Display Processor and Method of Operation Thereof

The invention relates to a system and method for using a video graphics display processor associated with a processor, such as a PC, to achieve high speed digital data transfer to an external device such as for purposes of backup of memory of the processor.

FIG. 1 illustrates a block diagram of a computing system 10 including associated hardware for providing graphics display capability. The computing system 10 may be a personal computer. Communications in the system are transmitted on bus 11 between the hardware elements described below. The system 10 includes a CPU 12. A disk controller 13 is coupled to bus 11 and to hard drive 14 and floppy disk drive 15. The memory space further includes a dynamic random access memory 16 which is also connected to the bus 11 and which provides high speed reading and writing of data to support data processing performed by the system 10. The memory space is used for diverse functions as known in the art. The hard drive 14 has a much larger storage capacity than the floppy disk 15 and because of its capacity, a substantial time is required for its back up because of the absence of a high speed data port which is available for restoration of the memory space therein. The floppy disk memory 15 is the widely used floppy disk memory for storing information which is processed in accordance with the myriad of functions conventionally performed by the CPU 12. Associated with CPU 12 is a graphics adaptor card 18 which is coupled to bus 11 and which is bidirectionally connected to a video random access memory 19. The video random access memory is also connected to a graphics display processor 20 which continually reads data to be displayed from the video random access memory and formats information for display by a video monitor 22. As is indicated on the video channel 24 by the notation "N", the output from the graphics display processor 20, which is connected to the video monitor 22, is N bits wide which is indicative of the number of bits to produce a color display of a selected number of colors in a color palate encoded by N parallel bits on the N lines of the output 24. The video channel 24 is representative of typically 8 or 24 parallel lines each of which transmits a bit in a word which commands the color encoded by the word to be displayed by the video monitor 22 for each pixel of display data stored in the frame buffer of the video random access memory 19.

The video random access memory 19 functions as a dual ported memory coupled to the bus and graphics display processor which permits the CPU 12 to control writing of information stored in the memory space of the CPU such as that stored in the hard drive 14 while the graphics display processor 20 is retrieving information from the video random access memory for purposes of formatting with appropriate video synchronization information for display by the video monitor 22.

Typically, the graphics display processor is programmed to operate in a graphics mode. For example, the VGA 640.times.480 graphics mode contains a data space of 480 rows (scan lines). Each of the scan lines contains 640 bits (pixels) of information. Each pixel further is displayed with a programmable color specified by the value of the N bits which are outputted by the N parallel lines of the video channel 24. Thus, the video channel 24 can be thought of as transmitting N serial information streams each having a bit value of zero or one which bit values are combined to command the color of display of each pixel displayed by the video monitor 22.

The graphics display processor 20 has first and second frame buffers which function to store information which is outputted by the video random access memory 19 to one of the frame buffers while the other of the frame buffers is driving the display of the video monitor 22 through the outputting of the display formatted data on the video channel 24.

Standard non-interlaced monitors 22 typically refresh data at rates of 60-72 frames. Thus, each serial data stream of the N serial data streams outputted by the video channel 24 has a data rate of approximately 20 megabits per second or more.

The use of the graphics display processor 20 to send display data to the video monitor 22 over a video channel 24 has been well known for many years. The representation of a video image to be displayed on the video monitor 22 is created by the CPU 12 controlling the writing of the data pattern into the video random access memory 19 where it is read by the graphics display processor 20. The CPU 12 creates proper patterns for display from the address space of system memory including data stored in the hard drive 14 and the bootable backup floppy disk memory 15. The graphics display processor 20 repeatedly scans the video random access memory 19 and processes the pattern of information stored and readout from the frame buffer of the video random access memory into the series of data streams having N parallel bits which are outputted on the video channel 24 to produce color pixels of N bit resolution on the video monitor 22.

The video monitor 22 displays the graphical or textual data which has been stored in the memory space of the system 10 and processed by the video random access memory 19 and graphics display processor 20 into a format suitable for display.

Graphics display processors 20 support a variety of video formats. Well defined protocols are known for programming these known variety of video formats.

Currently, the graphics display processor 20 has been developed to perform the single purpose of displaying the data stored in the memory space of the CPU 12 and converting it into a suitable display format for display on the video monitor 22 by the operations performed by the video random access memory 19 and the graphics display processor. The extremely high data rates which are necessary to drive the display of the video monitor 22 at frame rates which are typically, as explained above, between 60 and 72 frames per second have not been applied to other applications which use the video channel 24 as a high speed data output device.

The use of backup procedures to replicate and safeguard information stored in the internal hard drive have become more and more important as the storage capacity of hard drives has rapidly expanded in the last few years. The speed at which backup may be accomplished is a critical factor. As memory drives become larger, the time required to backup the internal hard drive increases. The increased time discourages users from performing backup of the hard drive on a regular basis.

PCs having large internal hard drives and PCs not supporting high-speed I/O devices present a particular problem. Today's laptops with large internal drives are good examples of where backup of data is a problem since the backing up of the stored data must be done either via the parallel or serial port which is present on the PC.

Currently, rapid backup of computer disk information requires the use of internal hardware devices capable of transferring information from the computer's data bus to an external storage device in a compressed or otherwise proprietary format. The most popular techniques available in the order of increasing transfer rates include the following:

(1) Serial communication ports

Serial communication ports typically can transfer data at speeds up to 11.5 K/Bytes per second. Serial ports are included on all PCs, are bidirectional and can be used for both backup and restore operations.

(2) Parallel communication ports

Parallel ports can transfer data at up to 30 K-Bytes per second. Occasionally, some input capability exists, but at much slower speeds dependent on the PC manufacturer's design. Generally, these ports are included on all PCs. Newer designs using parallel integrated circuits allow bidirectional data flow and at higher rates than their predecessors.

(3) Floppy disk drives

Usually, PCs come with at least one floppy disk drive. These devices will support a continuous transfer rate of about 45 K-Bytes per second for large data sets.

The practical transfer rate is limited by mechanical track-to-track access times and the fact that the media needs to be manually changed about after a megabyte has been written. Floppy drives are bidirectional and can be used for both backup and restore purposes.

(4) Floppy/hard disk controllers

Most PCs come with a disk controller capable of supporting both floppy and hard disk drives. The floppy drive controller can support about 300-500 K-Bytes per second in short bursts but not for continuous periods.

The controller is limited by a 16-bit byte count register which requires reloading after 64 K-Bytes have been transferred. The disk controllers are bidirectional and can be used for both backup and restoration.

(5) External or internal magnetic data cartridges

Today, the most popular backup devices use a magnetic data cartridge. These devices either use the PC's floppy disk controller or a separate external or internal interface controller. These devices can maintain about 500 K-Bytes per second without compression or about 1 M-Bytes per second when using compression techniques. These devices are typically optional equipment and cost approximately $200 for 250 K-Byte of backup capability. Both backup and restore are provided with many options for individual and group file selections available. The problem for many PCs, including laptops and palmtops, is that there is no internal space to hold the extra drive and no external connector to allow connection to an external drive.

(6) External or internal disk drives

Occasionally, users will install a second hard drive for the purpose of backing up or replicating data sets. This is the fastest backup technique available today and whenever it is possible, sustained transfer rates in excess 500 K-Bytes per second are easily accomplished.

The present invention is a process for outputting digital data stored in memory space of a computer having a graphics display processor and further, a system for outputting digital data stored in the memory space of a computer which utilizes the graphics display processor to format data originally stored in the computer memory space to produce at least one serial data stream including the digital data stored in the memory space of the computer and clock information which is a function of a clock signal representative of a rate at which at least one serial data stream is outputted by a video channel associated with the graphics display processor for displaying information formatted for display on a video monitor. With the invention, the high data transfer rates on the video channel which are produced by the graphics display processor for displaying display formatted information with a video monitor are used to output information which is not for display purposes, such as, but not limited to, providing information from the computer memory space for processing in a format to provide restoration of the data stored in the hard drive of the computer memory space to perform backup thereof.

The present invention has substantial advantages over the prior art as discussed above as follows. The invention utilizes a graphics display processor to transfer digital data originally stored in the computer memory space to an external device where the data may be processed for diverse applications. The present invention uses the architecture of a conventional computer system, such as a PC, and does not require any additional cost for additional hardware as a consequence of graphics display processors being standard equipment on virtually all PCs. No additional internal hardware is required to perform backup of the CPU memory in accordance with the present invention. No disassembly of the PC is required other than the possible disconnection of the monitor cable. PC backup and restore programs can be stored on a bootable, low-density floppy or other device, such as a PCMCIA card. Co-processor support is not required by a backup program for restoring data of the CPU. Less than 256 K-Bytes of internal CPU memory is used. The backup and recovery of files on a hard drive is possible using the present invention even if the system will not boot from the drive. Furthermore, recovery is possible from damaged boot sectors. The backing up of the memory space of the CPU is easy to use in that all that is required is the insertion of a floppy disk and the turning of the power on. No knowledge is required of the particular type of PC disk controller in use or the encoding format employed by the controller. The only system BIOS disk service used is the "read logical disk sectors" which is provided by all PC BIOS integrated circuits and is not dependent on the operating system. No knowledge of the operating system is required. High sustained data transfer rates such as 921.6 KBytes per second using 60 Hz VGA graphics display formats are possible. A single DOS backup program can be utilized for all Intel-based PCs. The present invention is extendible to systems using microprocessors other than those manufactured by Intel with the interface to the graphics display processors of non-Intel manufactured processors being almost identical to that of Intel-based graphics display processors. The present invention is not dependent upon the memory drive or speed with the invention being based on the video data display rates rather than the speed of an individual CPU or disk drive.

As a result, the dual increase of video rates and the speed of the graphics display processors which is ongoing will not obsolete the present invention. The present invention is especially applicable to backup procedures for replicating and safeguarding information contained on PCs which have large internal hard drives and PCs which do not have high-speeds I/O devices built in, such as today's laptops, which have large internal drives. For example, a 340 M-Byte hard disk may be backed up in under seven minutes using the aforementioned 921.6 K-Bytes per second rate. In accordance with the invention, more information may be backed up than with currently available techniques such as disk partition, boot, and FAT sectors, as well as the deleted files are preserved in the backup copy in addition to all of the normal files. The present invention does not depend on the CPU's operating system or the make or model of the graphics display processor or hard drive in the CPU. In large network installations where giga-bytes of storage are involved, the backup process is generally automated, but can take many hours to perform. The present invention can reduce the time required for backup even in large computer systems of this type.

A processor for outputting digital data stored in a memory of a computer having a graphics display processor in accordance with the invention includes reading digital data from the memory and processing the digital data to produce at least one serial data stream with the at least one serial data stream including the digital data and clock information, the clock information being a function of a clock signal representative of a rate at which the at least one serial data stream is outputted by a video channel; and serially outputting the at least one serial data stream on the video channel under the control of the graphics processor. The at least one serial data stream also includes display information which permits the at least one serial data stream to be displayed by a video monitor connectable to the video channel; processing at least one of the at least one serial data stream after outputting by the video channel to remove the display information from the processed at least one serial data stream; and producing the clock signal representative of a bit rate at which the at least one serial data stream is outputted by the video channel in response to the clock information in the one of the at least one serial data stream. One of the at least one serial data stream contains the clock signal and the display information and another of the at least one serial data stream contains the digital data and the display information or one of the at least one serial data stream includes the digital data with at least a portion of the one of the at least one serial data stream being encoded with self-clocking information which permits the clock signal representative of a rate at which the one of the at least one serial data stream is outputted by the video channel to be derived from processing at least the portion of the one of the at least one serial data stream outputted from the video channel. The invention further includes processing the one of the at least one serial data stream to remove the self-clocking information. The processing the one of the at least one serial data stream to remove the self-clocking information includes converting the one of the at least one serial data stream into parallel digital data having a number of bits corresponding to a number of bits stored at each addressable location of the memory from which the digital data was read.

The at least one serial data stream is outputted in frames formatted for video display, each frame having a set number of lines with each line having bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information; the frames are outputted under control of the graphics display processor on the video channel and stored in another memory; and the frames stored in the another memory are read out from the another memory in response to detection of storing the set number of lines in the another memory. Each frame is stored in one of a first and a second frame buffer of the another memory while another frame is being read out of another of the first and second frame buffer with sequential frames stored in the another memory being read out alternatively from the first and second frame buffers during storing of sequential frames outputted on the video channel. The frames read out from the another memory in response to detection of the storing of the set number of lines in the another memory are stored in a memory of a processing system in response to an interrupt signal produced in response to the detection of the storing of the set number of lines in the another memory.

The at least one serial data stream comprises a sequence of frames with each frame being serially read out as a series of lines under control of the graphics display processor, each line being formatted into a packet, including the clock information comprising a sync field for producing the clock signal, a scan line field for encoding an address of each line within each frame, a trigger field for encoding a number of a frame within the sequence of frames being outputted on the video channel, and a data field containing data from the block of digital data; and wherein each frame is transmitted with a vertical synchronization pulse and a horizontal synchronization pulse is transmitted with each line. The sync field is processed to produce the clock signal; and the sequence of frames are processed with a clock signal to remove the clock information and to convert each packet into parallel information formatted into groups of bits with each group of bits being equal in number to a number of bits stored at each addressable location in the memory from which the block of digital data was read. The sequence of frames is stored in another memory having first and second frame buffers; and when the trigger field changes in magnitude by one indicating storing of a complete frame from one of the sequence of frames in one of the frame buffers of the another memory, the complete frame is read out from the one of the first and second frame buffers and storing of a subsequent one of the frames is begun in another of the first and second frame buffers while the complete frame is being read out. An interrupt is produced in response to the change in magnitude of the trigger field by one; and the interrupt is received by a processing system which initiates storing of the frame read out from the one of the first and second frame buffers in response to the interrupt in a memory of the processing system. The memory of the processing system has first and second processing system frame buffers and the first and second processing system frame buffers store a sequence of frames in response to the interrupt to cause each of the first and second processing frame buffers to alternatively store a frame. The one serial data stream comprises a sequence of frames with each frame being serially read out as a series of lines under control of the graphics display processor; each frame is processed to remove the self-clocking information while retaining the digital data; the processed frames are stored in a backup memory; and the frames stored in the backup memory are read back into the memory of the computer to restore the digital data originally stored in the memory of the computer.

A system for outputting digital data stored in a memory of a computer in accordance with the invention includes a graphics display processor, coupled to the memory, for processing the digital data stored in the memory to produce at least one serial data stream including clock information, which is a function of a clock signal representative of a rate at which the at least one display formatted serial data stream is outputted, and display information for use in controlling a video monitor; a video channel, coupled to the display processor, for outputting the at least one serial data stream produced by the graphics display processor; a data processor memory; and a data processing system, coupled to the video channel and to the data processor memory, for processing the at least one serial data stream in response to the clock information and for removing at least the display information and controlling storing of the at least one of the at least one serial data stream with display information removed in the data processing memory which contains the digital data read from the memory of the computer system. One of the at least one serial data streams contain the clock signal and display information and another of the at least one serial data stream contains the digital data and the display information or one of the at least one serial data stream includes the digital data with at least a portion of the one of the at least one serial data stream being encoded with self-clocking information which permits the clock signal representative of a rate at which the one of the at least one serial data stream is outputted by the video channel to be derived from processing the portion of the one of the at least one serial data stream outputted by the video channel. The invention further includes a storage processor memory; and a storage processor, coupled to the data processing system and to the storage processor memory, for controlling storing of data read from the memory of the data processing system in the storage processor memory in response to the data processing system memory storing a data block of set size. The set size is a full frame of information formatted by the graphics display processor for display by the video monitor. The at least one serial data stream encoded with self-clocking information comprises frames having a set number of lines and bits disposed between periodically occurring horizontal synchronization information with at least a group of bits in each line being encoded with the self-clocking information. Each line is formatted into a packet including a sync field for use in detecting the clock signal and a data field containing the digital data stored in the memory of the computer; and the data processing system comprises a clock, responsive to the sync field, for producing the clock signal and a data separator, responsive to the clock signal and the lines, for removing the self-clocking information and converting the lines into parallel digital data having a number of bits equal to a number of bits stored at each addressable location of the memory of the computer. Each packet further includes a scan line field for encoding an address of each line within each frame and a trigger bit field for encoding a number of a frame within a sequence of frames outputted by the video channel; and each frame is outputted with a vertical synchronization pulse transmitted with each frame at a horizontal synchronization pulse transmitted with each line. The data processing system memory comprises first and second frame buffers; and wherein when the trigger field changes in magnitude by one indicating storing of a complete frame from one of the sequence of frames in one of the frame buffers of the data processing system memory, the data processing system causes the complete frame to be read out from one of the first and second frame buffers and controls storing of another one of the frames and another of the first and second frame buffers of the data processing system memory. The data processing system produces an interrupt in response to the change in magnitude of the trigger field by one; and in response to reception of the interrupt from the data processor, the storage processor initiates storing of a frame read out from the one of the first and second frame buffers of the data processing system memory in the storage processor memory The storage processor memory comprises first and second frame buffers, each storage processor frame buffer storing a frame in response to the reception of the interrupt from the data processing system with the storage processor first and second frame buffers alternatively storing and outputting a frame. The storage processor memory is a backup memory and the storage processor writes frames stored in the storage processor back into the memory of the computer to restore the original digital data.

A system for outputting digital data stored in a memory of the computer in accordance with the invention includes a graphics display processor, coupled to the memory, for processing the digital data stored in the memory to produce at least one serial data stream including the digital data and the clock information which is a function of a clock signal representative of a rate at which at least one serial data stream is outputted; and a video channel, coupled to the display processor, for outputting the at least one serial data stream produced by the graphics display processor. The clock information comprises at least a portion of one of the at least one serial data stream encoded with self-clocking information which permits the clock signal to be derived from processing at least the portion of one of the at least one serial data stream. The at least one serial data stream further comprises display information for use in controlling a video monitor.

FIG. 1 is a block diagram of a prior art personal computing system including a graphics display processor.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is an expanded block diagram of an embodiment of the video data acquisition subsystem 32 and the interface 33, system control, storage processor and memory 34, removable storage 36 and restore function 60 of FIG. 2.

FIG. 4 is a block diagram of the protocol of encoding data for the scan lines of frames outputted by the graphics display processor.

FIGS. 5A-5B, 6A-6D, 7, 7A-7E, 8, 8A-8F, 9, 10A-10C, 11A-11F, 12A-12F and 13A-13F are a circuit schematic of an embodiment of a system for practicing the invention as illustrated in FIG. 3.

Like reference numerals identify like parts throughout the drawings.

FIG. 2 illustrates a block diagram of an embodiment 30 of the present invention. The hardware of the CPU 12, disk controller 13, hard drive 14, floppy disk drive 14, dynamic random access memory 16, graphics adaptor card 18, video random access memory 19, graphics display processor 20, video monitor 22 and video output channel 24 having N parallel lines are identical to the prior art described above in conjunction with FIG. 1. The present invention differs from the prior art in that it utilizes the high speed data outputting capacity of the video channel 24 to process and output at least one serial digital data stream comprised of data stored in the memory space associated with the CPU 12 for applications other than driving a video monitor 22, such as, but not limited to, restoration of data stored within the memory space of the CPU whether in the internal hard drive and/or in the floppy disk drive 15 and/or D RAM 16. The graphics display processor 20 in accordance with the invention outputs at least one serial data stream containing digital data originally stored within the address space of the CPU 12, such as data stored in the hard drive 14 or the floppy disk drive 15 and clock information. The clock information is a function of a clock signal representative of a rate at which the at least one serial data stream is outputted by the video channel 24. The clock information is either an alternating series of one and zero bits outputted on a line of the video channel 24 at an identical rate at which data bits are read out on another line of the video channel or alternatively, at least a portion of each line of each video frame encoded with self-clocking information, such as Manchester code, which may be processed to derive a clock signal as explained below.

Connected in parallel to the video channel 24 is a video data acquisition subsystem 32 as described below with respect to FIG. 3. The video data acquisition subsystem 32 contains a processor and associated first and second frame buffer memories which are periodically used to store frames of information outputted by the first and second frame buffers of the graphics display processor 20 as is described below. The video data acquisition subsystem 32 is connected via interface 33 to a system control and storage processor and memory 34 which also contains first and second frame buffers which store frames outputted by the first and second frame buffers of the video data acquisition subsystem 32. The system control, storage processor and memory 34 writes information into a removable storage 36 which may be used to write information back into the internal hard drive 14 for restoration purposes as described below. The restore block 60 represents a processor used for writing information stored on the removable storage 36 back into the address space of the hard drive 14 of the CPU 12 as is described in detail below.

The present invention uses the programmable capability of the graphics display processor 20 to transmit data via the video channel 24 to the video data acquisition subsystem 32 while maintaining synchronism between the CPU 12, graphics display processor 20, video data acquisition subsystem 32 and system control and storage processor and memory 34. An example of protocols which may be used and the hardware required to receive, process and convert the data which has been formatted into a video display format by the graphics display processor 20 back into its original form as read from the address space of the CPU 12 to provide restoration of the internal hard drive is described below.

The graphics display processor 20 is programmed to operate in a graphics mode. For example, the VGA 640.times.480 graphics mode containing a data space of 480 rows of lines with each containing 640 pixels of information may be utilized. Each of the N parallel lines which are present in the video channel 24, which define the color resolution achievable for display of graphics information on the video monitor 22, has data outputted in a binary state of a one or a zero. The data outputted from the address space of the frame buffers of the graphics display processor 20 associated with the hard drive 14 may be visualized as a linear series of data bits having a length in this example of 307,200 bits per frame (640.times.480). The graphics display processor 20 formats the groups of 307,200 bits per frame which were read from the memory space of the internal hard drive 14 and which are transmitted from the graphics display processor on the video channel 24. During each refresh cycle of the graphics display processor 20, information contained in the video random access memory 19 is continually transmitted to the graphics display processor. The frame rate may be within the conventional range, such as 60-72 per second, which defines the refresh cycle of the graphics display processor 20.

Assuming that there are 60 frames per second, a refresh rate equal to 60.times.307,200 bits per frame is transferred by the graphics display processor 20 over the video channel 24 on each of the N parallel lines. This rate represents a rate approaching two megabytes per second. While it is not necessary in practicing the invention, the video monitor 22 may remain attached to display the data outputted by the video channel 24 which has been retrieved from the address space of the internal hard drive of the CPU 12 and processed for display purposes by the graphics display processor 20. As has been stated above, the video channel 24 is also connected to the video data acquisition subsystem 32. In the preferred application of the invention, only a single serial data stream of the N serial data streams are connected to the video data acquisition subsystem 32 as is described below with that line containing the digital data with at least a portion of the one of the at least one serial data stream connected to the video data acquisition subsystem 32 being encoded with self-clocking information which permits the clock signal representative of a rate at which the one of the at least one serial data stream is outputted by the video channel 24 to be derived from processing at least the portion of the one of the at least one serial data stream outputted from the video channel as described below in conjunction with FIGS. 3 and 4. Alternatively, two lines of the N lines of the video channel 24 may be connected to the video data acquisition subsystem 32 with the first line containing the data which has been retrieved from the address space of the CPU 12 and the display information added by the graphics display processor 20 and the other line containing an alternating series of ones and zero bits at the same bit rate at which data is outputted on the first line which is a clock signal for synchronizing the processing of the data by the video data acquisition subsystem 32.

The video data acquisition subsystem 32 processes the at least one of the at least one serial data stream, including processing of the clock information, to produce the clock signal representative of a bit rate at which the at least one serial data stream is outputted by the video channel to the video data acquisition subsystem in response to the clock information contained in the at least one serial data stream as described below in conjunction with FIG. 3. As is described below, the video data acquisition subsystem 32 further removes the self-clocking information and converts the serially outputted information received on the at least one serial data stream into parallel information having the same number of bits as each addressable location within the address space of the CPU 12. Thus, the video data acquisition subsystem 32 converts the data back into a parallel format have a number of bits per word corresponding to the number of bits of data per word stored within the address space of the CPU 12. The words may have differing number of bits depending upon the architecture of the CPU 12.

Synchronization is maintained between the CPU 12 sending the data to the graphics display processor 20, the graphics display processor sending out video formatted information on the video channel 24 and the video data acquisition subsystem 32 hardware receiving the video formatted information and converting it back into data. Several techniques are employed to establish and maintain this synchronism.

The basic output unit of the graphics display processor 20 is a video frame. The video frame includes all data transmitted between consecutive vertical sync (VS) pulses. VS pulses are distinguished from data by a variety of techniques and are usually defined by a slightly higher (and longer) voltage level. Sometimes, a single connector is used to carry this information to the video monitor 22 and sometimes the information is mixed with data on a single connector (such as sync on green).

The graphics display processor 20 generates VS at the start of each video refresh. In the example described above, VS is generated 60 times each second. With each VS, the graphics display processor 20 sets a bit in a status register in the graphics adaptor card 18. The CPU 12 application program monitors the VS bit and determines the exact time each video refresh cycle begins.

When the video data acquisition subsystem 32 receives VS, it resynchronizes to begin receiving the next set of 307,200 bits sent by the graphics display processor, which represents a full frame of video formatted data, which includes the data retrieved from the address space of the CPU 12, as well as the clocking information and display information, as described below, in conjunction with FIG. 4. The VS alone cannot provide synchronization down to the level of individual pixels. The VS alerts the video data acquisition subsystem 32 to begin pixel synchronization and provides frame synchronization between the CPU 12 and the hardware of the video data acquisition subsystem 32.

The video data acquisition subsystem 32 transfers the video data outputted from the graphics display processor 20 on the video channel 24. The video data acquisition subsystem may be implemented with hardware and software modules for performing specific functions on the data to be transferred. The first module of the software controls the graphics display processor 20 which may be, for example without limitation, pages 1-65 of the attached Appendix. This software is used to read data from the hard drive 14, convert it into the transmission format as described below in conjunction with FIG. 4, and write it into the video random access memory 19. The data is then transmitted using the video output channel 24 from the source CPU 12 to the video data acquisition subsystem 32.

The hardware of the video data acquisition subsystem 32 converts the original data from the formatted video signal and makes it available to the system control, storage processor and memory 34 and signals the processor within the system control, storage processor and memory when a frame of data is ready for transmission thereto. The second module is the software which controls the system control, storage processor and memory 34 which may be, for example, without limitation, pages 66-197 of the attached Appendix, and which functions to transfer data to a removable storage 36 which is a disk or other storage medium. Furthermore, the system control, storage processor and memory may be used to maintain multiple images and to provide a user interface backup and restore operations as described herein.

The video data acquisition subsystem 32 converts the input serial data stream outputted from the video channel 24 back into parallel data having the same number of bits which are read out from each address location in the address space of the CPU 12 and makes the converted data available for storage in the storage of the system control, storage processor and memory 34 and removable storage 36. The input serial video signal is conditioned and converted into a TTL level bit stream by processing performed by input conditioner 38, sync detector 40 and clock recovery circuit 42. The serial data is stripped of framing information, which was applied by the graphics display processor 20 in accordance with the conventional function thereof, and is converted to multiple bit words and held for temporary storage by the data recovery circuit 44 and the data stores 46 as described below in detail. The processed data is outputted alternately in a framed format from the data stores 46 which function as frame buffers. The output from the data stores 46 is applied to the interface 33 which is coupled to the system control storage processor and memory 34. The system control, storage processor and memory 34 is connected to the removable storage 36 which is connected to the restore function 60 as described below.

The input conditioner 38 converts the high speed video signal outputted on the video channel 24 into a digital data stream for processing by the remainder of the video data acquisition subsystem hardware. This function is accomplished in two steps using high speed operational amplifier circuits. The first high speed operational amplifier circuit is used to provide a ground reference to the input video signal from the video channel 24 which may be "floating" with reference to ground of the video data acquisition subsystem 32. A differential amplifier is used to compare the video input signal to the return signal and outputs the difference thereof. After this is accomplished, the processed video signal may be converted to a TTL level. The second operational high speed operational amplifier circuit is in a configuration of a Schmitt Trigger. The Schmitt Trigger allows four separate compare points for high and low transitions to provide a high degree of noise immunity. The use of a Schmitt Trigger is necessary to provide adequate processing when poor quality video input signals are received which are often generated by old or low quality video cards present in the video source system. After signal processing by the input conditioner, a pair of output signals are produced in the form of a Manchester encoded digital bit stream which is suitable for processing by digital electronics as described below.

The clock recovery circuit 42 recovers clocking information from the Manchester encoded bit stream. The clock recovery is accomplished by detecting mid-bit transitions in the data which are present in the Manchester encoded bit stream to provide a clock edge which is slightly delayed from these mid-bit transitions. An edge detector circuit is used to output a short pulse corresponding to each transition in the Manchester encoded data stream. Thereafter, the short output pulses are sent through a pulse blanking circuit which removes all pulses occurring between the aforementioned slightly delayed signal transitions produced by the edge detector. The pulse blanking is important for proper clock recovery and should be stable over time to permit processing of pixel rates produced by the graphics display processor 20 which are commonly in frequencies of between 25 and 32 million pixels per second as measured between blanking intervals.

The sync detector circuit 40 does not modify the Manchester data stream applied thereto as an input and functions to detect the sync signal which is the first 64 bits of each line of the video formatted frames outputted by their video graphics display processor 20 as described below in conjunction with FIG. 4. Once the sync word contained in the first 64 bits of each line of bits is detected in the Manchester data stream, the beginning of a valid formatted line of video has been detected. Once the position of the sync information is detected, a START signal is sent to the data recovery circuit 44 to allow the data recovery circuit to start processing the input bits which are received from the input conditioner 38. The data recovery circuit 44 performs four operations on the Manchester data which is outputted from the input conditioner 38. The first operation is to convert the serial Manchester data stream into a word format having a number of bits identical to the number of bits stored at each addressable location of the address space of the CPU 12. This function is accomplished by strobing bits into a serial to parallel converter with the recovered clock pulses as indicated by the CLOCK output from the clock recovery circuit 42. This processing also strips the Manchester data outputted by the input conditioner 38 of the Manchester encoding of the data. The second operation is to deformat the input lines of video of each frame by stripping off the sync, scan line, control channel and trigger bits as described below in conjunction with FIG. 4. This function is accomplished by routing the bits of each of the fields of FIG. 4 to an appropriate address based upon their position within the scan line having the format of FIG. 4. Frame and line number information are routed to registers used for control of data storage. The third operation is to route the data which is the last field within the line format of FIG. 4 to one of the data stores 46 using an address based on the line number received in the header. Addresses are then incremented for each incoming word until the line is complete. The least significant bit of the frame number is used to determine which of the data stores 40 in which the frame of data will be written. The least significant bit is also routed from the data recovery circuit 44 as the DATA READY signal to the interface 33 to function as a switch between the two data stores during read out. The fourth operation is to signal the interface 33 that the frame is ready for read out which is accomplished by the reception of the aforementioned DATA READY signal.

The data stores 46 are identical and perform identical functions. Each stores one complete frame of video data which has been stripped of all of the bits as described below in conjunction with FIG. 4 except the 512 data bits therein. The two data stores 46 perform the function of frame buffers for read out through the interface 33. Control over which store 46 is to be dedicated to data recovery and which store 46 is to be available for read out is based upon the value of the least significant bit of the frame number. When a data store 46 is dedicated to the data recovery process, data is written into the store using local bus control signals that come from the data recovery circuit 44. When a data store 46 is dedicated to the interface 33, data is read from the store using control signals that come from the interface. A data store may not simultaneously receive data from the data recovery circuit 44 and output the data to the interface 33.

The interface 33 provides access to the DATA READY signal and the data stores 46 to the system control, storage processor and memory 34 as described above. The interface 33 may have different circuit implementations without changing its performance. The interface 33 may be configured in different ways, but it must have sufficient bandwidth to handle the nominal data rate produced by the video channel 24 and to permit the system control, storage processor and memory 34 to respond to the DATA READY signal without any significant time delay. If the entire frame of data is not read out from the video data acquisition subsystem 32 before the next DATA READY signal, unread data will be corrupted by the next incoming frame.

FIG. 4 illustrates an example of a scan line protocol for encoding individual lines of the video formatted frames outputted by the video graphics display processor 20. There are 640 pixels in each of the 480 scan lines which are transmitted in five fields as illustrated in FIG. 4. It should be understood that when Manchester coding is used to encode each bit. Each data bit in each of the fields of FIG. 4 from the address space of the CPU 12 will require two bits to be encoded in a Manchester coded format. The Manchester encoding of each data bit retrieved from the address space of the CPU 12, which is outputted on the video channel 24 under control of the graphics display processor 20, is performed by CPU 12 under control of an application program.

The fields are a scan sync field containing 64 bits, a scan line field containing 32 bits, a control channel containing 16 bits, a trigger field containing 16 bits and a data field containing 512 bits. Thus, because of the use of Manchester coding which requires two bits to encode each data bit in order to provide self-clocking information, the scan sync field will be comprised of 32 bits, the scan line field will be comprised of 16 bits, the control channel will be comprised of 8 bits, the trigger field will be comprise of 8 bits and the data field will be comprised of 256 bits for a total of 320 bits or 40 bytes of actual data.

The scan sync field is optimized to contain a constant pattern of alternating ones and zeros to permit the clock signal to be derived by the clock recovery circuit 42 by permitting a phase lock loop to lock an oscillator to a frequency at which the scan field bits alternate between a one and zero value as described above. The 64 bits in the scan sync field stabilize the phase lock loop of the oscillator within the clock recovery circuit 42 which provides the clock signal on the output thereof to the sync detector 40 with sufficient stability to permit a remainder of each line of a video frame to be processed without further synchronization information. After the initial pixel clock rate is established for each line within the clock recovery circuit 42 by processing the scan sync field, the phase lock loop circuit maintains the video data acquisition subsystem 32 within synchronization for the remainder of the scan line. If synchronization is lost at the end of the line, it will be reacquired on the next line by processing the next 64 bits of the scan sync field.

The scan line field of 32 bits is an address of each scan line in the frame. Numbering starts at zero for the first scan line transmitted following VS. Each scan line address is incremented by one. This technique allows the video data acquisition subsystem 32 to determine the total number of scan lines transmitted with each frame and allows processing when the video frame format is unknown to contain a specified or fixed number of scan lines. The first scan line is detected by the presence of a zero in the scan line field. The line address can also be used to generate addresses at which each scan line's data is stored in the data stores 46.

The control channel of 16 bits provides a mechanism for the program of the CPU 12 to send an "out-of-band" stream of data or control signals to either the video data acquisition subsystem 32 or system control, storage processor and memory 34. With each frame occurring at 60 frames per second, up to eight bits of control information, or data, can be passed to the video data acquisition subsystem 32 and system control, storage processor and memory 34. The high order four bits may be used to interrupt the operation of the storage control, storage processor and memory 34. All eight bits are available to the system control and storage processor 34 as a byte-wide status register. The control channel can be used in numerous ways but the four high order bits can be used to provide an efficient method of identifying the contents of each frame. The four low-order bits can be used to pass data directly to the system control, storage processor and memory 34. Quantities, such as the amount of data remaining, the frame dimensions, the refresh rate, etc., may be encoded with this field.

Frame synchronization is maintained between the CPU 12 and the video data acquisition subsystem 32 for another reason. The CPU 12 controls providing data to the video random access memory 19. The CPU 12 may be able to keep up with the data requirements of the video random access memory 19 and the graphics display processor 20 and therefore send out 307,200 bits per frame as described above. If the CPU 12 cannot keep up with the requirements of the video random access memory 19, the graphics display processor 20 will retransmit whatever is currently in the video random access memory resulting in some frames being sent out more than once. The video data acquisition subsystem 32 must be able to distinguish between new and old frames of data to determine which frames to store and which to ignore.

The trigger field of 16 bits provides the bits necessary for the synchronization. The application program of the CPU 12 increments a counter in the trigger field only when the entire 640 bits.times.480 line frame has been coded and is ready to be transmitted to the video data acquisition subsystem 32. By the time the video data acquisition subsystem 32 receives the trigger field as explained above, it will have already stored the previous frame in its internal memory which includes the data stores 46 which function as first and second frame buffers. As explained above, the video data acquisition subsystem 32 monitors the state of the least significant bit of the trigger field counter maintained by the CPU 12 for changes from one frame to the next. Since the field contains an incrementing counter, the low-order bit toggles between zero and one each time the counter is incremented. As stated above, the dual-ported data stores 46 of the video data acquisition subsystem 32 have two frame buffers with each being large enough to hold an entire 640 bits by 480 line decoded data frame.

Each of the data stores 46 holds a single frame of decoded data. While the state of the trigger bit (the low-order bit and the trigger field) remains fixed, the video data acquisition subsystem 32 continues to overwrite the data in the current buffer with each successive frame. The video data acquisition subsystem 32 stops writing into the current buffer of the data stores 46 with new data and begins writing into the other frame buffer when the trigger bit toggles. As the trigger bit toggles, the video data acquisition subsystem 32 begins writing data from the next frame into the other frame buffer of the data stores 46. When a complete data frame has been stored, a DATA READY signal is sent to indicate that a new data block is available for transfer to the system control and storage processor and memory 34 via the interface 33.

The dual-ported memory in the form of the data stores 46 permits the CPU within the storage control, storage processor and memory 34 to read data from one memory frame buffer of the dual-ported memory while a new data frame is being stored in the other frame buffer and to read and write data into the first and second frame buffers of the system control, storage processor and memory 34 in the same fashion as data is being read and written into the data stores 46. Once a complete frame has been transferred to the system control, storage processor and memory 34 over the interface 33, the two frame buffers of the data stores 46 are interchanged in function and the process is repeated.

If the CPU 12 program causes the trigger bit to toggle after a valid frame has been stored in the video random access memory 19 connected to the graphics display processor 20 and prior to writing the first bit of the next frame, the required CPU 12 to system control and storage processor and memory 34 synchronization is achieved. The CPU 12 program can write as much of the next frame as desired following the trigger bit since the frame buffer switch will take effect before the first data bit of the new frame is stored by the video data acquisition subsystem 32. It is not necessary for the CPU 12 to wait until the storage control and storage processor 34 has received the trigger bit before writing the next frame of data. The graphics display processor 20 performs the transmitting first, followed by the trigger bit and then additional data bits.

The data field of 512 bits in FIG. 4 transfers actual data from within the memory space of the CPU 12. With the video format given in the above example, 480 scan lines times 256 data bits (32 bytes) per line, can be transferred with each frame. Therefore, as stated above, up to 921,600 bites per second can be transmitted from the CPU 12 to the video data acquisition subsystem 32 continuously if the CPU 12 keeps up with the graphics display processor 20. Faster CPU's 12 are capable of performing this task.

One reason a fast CPU 12 may not keep up with the graphics display processor 20 is that, during backup, it has to read data from the hard drive 14 which takes additional time, with several frames being required to perform the complete disk read. This is particularly true when large disk blocks are being read to optimize the disk I/O. While the CPU 12 is accessing the hard drive 14, calibration data can be continuously sent to the storage control and storage processor and memory 34 for validation. The storage control and storage processor and memory 34 will differentiate between calibration data and valid CPU data by the contents of the control field. If calibration data is found to be incorrect, the operator must be notified by the storage control and storage processor 34 so that the backup process can be terminated. By sending calibration data every time the hard drive 14 is accessed, the validity of the backup is periodically checked throughout the entire backup process.

If frame by frame calibration is desired, the low-order four bits of the control field can be used. This allows for validation of the control field but, does not validate bits in other regions of the scan line, such as the data field.

Furthermore, the first and second frame buffers of the data stores 46 provide temporary storage and synchronization between the video data acquisition subsystem 32 and the system control, storage processor and memory 34. The system control, storage processor and memory 34 must be sufficiently fast to keep up with the average data transfer rate thereto but may at times be unable to keep up with each transmitted individual frame while storing data in its storage device. The use of first and second frame buffers in the system control, storage processor and memory 34 allows the capture of data sent to it. This is sufficient to keep up with the video data acquisition subsystem 32.

When the video data acquisition subsystem 32 notifies the system control, storage processor and memory 34 that one of the data stores 46 is ready to transfer data, the system control and storage processor will transfer the contents of one of the data stores 46 of the video data acquisition subsystem 32 to its own frame buffer space which is comprised of first and second frame buffers and block it for optimal output to the removable storage 36. The first and second frame buffers of the system control and storage processor and memory 34 function in the same fashion as the data stores 46 which function as frame buffers of the video data acquisition subsystem 32 which allow one frame buffer to be written into while the other is being filled and outputting information to the removable storage device 36.

The system control, storage processor and memory 34 includes a set of input/output registers to allow the CPU therein to control operating parameters within the video data acquisition subsystem 32 and to monitor its status. Parameters such as the approximate video formats expected and the number of bits in each field of the data packet format of FIG. 4 can be passed from the system control, storage processor and memory 34 to the video data acquisition subsystem 32 to allow adapting to a wide variety of PCs.

The restore block 60 functions to perform restoration as follows. When the backing up of files of the CPU 12 is required, the format of the backup data stored in the removable storage 36 is important. The format used allows the original CPU 12 internal hard disk drive to be reconstructed on a file-by-file basis or to have the entire disk restored as a bit image. Two methods may be used to perform this task. In the first method, the data written into the system control, storage processor and memory 34 represents an exact image of the original data stored in the disk of the CPU 12. The PC restore program executed by block 60 uses a PC-based device driver to map individual disk read commands into the disk read commands required to read each sector off of the removable storage 36 as though it still resided on the original CPU 12 disk. The second method also uses data written in the removable storage device 36 which is an exact image of the original CPU 12 disk partition. The program executed by the block 60 uses a driver which processes the removable storage 36 as an extended partition of its own containing one or more logical drives. The user will be able to change to the direct logical drive and allow the operating system to read the files directly as though there were files contained by that operating system.

The storage control, storage processor and memory 34 is a fast general-purpose single card computer containing associated memory and further functioning to store collected data on removable storage 36 or to transmit the data by a communications channel (not illustrated) to support diverse applications for the data stored in the internal hard drive 12. Pages 66-197 of the Appendix contain a computer code listing that in association with the circuit schematic of FIGS. 5A-5B, 6A-6D, 7A-7E, 8A-8F, 10A-10C, 11A-11F, 12A-12F and 13A-13F are an embodiment of the present invention. Furthermore, pages 1-65 contain a computer code listing which may be used to control the graphics display 20 which functions in conjunction with the remaining parts of FIG. 3 including the system control, storage processor and memory 34 to practice the present invention. The system control, storage processor and memory 34 is responsible for setting up the mode of operation of the video data acquisition subsystem 32 and monitoring the progress of the backup operation when original data stored within the memory space of the CPU 12 is being restored. The system control, storage processor and memory 34 monitors the amount of data transmitted and computes the estimated time to complete the backup process. The system control, storage processor and memory 34 stores all the collected data and validates calibration data. When operator feedback is utilized, the system control, storage processor and memory 34 is responsible for the generation and formatting of user messages.

As has been stated above, while a preferred embodiment of the present invention, as described above in conjunction with FIG. 4 utilizes the scan sync field to produce the local clock signal necessary for completing processing of the transmitted at least one serial data stream into parallel data having the same number of bits as the number of bits stored in each addressable location of the CPU 12 memory, it is also possible to transmit on one line of the video channel 24 data which has not been formatted with self-clocking information and to transmit on another line of the video channel an alternating sequence of ones and zeros at the same bit rate as the data on the one channel for the purpose of functioning as a clock recovery 42 to be applied directly to the data recovery 44.

While the invention has been described in terms of its preferred embodiments, it should be understood that numerous modifications may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims. It is intended that all such modifications fall within the scope of the appended claims. ##SPC1##