IBM PC Compatible Multi-Chip Module

This invention relates to a multi-chip module.

The most successful applications of computer technology have been those that people do not see. Microcontrollers and microprocessors govern automotive anti lock braking systems, automatic teller machines, elevators, subway ticket systems, and medical equipment. These systems which include hidden computers, otherwise known as embedded systems, permeate our lives.

The area of greatest growth in the embedded control market is the segment of ultra-miniature controllers for portable and transportable instruments. Original Equipment Manufacturers (OEMs) have indicated a strong interest in developing products with the personal computer (PC) architecture, but have found that size, integration, power, reliability, or cost constraints make existing broad-level products unsuitable for their applications.

The reduced size and increased complexity of integrated circuits have made it possible to design and construct embedded computer modules of remarkably small form factors. However, the mere combination of processing functions in a small package has not heretofore been accompanied with a corresponding high level of functional integration. As a result, such embedded computer modules have been limited in a number of respects.

For example, in order to communicate with and control the embedded computer modules in a development or maintenance mode, it is necessary to include numerous connector pins, external jumpers, and the like, which have no useful function in an operational mode. This tends to limit the ability of the designer to reduce the size of the embedded computer module due to the need to include the additional connector pins, connectors, jumper pins, etc. on the embedded computer module and on the printed circuit board on which the embedded computer module is mounted. This can also affect the reliability of the embedded computer system, particularly in applications in hostile environments (e.g., shock, vibration, etc.), and introduces unwarranted complexity in the OEM's design.

In another respect, because embedded computer components are typically designed for applications which do not have the usual complement of external input/output (I/O) devices found in desktop PC applications, or do not have sufficient redundancy or backup devices and modes, it is often cumbersome to diagnose and/or recover from otherwise non-fatal fault conditions in the embedded computer.

There is a need to provide an embedded computer with a high level of functional integration, with a reduced number of connector pins, connectors and jumper pins, and with sufficient redundancy and backup modes and devices to facilitate operation of the embedded computer in an operational mode, in diagnostic and maintenance modes, and to facilitate recovery from fault conditions.

It is an object of the invention to incorporate a multi-chip module in an ultra-miniature form factor. In particular it is an object of the invention to provide a module the size of a large integrated circuit.

It is an object of the invention to provide a multi-chip module with a high level of functional integration while having a reduced number of connector pins, connectors and jumper pins.

It is an object of the invention to provide a multi-chip module with sufficient redundancy and backup modes and devices to facilitate the operation of the multi-chip module in an operational mode, in diagnostic and maintenance modes, and to facilitate recovery of the multi-chip module from non-fatal fault conditions.

It is an object of the invention to provide a multi-chip module with a fail-safe feature wherein the module comprises both a read only memory (ROM) chip and a flash memory chip in which both chips comprise a basic input/output system (BIOS) program, and wherein, under normal operating conditions the flash memory serves as the source of the BIOS program, and, if the flash memory should become erased or otherwise corrupted, the ROM can serve as the source of the BIOS program and allow the flash memory to be reprogrammed.

It is an object of the invention to provide an Intel X86 compatible computer module and peripheral controller modules wherein the computer module includes a CPU, I/O (a parallel port and two serial ports), a keyboard interface, a dynamic random access memory (DRAM) interface, floppy disk controller, hard disk controller, and flash disk functions based on an Intel X86 architecture. Specifically, it is an object of the invention to provide a multi-chip module that provides an OEM with the facility for incorporating a feature set that is compatible with IBM PC/AT hardware, software, and bus pin configuration.

It is an object of the invention to provide a module having low power consumption, broad thermal adaptability, low cost, and high reliability by eliminating cables and mounting hardware.

It is an object of the invention to provide a computer module having a connector pin layout which is organized to facilitate the design of OEM printed circuit boards to interface the computer module with other modules mounted to the printed circuit board.

It is an object of the invention to provide a module family having identical Industry Standard Architecture (ISA) bus pin configurations to facilitate easy interconnection.

According to the invention there is provided a multi-chip module comprising a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs, and a plurality of module pins secured in a single row along the periphery of the substrate and connected to the inputs and outputs. The module pins include a set of 94 contiguous pins which pins define an ISA bus means. Of the 94 contiguous pins comprising the ISA bus means, 88 pins comply in number and signal type with corresponding signal pins specified in IEEE-P996 and ISA specifications. The ISA bus means further includes three pins allocated to additional signals, two ground pins, and a power pin. The three additional signals include DRQ2OUT--which is a floppy disk direct memory access (DMA) request and may be coupled to DRQ2, IRQ7OUT which is a parallel port interrupt request and may be coupled to IRQ7, and IRQ6OUT which is a floppy disk interrupt request and may be coupled to IRQ6. The ISA bus means will hereinafter be referred as to as the ISA bus.

Table 1 lists the signal and power connections comprising the ISA bus of the multi-chip module of the invention. The first column lists mnemonics representing the signal and power connections. The second column lists the standard ISA connector pins corresponding to the respective signal and power connections. The third column lists the corresponding respective connector pins employed in a preferred embodiment of the multi-chip module of the invention. There is no corresponding ISA pin shown for the three additional signal pins, the two ground pins and the power pin.

The multi-chip module can be rectangular in shape, having a first side, a second side opposite the first side, a third side, and a fourth side, and is defined by an upper surface, a lower surface, and a peripheral wall, and wherein a plurality of pins extend from the peripheral wall.

The ISA bus pins preferably extend along the first side and at least partially along the third and fourth sides. The multi-chip module can include 240 module pins. In a preferred embodiment, the 94 ISA bus pins, as defined herein, are numbered from 38 to 131, inclusive, as shown in Table 1. It is understood that the 94 ISA bus pins may be numbered in reverse order, for example from 131 to 38, or from 203 to 110 (with all 240 pins numbered in reverse order) or between any two numbers, in ascending or descending order, as long as the 94 ISA bus pins are contiguous and extend along a first side and at least partially along two sides bounding the first side. In a preferred embodiment, 70 of the ISA pins extend along a first side of a multi-chip module, and 12 pins extend along each of the two sides bounding the first side, thereby forming a contiguous set of 94 ISA bus pins.

The functional circuits in a multi-chip module of the invention can include a central processing unit. The functional circuits can further include two serial interfaces, a parallel interface, a hard drive interface, a floppy disk interface, a keyboard interface, and flash memory.

Other multi-chip modules of the invention can include functional circuits that include a PCMCIA interface, an Ethernet interface, or a display controller.

The substrate can comprise a printed circuit board and the functional circuits comprise semiconductor devices which can be packaged or can be in bare die form secured to the printed circuit board.

Further, according to the invention, there is provided a multi-chip module comprising a plurality of functional circuits encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side; and a plurality of pins extending laterally from the peripheral wall, wherein the pins include a set of 88 ISA bus signal pins, three additional signal pins as described above, two ground pins and a power pin. The 94 pins defining an ISA bus means, the 88 ISA bus signal pins of which comply in number and signal type with the corresponding signal pins specified in IEEE-P996 and ISA specifications.

Still further, according to the invention, there is provided a module family comprising a plurality of functionally different modules, wherein each module has a plurality of pins and the pins of each module include a set of 88 ISA bus signal pins, three additional signal pins as described above, two ground pins and a power pin. The 94 pins defining an ISA bus means, the 88 ISA bus signal pins of which comply in number and signal type with the corresponding signal pins specified in IEEE-P996 and ISA specifications.

Each module can comprise at least one functional circuit encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side, and wherein the pins of the module extend laterally from the peripheral wall.

In a preferred embodiment, the multi-chip module comprises a read only memory (ROM) chip and a flash memory chip. The ROM includes instructions comprising a basic input/output system (BIOS). A BIOS is preloaded in the flash memory chip. Under normal operating conditions, a jumper is set to select the flash memory to serve as the source of the BIOS program. However, if the flash memory should become erased or otherwise corrupted, the jumper may be set to select the ROM as the source of the BIOS program. This feature is new in embedded computer modules and allows the module to be packaged without the need to have all the flash memory pins externally accessible. With a simple change of a jumper connection, the module can be initialized from the ROM, and the flash memory can then be reprogrammed.

Embedded computer modules may be operated in one of several modes, e.g. an operational mode, a download mode and a redirection mode. It is known in IBM PC compatible computers to set up jumper connections to establish the desired operational mode. During initialization, the processor tests the jumper connections, and sets up its operation and communications accordingly. However this approach requires many jumper pins which have a limited use, and typically have no useful function in an operational mode.

This problem is solved in a preferred embodiment of the multi-chip module which can use a connector coupled to a serial port to determine in which mode the module should operate. In an operational mode, a serial port connector may be coupled to a serial port of the multi-chip module, with the serial port connector wired to carry on normal serial communications. In other modes, serial port connectors alternatively coupled to a serial port of the multi-chip module may have particular pins wired in configurations which indicate to the processor that the module should operate in corresponding respective modes. Remaining pins in the connector are then used to conduct the serial communication in the selected mode. This is a feature not previously known in the use of embedded computer modules. This feature again permits the use of an multi-chip module having a reduced number of connectors, connector pins and jumper pins. This feature helps simplify the design of the printed circuit board upon which the multi-chip module is mounted and the reliability of the resultant embedded computer system.

The multi-chip module may include an internal DRAM. However, in some applications, OEMs may require additional external DRAM. If the size of the internal DRAM is not compatible with the size of the external DRAM (for example, 4 Mbytes internal and 16 Mbytes external) it would be necessary to disable the internal DRAM. In a preferred embodiment, the multi-chip module includes a programmable logic array (PAL) which can be used to enable or disable electronic drivers. By setting the state of a flip-flop in the PAL, the multi-chip module can be set up to disable the internal DRAM and operate with the external DRAM. During initialization of the multi-chip module, the flip-flop in the PAL is set or reset, as the case may be, thereby setting up the DRAM configuration.

Information regarding the configuration of the multi-chip module may be stored in the main complementary metal-oxide semiconductor (CMOS) memory. However, CMOS memory is volatile, i.e. the contents of the memory are lost when power is removed. Therefore, it is known in applications using CMOS memory, to use a backup battery to keep the CMOS memory powered, even in case of a failure of the main source of power. In a preferred embodiment of the multi-chip module of the invention, such configuration information, and any other necessary information may be stored in a designated area of the flash memory. The multi-chip module may be completely powered down, and the flash memory will retain the required data and be prepared to support subsequent initialization and operation of the module.

FIG. 1 is a plan view of a multi-chip module of the invention;

FIG. 2 is a side view of the module of FIG. 1;

FIG. 3 is a block diagram of a multi-chip module of the invention;

FIGS. 4A and 4B are a schematic representation of an embodiment of a multi-chip module of the invention indicating the configuration of the pins;

FIG. 5 shows a PC board layout for a development board showing the mounting site for the module of FIG. 1, and

FIG. 6 is a schematic representation of a number of different modules in accordance with the invention coupled to each other by means of their ISA buses to form a module family of the invention.

FIG. 7 is a flow chart representing a power on self test (POST) initialization sequence of a module of the invention.

FIG. 8 is a flow chart illustrating BIOS program selection and loading in accordance with the invention.

The present invention has been developed to address problems in the prior art by providing a multi-chip module packaged to resemble a large integrated circuit chip comprising a 240 pin QFP, in one embodiment having an overall footprint of 59.54.times.79.88 mm. The module includes a set of pins constituting a bus for connection to the OEM designer's proprietary internal hardware. The invention specifically contemplates providing this bus with a configuration complying with the ISA specification. This allows the OEM designer quickly to incorporate IBM PC/AT hardware and software and to implement the module in ISA compatible proprietary product designs. The module is now described in greater detail with reference to FIGS. 1 and 2 which show a plan view and a side view, respectively, of the module.

The module 10 is a 240 pin QFP with gull wing pins having a 0.762 mm. pitch. In the embodiment shown, the body is rectangular, the one side of which measures 76.2 mm and the overall footprint in this embodiment being 59.54.times.79.88 mm. The pins themselves are typically 0.5 mm wide, and the dimensions of distances 12 and 14 in FIG. 1 are 3.5 mm for this embodiment. By using a chip-like package in which the pins are formed around the periphery of the module 10 in a single row as illustrated in FIGS. 1 and 2, the module 10 can easily be soldered into place to form a very sturdy, reliable set of connections. Furthermore, tracks can be designed to lead directly from the pins to another device by making use of PC board tracks on one or both surfaces of the PC board without the need for several layers to route the various tracks. Since the pins are soldered directly to the interconnecting tracks, the system has inherent reliability in that it eliminates cables and mounting hardware that could otherwise vibrate loose. As many as half a dozen interconnecting cables, assorted connectors and mounting hardware required with many existing prior art single board computers, are thereby eliminated.

The module provides an Intel X86 compatible computer in an ultra-miniature form factor that can be integrated as easily as a semiconductor device and provides the full functionality of a desk top computer. As is described in greater detail below, the same concepts of using a chip-like module using a QFP package with gull wing pins and having an ISA compatible bus is extended also to peripheral controller modules.

By integrating a full X86 AT-compatible computer onto a proprietary OEM design, the need for multiple boards is eliminated, thereby eliminating cables and mounting hardware.

The full compatibility with PC-AT ISA allows for easy integration with low-cost hardware peripherals. The ISA-compliant bus makes it easy to interface with proprietary hardware design.

One embodiment of the module 10, having a CPU as one of its functional circuits, is illustrated in FIG. 3 and includes standard I/O interfaces, e.g. serial ports, a parallel port, and floppy and hard disk interfaces allowing standard hardware, cables, and software libraries to be incorporated in the design. The module 10 includes an 80386 SX CPU 20 which is connected to a DRAM bus 22 and an ISA bus 24 by means of core logic 26. The core logic controls AT-compatible DMA controllers, interrupt controllers, and timers/counters. The core logic also controls the AT keyboard controller 28 and the real time clock 30. Two serial ports 32, 34 and a parallel port 36 are provided, as are a floppy disk controller 40, an IDE hard drive interface 42, and ROM 43. In order to facilitate total solid state operation, internal flash memory 44 is provided, and is controlled by a solid state flash disk controller 46. Power is controlled by means of a power monitor 48 which provides a power saving function by controlling CPU sleep modes, and by a watch dog timer 50. The watch dog timer 50 monitors CPU cycles to detect interrupts in the cycle thereby allowing the system to be automatically reset after a predetermined time delay.

The microprocessor and various controllers and interfaces comprise chips, optionally in die form, mounted on a multi-layer PC board, e.g. ten-layers. The CPU 20 can be a standard 33 MHz 80386 SX CPU having a DRAM controller for supporting up to 16 M bytes of DRAM. Alternatively, CPU 20 can be another standard microprocessor chip such as another type of 80386 chip or die, a 80486 chip or die, a Pentium chip or die, or any other desired microprocessor which is capable of providing the function of the X86 device.

The standard DRAM interface provides all the signals for connecting standard page-mode DRAMs of various configurations, including standard 8- and 9-bit 30-pin SIMM modules and discrete components, such as standard 1M.times.4 and 4M.times.4 DRAM chips. The interface is designed to support 70 ns or faster DRAMs.

The DRAM interface consists of: Multiplexed addresses MA00 to MA10; Bi-directional data D0 to D15; Column Address Strobes CASL0- to CASL3- (low byte), and CASH0- to CASH3- (high byte); Row Address Strobes RAS0- to RAS3; and Memory Write Strobe DRWE-.

The serial ports 32, 34 are PC-compatible asynchronous serial ports, typically treated as COM 1 and COM 2 devices by DOS, and are shown in Table 2.

Either or both serial ports can be disabled using SETUP. When disabled, a port's I/O address and interrupt are made available for other expansion devices on the PC bus.

A full complement of input and output handshaking lines are supported by the serial ports, and all serial port signals are at standard LSTTL levels. In another embodiment, RS232C signal compatibility can be achieved by including a TTL-RS232C level converter to provide the necessary bipolar signal levels.

The parallel port, shown in Table 3, is a fully-compatible PC/AT parallel port providing bi-directional operation. It is typically used to support a line printer.

Pull-up resistors, e.g. 4.7 K-ohm (+5V), are typically provided to the following parallel port signals: STRODE-, SLIN-, INIT- and AUTOFD-.

Generally, if the parallel port will be connected to a cable for high speed data communication (as opposed to static digital output levels or static TTL level sensing), certain signals require 2.2 nF capacitor connected to ground. These include PD0 to PD7, and STRB-.

Parallel port registers are provided for the parallel port as shown in Table 4.

The DOS-compatible floppy drive interface 40 allows cable connections for up to four floppy drives. In PC-compatible systems, the BIOS and DOS support two drives. These are configured using the BIOS SETUP function. Hardware controls for two additional drives provided.

The floppy drive interface supports the following standard floppy formats:

The various floppy interface resources are listed in Table 6:

Outputs to the floppy drive and from the floppy drive are open collector. Pull-up resistors are therefore required for proper termination, both on the circuit board and one of the attached floppy drives (but not both).

Pull-up resistors, for example 330-ohms, are required for the following floppy interface signals: DSKCHG-, RDATA-, WRPRT-, TRK0-, and INDEX-.

The pin numbers and functions associated with the floppy drive are listed in Table 7.

The IDE hard drive interface 42 is a standard interface used in PC-compatible systems for hard disk drives. Up to two drives can be connected in a master-slave arrangement. The IDE hard disk drive resources are listed in Table 8:

The IDE interface pins are arranged to easily attach to a male PC-mounted ribbon-cable connector, with the IDE drives typically being attached to the drive interface using a 40-pin ribbon cable.

The pin configuration for the IDE interface is shown in Table 9.

The pin configuration for one embodiment of the entire multi-chip module 10 is illustrated in FIGS. 4A and 4B and listed in Table 10. It will be recognized in both FIG. 4 and Table 10 that the pin arrangement of the multi-chip module 10 is organized to group interfaces in a way to simplify the design of printed circuit boards to interface the multi-chip module with other modules on the printed circuit board.

As mentioned above, the core logic 26 supports a DRAM bus 22 and an ISA compatible expansion bus 24. The 240 module pins include a set of 94 contiguous pins which set of 94 continuous pins comprises the ISA bus 24. Of the 94 contiguous pins comprising the ISA bus, 88 pins comply in number and signal type with corresponding signal pins specified in IEEE-P996 and ISA specifications. The ISA bus 24 includes three pins allocated to additional signals, two ground pins, and a power pin. The three additional signals include DRQ2OUT--which is a floppy disk DMA request and may be coupled to DRQ2, IRQ7OUT which is a parallel port interrupt request and may be coupled to IRQ07, and IRQ6OUT which is a floppy disk interrupt request and may be coupled to IRQ6. The pin configuration for the ISA expansion bus 24 is shown in Table 11, with corresponding pin numbers for expansion bus connectors A, B, C, D.

The contiguous pin configuration of the expansion bus 24 is a critical feature of the invention. Since it forms a single row of pins on the module 10, the pins can be easily connected directly to the expansion bus connectors without having to resort to multiple layer boards to route the PC board tracks from the module 10 to the expansion bus connectors A, B, C, D.

In the embodiment of the invention depicted herein, the 94 ISA bus pins are numbered from 38 to 131, inclusive, as shown in Tables 1 and 11. This corresponds to pins 38 to 131, inclusive, of the 240 multi-chip module pins listed in Table 10. It is understood that the 94 ISA bus pins may be numbered in reverse order, i.e. from 131 to 38, or between any two numbers, in ascending or descending order, as long as the 94 ISA bus pins are contiguous and extend along a first side and at least partially along two sides bounding the first side of the multi-chip module. In the embodiment depicted herein, 70 of the ISA pins extend along a first side of a multi-chip module, and 12 pins extend along each of the two sides bounding the first side, thereby forming a contiguous set of 94 ISA bus pins.

Furthermore, as mentioned above, the present invention includes microprocessor modules (as illustrated in FIG. 3), peripheral controller modules, e.g., display controller modules, Ethernet control modules, and PCMCIA compatible modules for extended memory (RAM, ROM, EEPROM, flash memory, etc.), as well as for modem, fax, and network interfaces, and also for wireless communication devices. By providing an identical pin configuration for the ISA buses, the various modules can easily be coupled to one another.

A further feature of the invention is illustrated in FIG. 5. FIG. 5 illustrates a card 54 having a mounting site 56 for a module having a pin configuration as described above with reference to FIG. 4. The card 54 provides an integrated way for system development in standard ISA passive backplane systems. The card includes an AT-bus and a PC/104 bus, and occupies a single slot in an AT-class (16-bit) passive backplane. This allows development to be performed using a terminal on a serial port as a console. A standard VGA or SVGA display controller can be plugged into another slot on the backplane if desired, or, a PC/104 display controller can be installed directly on the PC/104 header 58 on the card 54. Since the module 10 is ISA compatible, a wide selection of hardware peripherals may be integrated. The ISA-compatible bus allows an OEM to easily interface its proprietary hardware design with the module 10. Furthermore, the standard BIOS and embedded DOS allows application software to be developed using standard desk top PCs and standard development tools for implementation on the system using one or more modules of the present invention. It will be appreciated that, depending on the nature of the module, the size of the module and the number of pins may vary, however it is an important feature of this invention that the pins for the ISA bus retain their configuration in each module to allow the modules to be readily coupled to one another as illustrated in FIG. 6 in which different modules 60, 62, 64 of the invention are connected to each other by means of bus lines 66, 68 extending between the ISA-compatible bus pins indicated by reference numerals 70, 72, 74, respectively.

FIG. 7 is a flow chart representing a power on self test (POST) 100 initialization sequence of a module of the invention. The POST includes five processing steps which include chip initialization 102, operational mode determination 104, configuration determination 106, BIOS service initialization 108 and boot path determination 110.

During chip initialization 102, general registers, DRAM controllers, counter timers and configuration registers are all initialized. A test is performed to determine whether to use the BIOS in flash memory or in ROM. Pin BDIS- (pin 219 in the embodiment represented in Table 10) is tested. In one embodiment, if BDIS- is pulled low, e.g. connected to ground by an external jumper, then the BIOS is obtained from ROM, and, if BDIS- is allowed to float or pulled high, then the BIOS is obtained from flash memory. This feature is not previously known in embedded components, and it facilitates reloading BIOS in flash memory while minimizing the number of signal pins which are brought out of the module. If BIOS in the flash memory should become corrupted, BDIS- may be set to use the BIOS in ROM, and a serial connector configured (as described below) to place the module in a download configuration may be connected to a serial port. The BIOS may then be downloaded to the flash memory.

During operational mode determination 104, a serial connector is checked to determine the mode in which the module will operate. Tables 12 through 20 depict wiring configurations for serial cables and connectors according to one embodiment of the invention. In Tables 12 through 20, the "Module Connector" refers to a connector at a first end of a serial cable, which connector couples with a mating connector mounted to a printed circuit board on which is mounted a multi-chip module of the invention. The "Cable/Connector" refers to a connector at a second end of the serial cable, which connector couples to a mating connector mounted on another device, e.g., a modem, PC, etc. The pin numbers listed in Tables 12 through 20 are standard pins used to carry the various data and control signals in a serial interface.

For the Module Connector, Tables 12 through 20 list the pin number, the data or control signal carried by each respective pin, and whether the signal is an incoming or outgoing signal. For the Cable/Connector, the tables list the corresponding respective pin numbers for both a 9-pin and a 25-pin serial cable, as well as the data and control signals, and whether the signal is an incoming or outgoing signal. Connections between multiple pins on the same connector are shown by listing each of the coupled pins in the same row of a table. Pins on one connector which are not coupled to the serial cable, and hence not coupled to pins on the other connector are shown opposite a row of blank entries corresponding to the other connector.

Table 12 depicts the wiring configuration for a serial cable and its associated connectors for a straight through connection. In this configuration, each pin at one end of the serial cable is connected to the corresponding pin at the other end of the serial cable. This configuration cannot be used to connect two PC computers together because the output pins of one computer are connected directly to the output pins of the other computer. This cable is usually used to connect a PC to a modem. It can also be used as an extension to a serial cable.

Table 13 depicts a serial cable and connector wiring for a cross-over connection. In this configuration, a serial cable may be used to connect one PC serial port directly to another PC serial port in order to allow one PC to "see" the other PC's control signals. This configuration can be useful in conjunction with software which depends on hardware handshaking.

Table 14 depicts a serial cable and connector wiring for a null modem connection. This cable simulates the case where two serial ports of two PC's are connected by a modem. With a null modem cable, only the data signals, not the control signals, are transmitted from one PC to the other. The control signals are lopped back inside the respective connectors. This is a preferred configuration for PC to PC communication.

Table 15 depicts a serial cable and connector wiring for a three wire cable. This cable is a null modem cable without the looped back control signals. This is considered a low cost cable for PC to PC communications.

Tables 16a and 16b depict a serial cable and connector wiring for a first redirection cable. This configuration can be used to cause the multi-chip module to redirect the screen and keyboard interfaces to the serial port. This is a variation of either a cross-over cable (Table 16a) or a null modem cable (Table 16b) with the CTS control signal pin tied to the GND pin, and not connected to any other pin. Note that on most hardware platforms, these cables are indistinguishable from an open connector because an open pin will appear to the software to float low. This configuration can be useful in a manufacturing environment to install software in the module. This configuration is not compatible with standard communications software.

Tables 17a and 17b depict a serial cable and connector wiring for a second direction cable. This is a variation of either a cross-over cable (Table 17a) or a null modem cable (Table 17b) with the TXD signal pin tied to the CTS control signal pin. This configuration can also be used to cause the multi-chip module to direct the screen and keyboard to the serial port. This configuration can be used in a manufacturing environment to test the module and associated electronics.

Tables 18a and 18b depict a serial cable and connector wiring for a download cable. This is a variation of either a cross-over cable (Table 18a) or a null modem cable (Table 18b) with the TXD signal pin tied to the DCD control signal pin. This configuration may be used to cause the module to initiate the YMODEM batch protocol to the serial port. This may be used in a manufacturing environment to download binary images to the flash memory. This configuration may be used in manufacturing facilities which use automated system configuration equipment.

Tables 19a and 19b depict a serial cable and connector wiring for a cable combining second redirection configuration (Tables 17a, 17b) and a download configuration (Tables 18a, 18b). This is a variation of either a cross-over cable (Table 19a, or a null modem cable (Table 19b) with the TXD signal pin tied to both the CTS and DCD control signal pins. This configuration can be used to cause the module to initiate the YMODEM batch protocol to the serial port. This may be used in a manufacturing environment to manually download binary images to the module's flash memory and configure and test the module and associated electronics.

Table 20 depicts a serial cable and connector wiring having miniature toggle switches installed in the hood of the connector at the Module Connector end of the serial cable. This configuration can be very useful in the development environment. In Table 20, C1, NC1, and NO1 correspond to the common, normally closed and normally open contacts, respectively, of a first toggle switch; and C2, NC2 and NO2 correspond to the common, normally closed and normally open contacts, respectively, of a second toggle switch. As indicated in Table 20, pin 3 of the connector at the module end of the serial cable is coupled to the normally open contacts (NO1, NO2) of both toggle switches, pin 7 is coupled to the normally closed contact (NC1) of the first toggle switch, pin 8 is coupled to the common contact (C1) of the first toggle switch, pins 4 and 6 are coupled together and to the normally closed contact (NC2) of the second toggle switch, and pin 1 is coupled to the common contact (C2) of the second toggle switch.

Referring again to FIG. 7, during configuration determination 106, the module determines the configuration of the system in which it resides. Configuration determination may include determining the amount of DRAM, the type of video system (e.g. monochrome v. color, make of display panel, etc.), the quantity and type of hard drive(s), the quantity and type of floppy drive(s), the type of keyboard and mouse, the quantity and type of silicon disks (e.g., flash memory formatted as disks, SRAM formatted as disks), and the number of serial and parallel ports.

With its high level of integration, the multi-chip module of the invention includes internal DRAM. However, if a user of the module, for example OEM, needs additional DRAM for a particular application, and if the amount of internal DRAM is not compatible with the amount of external DRAM, it is necessary to disable the internal DRAM. During configuration determination, a flip-flop may be set or reset in the PAL to either enable or disable the electronic drivers, thereby enabling or disabling the internal DRAM. This is a capability not previously known in embedded modules.

BIOS service initialization 108 is a software only process which, for example, may initialize BIOS parameters based on the results of the configuration determination step, set up BIOS software services including keyboard read, display write, and floppy and hard drive read and write services.

Boot path determination 110 is a process in which the module determines the source from which it will obtain the operating system. Pre-established parameters instruct the module to look in a particular order, and may include, for example, a first or second floppy drive, a first or second hard drive, a ROM-based application, a built-in debugger or a ROM DOS.