Circuit With Multiple Output Voltages for Multiple Analog to Digital Converters

1. Field of the Invention

The present invention relates to circuits for use with analog-to-digital converters (ADCs) and, in particular, to circuits that provide multirange output voltages for multiple ADCs.

2. Description of the Related Art

ADCs are used to convert an analog voltage to a digital signal. In some applications, the analog voltage has a magnitude which is proportional to the magnitude of an input signal to be monitored. For example, the input signal may be an input current flowing in a given current path. This input current may drive a primary winding of a current transformer, which produces a current in the secondary winding of the transformer, which is proportional to the input current. The secondary winding current may be applied to a known impedance, such as a resistance, to provide an analog voltage, which has a magnitude proportional to the magnitude of the secondary winding current and, thus, to the magnitude of the input current. The windings of the transformer and value of the resistance may be selected so that the range of the analog voltage for the expected range of the input current will be within the analog voltage input range of an ADC, which in turn converts the analog voltage to a digital signal, which can then be used to monitor the magnitude of the input current.

One problem with such conventional circuits utilizing ADCs is that the input signal to be monitored may have wide magnitude variations, which requires an ADC having a large dynamic range in order to accurately measure the signal's magnitude at both low and high levels. Unfortunately, ADCs capable of measuring a large dynamic range, for example larger than 10 bits, can be relatively expensive and thus unattractive.

Another problem exists in some configurations in which the secondary winding current is forced through a relatively large resistance, which causes a relatively large voltage signal to be produced when the secondary winding current is passed through the resistance. This imposes a large burden on the transformer, which could result in saturation, causing distortion and thus reducing the efficiency and performance of the transformer. Such large voltage signals can also cause damage to the ADC.

A circuit for generating at least two output voltages in response to an input current. A first stage comprises a first impedance for providing a first output voltage when the input current passes through the first impedance. At least a second stage comprises a second impedance coupled to the first impedance, wherein the second impedance provides a second stage voltage when the input current passes through the second impedance. At least a second output voltage is equal to the sum of the second stage voltage and the first output voltage. The second stage further comprises a second stave shunt operable to shunt the input current away from the second impedance when the magnitude of the second output voltage is above a predetermined amount.

FIG. 1 is a schematic diagram of a circuit in accordance with the present invention; and

FIG. 2 depicts the output voltages of the circuit of FIG. 1 versus an input current.

Referring now to FIG. 1, there is shown a schematic diagram of a circuit 100 in accordance with the present invention. Circuit 100 includes a current transformer 102 having primary winding or coil L.sub.1 and secondary winding or coil L.sub.2, which have a certain turn ratio to one another. Transformer 102 further includes core 105. Each terminal of secondary winding L.sub.2 is coupled to node 110 through a respective diode of bridge rectifier 150.

Circuit 100 further comprises stages 121, 122, and 123. Stage 121 comprises resistor R.sub.1, coupled between nodes 110 and 111. Stage 122 comprises resistor R.sub.2, coupled at one terminal to node 112, and at its other terminal to node 111, to a terminal of resistor R.sub.1, to a terminal of resistor R.sub.6, and to the emitter of transistor Q.sub.1. Resistor R.sub.6 is coupled at its other terminal to the base of transistor Q.sub.1, to a terminal of resistor R.sub.8, and to the emitter of transistor Q.sub.3. Resistor R.sub.8 is coupled at its other terminal to the base of transistor Q.sub.3 and to the anode of zener diode Z.sub.1. The collector of transistor Q.sub.3 is coupled to a terminal of resistor R.sub.10. The other terminal of R.sub.10 is coupled to the cathode of zener diode Z, and to a terminal of resistor R.sub.4. Resistor R.sub.4 is coupled to the collector of Q.sub.1, to node 112, and to resistor R.sub.2 through resistor R.sub.7.

Stage 123 comprises resistor R.sub.3, coupled at one terminal to node 113, and at its other terminal to node 112, to a terminal of resistor R.sub.2, to a terminal of resistor R.sub.7, and to the emitter of transistor Q.sub.2. Resistor R.sub.7 is coupled at its other terminal to the base of transistor Q.sub.2, and to a terminal of resistor R.sub.4. Resistors R.sub.4 and R.sub.7 are thus components of both stages 122 and 123. Resistor R.sub.4 is coupled at its other terminal to the cathode of zener diode Z.sub.1, to resistor R.sub.10, to resistor R.sub.9, and to the emitter of transistor Q.sub.4. Resistor R.sub.9 is coupled at its other terminal to the base of transistor Q.sub.4 and to the anode of zener diode Z.sub.2. The collector of transistor Q.sub.4 is coupled to a terminal of resistor R.sub.11. The other terminal of resistor R.sub.11 and the cathode of zener diode Z.sub.2 are coupled to resistor R.sub.5 and to each terminal of secondary winding L.sub.2 through a is respective diode of bridge rectifier 150. The other terminal of resistor R.sub.5 is coupled to the collector of transistor Q.sub.2, to resistor R.sub.3, and to node 113.

In one embodiment, the resistors of circuit 100 have the following values: R.sub.1 =12.5 .OMEGA.; R.sub.2 =187.5 .OMEGA.; R.sub.3 =3 K.OMEGA.; R.sub.1 =866 .OMEGA.; R.sub.5 =13.7 K.OMEGA.; R.sub.6 =10 K.OMEGA.; R.sub.7 =10 K.OMEGA.; R.sub.8 =10K.OMEGA.; R.sub.9 =10K.OMEGA.; R.sub.10 =82 .OMEGA.; R.sub.11 =82 .OMEGA.. Zener diodes Z, and Z.sub.2 each have reverse breakdown voltages of 15 V.

First current I.sub.1, driven by current source 101, flows through primary winding L.sub.1 of transformer 102. A proportional alternating current 13 is thereby generated at secondary winding L.sub.2. Alternating current 13 is rectified by bridge rectifier 150 to generate rectified second current I.sub.2, which is applied to stage 123 at the junction of resistors R.sub.11, R.sub.5, and zener diode Z.sub.2. Secondary winding L.sub.2 combined with bridge rectifier 150 is thus a current source that generates second current I.sub.2. Circuit 100 outputs three voltages, V.sub.1, V.sub.2, and V.sub.3, at nodes 111, 112, and 113, respectively, each of which is measured with respect to ground or common node 110. Voltages V.sub.1, V.sub.2, and V.sub.3 are analog voltage signals that are applied to ADCs 1, 2, and 3, respectively. Each ADC, in one embodiment, is a 10-bit ADC. Thus, the magnitude of each of voltages V.sub.1, V.sub.2, and V.sub.3 is converted to a 10-bit digital number by its respective ADC at each sampling interval. Each of voltages V1, V.sub.2, and V.sub.3 thus has a dynamic range of 10 bits. Circuit 100 is configured to provide an 18-bit dynamic range for the measurement of current I.sub.2 (and thus of current I.sub.1). As will be appreciated, since circuit 100 may be utilized to monitor the magnitude of second current I.sub.2 and thus of first current I.sub.1, either of currents I.sub.1 or I.sub.2 may be considered as the input current converted to corresponding voltages V.sub.1, V.sub.2, and V.sub.3 and thus monitored by ADCs 1, 2, and 3. For purposes of the present description, rectified current I.sub.2 is considered to be the input current, generated by the current source consisting of secondary winding L.sub.2 and rectifier 150, the magnitude of which is to be monitored by ADCs 1, 2, and 3.

To provide an 18-bit dynamic range utilizing three 10-bit ADCs, the magnitudes of voltages V.sub.1, V.sub.2, and V.sub.3 are selected such that V.sub.3 is 4 bits, or 16 times (2.sup.4 =16), larger than V.sub.2, and V.sub.2 is 16 times larger than V.sub.1. For lower magnitudes of current I.sub.2, current 12 flows through each of resistors R.sub.3, R.sub.2, and R.sub.1. The values of these resistors are selected so that voltages V.sub.1, V.sub.2, and V.sub.3, at nodes 111, 112, and 113, are progressively larger by factors of 16. Thus, to ensure that V.sub.2 =16 A V.sub.1, the values of the resistors are selected such that R.sub.2 +R.sub.1 =16 A R.sub.1. Similarly, to ensure that V.sub.3 =16 A V.sub.2, the values of the resistors are selected such that R.sub.3 +R.sub.2 +R.sub.1 =16 A (R.sub.2 +R.sub.1). Thus. stages 121, 122, 123 each provide a resistance for current I.sub.2 to be multiplied by to provide the appropriate output voltage for that stage. For example, stage 123 provides resistor R.sub.3. When current 12 flows through resistor R.sub.3, then the incremental voltage produced thereacross, when added to voltage V.sub.2 with which it is in series, provides voltage V.sub.3, having a magnitude 16 times larger than that of V.sub.2.

Referring now to FIG. 2, there is depicted the output voltages V.sub.1, V.sub.2, and V.sub.3 of circuit 100 of FIG. 1 versus current I.sub.2. In one embodiment, each of ADCs 1, 2, and 3 is configured to operate within a range of 50 mV to 1.25 V, the maximum reading of each ADC. At low currents of approximately 100 .mu.A, V.sub.1 .apprxeq.1.25 mV, V.sub.2 .apprxeq.20 mV, and V.sub.3 .apprxeq.320 mV. Thus, at this current magnitude, the most sensitive reading can be provided by ADC 3 measuring V.sub.3. At a higher current I.sub.2 magnitude, such as 1 mA, V.sub.3 is larger than 1.25 V and is thus too large for ADC 3 to provide an accurate measurement. Thus, at this higher current, the reading of the magnitude of V.sub.2 provided by ADC 2 may be utilized. At higher currents, such as 10 mA, ADC 1, which measures V.sub.1, may be utilized.

ADCs 1, 2, and 3 may be utilized in this fashion to provide an effective 18-bit resolution measurement of the magnitude of currents I.sub.2 and I.sub.1. When input current magnitude is lower, greater resolution may be provided by using the lower 10-bits of the 18-bit resolution provided by ADC 3. When input current magnitude is highest, the upper 10-bits of the 18-bit overall resolution may be obtained from ADC 1. As will be appreciated by those skilled in the art. ADCs 1, 2, and 3 may be utilized in this fashion by always selecting the reading from the ADC having the largest-magnitude input voltage that is also not greater than the maximum allowable input voltage for ADCs. For example, a program running on a processor may constantly monitor the reading of V.sub.1 provided by ADC 1. Whenever V.sub.1 is greater than approximately 78 mV (the point at which V.sub.2 =1.25 V), ADC 1 will be utilized to measure the input current. Whenever V.sub.1 is greater than approximately 5 mV (the point at which V.sub.3 =1.25 V) but less than approximately 78 mV, ADC 2 will be utilized to measure the input current. Whenever V.sub.1 is less than approximately 5 mV, ADC 3 is utilized to measure the input current.

If stages 122 and 123 consisted exclusively of resistors R.sub.2 and R.sub.3, then, at higher input currents, for example when ADC 1 is utilized to measure V.sub.1, voltages V.sub.2 and V.sub.3 would be 16 and 256 times larger, respectively, than V.sub.1. Such large voltages could damage ADCs 2 and 3, and also place an undesirable burden on transformer 102, as explained previously. Therefore, in the present invention. stages 122 and 123 provide shunting means 132 and 133 which shunt most of current I.sub.2 away from the stages respective resistors R.sub.2 and R.sub.3. In stage 122, shunting means 132 consists of the components of stage 122 other than resistor R.sub.2. In stage 123, shunting means 133 consists of the components of stage 123 other than resistor R.sub.3. As illustrated in FIG. 2, at an input current I.sub.2 of approximately 1 mA, voltage V.sub.3 is approximately 3 V, and, as input current I.sub.2 increases, voltage V.sub.3 starts to "fold back" to a voltage having a slightly larger magnitude than that of V.sub.2 by the time input current I.sub.2 is approximately 1.3 mA, since most of current I.sub.2 is shunted by shunting means 133 so that it no longer passes through R.sub.3. Similarly, at an input current I.sub.2 of approximately 15 mA, voltage V.sub.2 is approximately 3 V, and, as input current I.sub.2 increases, voltage V.sub.2 starts to fold back to a voltage having a slightly larger magnitude than that of V.sub.1 by the time input current I.sub.2 is approximately 20 mA, since most of current I.sub.2 is shunted by shunting means 132 so that it no longer passes through R.sub.2.

Shunting means 133 and 132 operate as follows, as will be appreciated by those skilled in the art. At current 12 magnitudes below 1 mA, both shunting means are "off," and thus allow I.sub.2 to pass through resistors R.sub.3 and R.sub.2. When shunting means 133 and 132 are off, their constituent zener diodes and transistors are off, and the shunting means appear as open circuits to current I.sub.2. As current I.sub.2 reaches and begins to exceed 1 mA, the voltage drop across resistor R.sub.5 becomes high enough such that the voltage at the terminal of resistor R.sub.5 coupled to the cathode of zener diode Z.sub.2 turns on Z.sub.2, causing current I.sub.z2 to flow therethrough. Current I.sub.z2 flows through resistor R.sub.9, causing a voltage drop thereacross which turns on transistor Q.sub.4. Current thus flows through transistor Q.sub.4 and thence through R.sub.4 and R.sub.7. The voltage drop across R.sub.7 is sufficient to turn on transistor Q.sub.2, which thus shunts away from R.sub.3 most of current I.sub.2, causing the voltage V.sub.3 to "fold back" as illustrated in FIG. 2. At this point. V.sub.3 is slightly larger than V.sub.2.

Most of current I.sub.2 thus flows through Q.sub.2 instead of through R.sub.3 for current magnitudes above approximately 1.3 mA. At this point none of the current from Q.sub.4 flows down into shunting means 132, since Q.sub.3 and Z.sub.1 of shunting means 132 are off because the voltage across R.sub.2 is insufficient to allow current to flow through zener diode Z.sub.1. Transistor Q.sub.1 thus remains turned off, and current I.sub.2 flows through stage 123 and thence through resistors R.sub.2 and R.sub.1, to develop voltages V.sub.2 and V.sub.1, as before. As current I.sub.2, reaches and begins to exceed 15 mA, the voltage drop across resistor R.sub.4 becomes high enough such that the voltage at the terminal of resistor R.sub.4 coupled to the cathode of zener diode Z.sub.1 turns on Z.sub.1, causing current I.sub.Z1, to flow therethrough. Current I.sub.Z1, flows through resistor R.sub.8, causing a voltage drop thereacross which turns on transistor Q.sub.3. Current thus flows through transistor Q.sub.3 and thence through R.sub.6. The voltage drop across R.sub.6 is sufficient to turn on transistor Q.sub.3, which thus shunts away from R.sub.2 most of current I.sub.2, causing the voltage V.sub.2 to "fold back" as illustrated in FIG. 2. At this point. V.sub.2 is slightly larger than V.sub.1.

Resistors R.sub.4 and R.sub.5 along with zener diodes Z.sub.1 and Z.sub.2, are the principal components of circuit 100 that set the fold back points, or maximum voltages, for ADCs 2 and 3, respectively. Resistors R.sub.10 and R.sub.11 are used to reduce the power loss in transistors Q.sub.3 and Q.sub.4 at higher current levels.

Thus, circuit 100 is a circuit for generating output voltages V.sub.1, V.sub.2, and V.sub.3 in response to an input current I.sub.2. In one embodiment, circuit 100 comprises a first stage 121 comprising a first impedance R.sub.1 for providing a first output voltage V.sub.1 when the input current 12 passes through the first impedance R.sub.1, and a second stage 122. Second stage 122 comprises a second impedance R.sub.2 and a second stage shunt means 132, wherein the second impedance R.sub.2 provides a second stage voltage V.sub.R2 =(V.sub.2 --V.sub.1) when the input current I.sub.2 passes through the second impedance R.sub.2 and the second stage shunt means 132 is for shunting the input current I.sub.2 away from the second impedance R.sub.2 when the input current I.sub.2 is above a predetermined amount (in the example given above, 15 mA). The second impedance R.sub.2 is coupled to the first impedance R.sub.1 so that the second stage voltage V.sub.R2, when added to the first output voltage V.sub.1, provides a second output voltage V.sub.2. The second stage shunt means 132 preferably comprises a transistor Q.sub.1 for shunting the input current I.sub.2 away from the second impedance R.sub.2. The second output voltage V.sub.2 is preferably a predetermined multiple (e.g., 16) of the first output voltage V.sub.1.

In further embodiments, additional stages may be added, such as third stage 123. Third stage 123 comprises a third impedance R.sub.3 and a third stage shunt means 133, wherein the third impedance R.sub.3 provides a third stage voltage V.sub.R3 when the input current 12 passes through the third impedance R.sub.3 and the third stage shunt means 133 is for shunting the input current away from the third impedance when the input current is above a second predetermined amount (e.g., 1mA), wherein the third impedance is coupled to the second impedance so that the third stage voltage V.sub.R3, when added to the second output voltage V.sub.2, provides a third output voltage V.sub.3.

Thus, circuit 100 of the present invention provides for reduced power requirements and a reduced burden on the transformer. Central processing units (CPUs) having multiple 10-bit ADCs are also relatively inexpensive, so that the current invention provides for a larger dynamic ADC range than is possible with a single ADC, at a lower cost.

Those skilled in the art will appreciate that alternative embodiments of the present invention may utilized a number of stages other than three. For example, a four-stage circuit may be utilized with four ADCs and four output voltages, in which three of the four stages provide a resistor and a shunting means. Additionally, in alternative embodiments, ADCs having a resolution other than 10-bits may be utilized. ADCs may also be combined with overlaps other than 4 bits, to provide an effective resolution other than 18 bits. For example, three 10-bit resolution ADCs may be utilized, with voltages V.sub.1, V.sub.2, and V.sub.3 separated by a factor of 32 (5 bits) rather than 16 (4 bits), for an overall resolution of 20 bits instead of 18 bits. Alternatively, three 12-bit resolution ADCs may be utilized, with voltages V.sub.1, V.sub.2, and V.sub.3 separated by a factor of 16, for an overall resolution of 20 bits instead of 18 bits.

It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as recited in the following claims.