Method and System for Yield Loss Analysis by Yield Management System

1. Field of the Invention

This invention relates to methods and apparatus for systems for manufacture of semiconductor devices and more particularly to yield loss analysis in yield management systems.

2. Description of Related Art

U.S. Pat. No. 5,598,341 of Ling et al. for "Real-Time In-Line Defect Disposition and Yield Forecasting System" shows a real time defect disposition and yield forecasting system which uses KLA and INSPEC inspection tools. A particle in contact with two conductor lines is described as a "killer defect." It is stated that the particle "may kill or prevent the normal operation of the semiconductor device which utilizes conductors . . . " Ling describes a real time, in-line system. An inspection method/tool provide for inspection of at least two layers of a semiconductor wafer, producing "first information" on particle size, particle location, and the number of particles. A design review station inspects those at least two layers and produces "second information" including the layouts of each of those at least two layers. A yield management station is operatively connected to the in-line fabrication inspection tool and to the design review station. The yield management station determines at least one of a number of killer defects for the devices in each of the at least two layers or a defect sensitive area index for each of the at least two layers responsive to layers using the first and second information. Determination of a priority is made for analyzing each of the at least two layers responsive to at least one of the number of killer defects and the defect sensitive area index for each of the at least two layers. See col. 5, line 55 to col. 7, line 8. Ling does not appear to disclose the 6th order polynomial curve fit to identify the killer stage, but Ling does describe a general analysis method/tool/program, Col. 6, line 55 to Col. 7, line 8 .

U.S. Pat. No. 5,475,695 of Caywood et al. for "Automatic Failure System" teaches an automatic failure analysis system which discloses automatic fault extraction (AFE) and a specific analysis technique called inductive fault analysis (IFA).

U.S. Pat. No. 4,801,869 of Sprogis for "Semiconductor Defect Monitor for Diagnosing Processing-Induced Defects" shows a design for a defect monitor pattern/wafer.

U.S. Pat. No. 5,544,256 of Brecher for "Automated Defect Classification System" shows an automated defect classification system for analyzing digital images of defects.

KLA In-line defect inspection tools and the Yield Management System (YMS) are popular tools for studying the visual defect in process but heretofore, there has been no systematic method for determining the correlation between yield loss and visual defects. In the more complicated manufacturing processes, the state of the art methods of yield loss analysis have made it difficult to correlate the major killing stages to the resulting losses in yield. Thus it has been difficult to be efficient in selecting which action to take to improve the yield.

An object of this invention is to identify the correlation between yield loss and visual defects and to find out the major yield killing stages.

The invention includes a yield management method which performs the features as follows:

C.sub.p Yield Test;

The definition of four kinds of dies from the C.sub.p yield test;

The defective bad die compared with yield loss;

The definition of defective bad die percentage (DBD %) and defective bad die count (DBDC);

A trend chart comparison between DBD % and yield loss;

A trend chart comparison between DBDC and yield loss;

Finding the major killer stages.

The invention is a yield management system which performs the functions as follows:

1) correlates the visual defects on dies on a wafer to loss of die yield,

2) accumulates data for run analysis to produce plots of data for each wafer on a stage by stage basis, which can be used to find the killer stage, and

3) uses a polynomial curve fitting (6th order) method to produce curves which are compared to determine which of the stages of the production line is the killer stage.

The present invention focuses upon a single stage of manufacture of a single layer at a time, unlike Ling et al.

Analysis is made of the percentage of defective bad dies (DBD %) compared with yield loss in as expressed in a trend chart.

In addition, analysis is made of the Defective Bad Die Count (DBDC) compared with the yield loss as expressed in a trend chart.

Further factors to consider are as follows:

1. DBD %: that can involve at least two different types of products but they use the same design rule (i.e. 0.5 .mu.m design rule.)

2. DBDC: just for the single product analysis.

The system is used to analyze the overall yield trend. This system forecasts the applicability of the process employed to different products from the one being focussed upon. (DBD %)

Caywood et al. discloses a specific analysis technique which is different from the sixth (6th) degree polynomial regression of the invention.

In accordance with this invention, a method for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages comprises the following steps.

Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location.

Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages.

Calculate the defective die count for each stage for the wafer.

Calculate the defective bad die count for each stage for the wafer.

Determine the percentage of the defective bad die count divided by the defective die count.

Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. and

Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

Preferably the method includes the additional steps, as follows:

Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages with sixth order fitting curves.

Compare the plots with the sixth order fitting curves to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

Calculate the defective bad die count for several combined stages.

Plot a trend chart for the combined plot.

Preferably plot that trend chart for stages with fitting curves which indicate possibly matching trends.

In accordance with another aspect of this invention, a system for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages is provided.

The system comprises as follows:

Means for inspecting semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location;

Means for inspecting the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages;

Means for calculating the defective die count for each stage for the wafer;

Means for calculating the defective bad die count for each stage for the wafer;

Means for determining the percentage of the defective bad die count divided by the defective die count;

Means for plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages; and

Means for comparing the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

Preferably the system includes:

Means for plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages with sixth order fitting curves;

Means for comparing the plots with the sixth order fitting curves to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage;

Means for calculating the defective bad die count for several combined stages;

Means for plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages with sixth order fitting curves;

Means for plotting a trend chart for the combined plot;

Means for plotting a trend chart for stages with fitting curves which indicate possibly matching trends.

The foregoing and other aspects and advantages of this invention are explained and described below with reference to the accompanying drawings, in which:

FIG. 1 is a flow chart of the method of this invention and the operation of the system of this invention.

FIG. 2 shows a system for performing the method of FIG. 1 in a manufacturing system.

FIG. 3 shows a semiconductor wafer on which is a plurality of dies have been produced in accordance with the operation of the system and method of this invention.

FIG. 4 shows a chart of the result of a C.sub.p yield test using the novel method of this invention for yield improvement analysis.

FIG. 5. shows a chart of four sets of die categories with respect to good and defective dies which are either clean or defective.

FIG. 6 shows the trend chart of yield loss & DBD % for the POLY.sub.-- ASI (Front End, Poly1-Etch) inspection after stripping photoresist.

FIG. 7 shows the trend chart of yield loss & DBD % for the Plug1-BARRIER stage.

FIG. 8 shows the trend chart of yield loss & DBD % for the Plug1-W-DEP stage.

FIG. 9 shows the trend chart of yield loss & DBD % for the Plug1-W-Etch Back stage.

FIG. 10 shows the trend chart of yield loss & DBD % for the VIA1-Oxide1-DEP stage.

FIG. 11 shows the trend chart of yield loss & DBD % for the Plug3-W-Etch Back stage.

FIGS. 12 and 13 show the correlation of 0.5 .mu.m SPTM logic C.sub.p yield lost and KLA In-line Monitor results for the six stages of FIGS. 6-11 combined. The sampling is for 2 wafers in 1 lot. The defect size is greater than 2 .mu.m. In FIG. 12 the key BDC stands for Bad Die Count, and the key DBDC stands for Defective Bad Die Count including the upper curve of six stages DBDC the and the lower curve of yield lost BDC as a function of the wafer number of wafers being inspected. FIG. 13 shows the accumulation of the DBDC of three stages Poly1-Etch; VIA1-Oxide1-Dep; and Plug3-W-Etch Back.

FIG. 14 shows the accumulation of the DBDC of two stages VIA-Oxide1-Dep; and Plug3-W-Etch Back.

FIG. 15 shows the upward trend in yield vs. wafer in a way that the killer defect problem has been overcome.

The purpose of the method of this invention is to point out the correlation between visual defects and lost yield. The method will be described below in connection with the flow chart in FIG. 1.

FIG. 2 shows a system for performing the method of FIG. 1 in a manufacturing system which is producing a plurality of dies on a semiconductor wafer W of the kind shown in FIG. 3. Wafer W includes some dies which are perfect and some dies which have imperfections. There are four different types of dies including a Clean Good Die (CGD), Clean Bad Die (CBD), Defective Good Die (DGD), Defective Bad Die (DBD). A "Clean" die is a die without a visual defect. A "Defective" die is a die with a visual defect. A "Good" die is a die which will perform satisfactorily. A "Bad" die is a die which will not perform satisfactorily.

FIG. 4 shows a chart of the result of a C.sub.p yield test using the novel method of this invention for yield improvement analysis by the results of KLA defect scan by a Yield Improvement Analysis by KLA-Tencor In-Line Monitor System.

C.sub.p is defined as follows: ##EQU1##

The data is plotted with the C.sub.p Yield data vs. the Wafer Number from Wafer 1 to Wafer 65.

As can be seen from wafer number 1 through wafer number 33, the C.sub.p Yield Trend was Down.

.fwdarw."Slow downward trending.

After some adjustments have been performed in accordance with this invention at the killer stages as pointed out by this invention, there is an improvement from wafer number 34 through wafer number 65, where the C.sub.p Yield Trend is Up.

FIG. 5. shows a chart of four sets of die categories with respect to good and defective dies which are either clean or defective. Area 1 plus Area 3 of the chart encompass the total number of dies. Within the Areas 1 plus 3 area areas 2 and 3 which cover only the bad dies which can be either clean or defective. The areas shown in FIG. 5 are as follows:

Area 1: Clean Good Die (CGD)

Area 2: Clean Bad Die (CBD)

Area 3: Defective Good Die (DGD)

Area 4: Defective Bad Die (DBD)

The four areas 1-4 are described in terms of the visual details and the yield test in Table I below.

The novel method of yield improvement of this invention is focused on the DBD area (Area 4) vs. the Yield Loss areas (Area 2+Area 4). That is to say, that the present invention focuses upon improvement of yield by focussing upon the Area 4 as distinguished from the combination of Area 2 plus Area 4.

Parameters which are used in analyzing the products of the manufacturing process, in accordance with this invention are as follows: ##EQU2## where DDC=Defective Die Count (Scanned by KLA)

DBDC=Defective Bad Die Count

To calculate the DBD % for every stage and to compare the trend chart with C.sub.p yield, that could show the correlations between the C.sub.p yield loss and the specific defects. Definition of Defective Bad Die Count (DBDC) Same processes (design rule), same product type (same product.)

To accumulate the defective bad die count for the specific stages which there are obviously correlations with C.sub.p yield loss and to compare the trend chart between them, that show the major killer Stages for C.sub.p yield loss.

Referring to FIG. 2 again, the system used to perform this invention includes a computer system 14 with a Central Processing Unit (CPU) 16. CPU 16 is connected by line 17 to memory 18. CPU 16 is also connected by line 19 to Direct Access Storage Device (DASD) 20. A keyboard 24 is connected by line 23 to CPU 16 to supply input data and commands from the operator to CPU 16. A line 25 connects from CPU 16 to monitor 26 which is viewed by the operator.

The results of the data analysis performed by the CPU 16 are supplied on line 21 to plotter 22 which prints out charts of the results of the analysis made by the system 14 in accordance with this invention such as the DBD % and the Yield Loss % as shown in FIGS. 6-11 as well as the Bad Die Count % and DBDC % shown in FIGS. 12-14.

The graphs printed on the plotter 22 can also be displayed on the monitor 26 for use by the operator.

There is a Defect Detection System (DDS) 31 which tests the wafers W being manufactured to determine whether there are any visual defects (Area 3 and Area 4.) System 31 is connected by line 30 to the CPU 16. System 31 can be a KLA In-Line Monitor Stage (2130, 2132)

There is also a Yield Management System (YMS) 33 connected by line 32 to the CPU 16. The YMS system 33 can be commercially available product such as the Hewlett Packard HP 735 described in Ling et al U.S. Pat. No. 5,598,341 Col. 10, lines 14-52.

The method accumulates data on the visual defects that were correlated to yield loss to determine which is the major stage killing the yield of the manufacturing process.

The method uses a sixth order polynomial curve to fit with the DBDC trend chart and the major yield killing stages will be found quickly and obviously.

State of the art methods of yield loss analysis are complicated. Except the defects of some critical layers such as polysilicon, contact and metal pattern, the visual defects were not easy to verify clearly the correlation to the yield.

A simple way to identify the correlation between yield loss and visual defects is to compare the yield bit map with defective map and to calculate the Defective Bad Die percentage (DBD %) and Defective Bad Die Count (DBDC). A bad die has a specific visual defect.

The killing ratio percentage is as follows: ##EQU3##

To compare the trend chart of DBD % of specific visual defect with yield loss trend chart that will show the correlation between them. If selected the stages which visual defects had strong correlation with yield loss to calculate the DBDC and to fit the DBDC trend chart with a sixth order polynomial curve that can quickly and obviously to point out the major killer stages about yield loss. By this method of analysis the stages with major defects causing yield loss are identified providing an efficient tool for yield improvement.

FIG. 1 is a flow chart of the method of this invention In block 40 the program begins.

In block 42 the step is to count visual defects by scanning dies at a series of several (6) stages of manufacture.

In block 44 the step is to calculate the Defective Die Count (DDC) for each wafer at each stage with the YMS.

In block 46, the step is to calculate the Defective Bad Die Count (DBDC) at each stage for each wafer with the YMS.

In block 48, the step is to determine DBD percentage by the formula: ##EQU4##

In block 50, the step is to plot trend chart for every stage scanned of both yield lost and DBD %.

In block 52, the step is to determine the degree of correlation of the trends of lost yield and DBD % to determine the major killer stage.

In block 54, the step is to calculate the Defective Bad Die Count (DBDC) for several (e.g. six (6)) combined stages for each wafer from the YMS data.

In block 56, the step is to plot the trend chart for several (e.g. six (6)) combined stages scanned of both yield lost and DBD %.

In block 58 step is to determine the killer stage from the combined plot from block 56.

In block 60 the step is to modify the design to reduce source of defects in major killer stage block 62.

In block 62 the program ends.

FIGS. 6-12 show the trend charts of the yield loss and the DBD % for six stages as a function of the 45 wafers which were processed. For both the yield loss curve and the DBD % curve there are sixth order polynomial fitting curves which permit comparison of the yield loss polynomial curve with the DBD % polynomial curve. In FIGS. 6-12 the Yield loss and DBD % curves are fitted with a solid line sixth

The KLA Tencor system has been used to scan the six stages as follows:

FIG. 6 shows the trend chart of yield loss & DBD % for the POLY.sub.-- ASI (Front End, Poly1-Etch) inspection after strip-ping photoresist. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD % (P1SDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves are not a complete match.

FIG. 7 shows the trend chart of yield loss & DBD % for the Plug1-BARRIER stage. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD % (P1BDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves are not trending together, but diverge instead.

FIG. 8 shows the trend chart of yield loss & DBD % for the Plug1-W-DEP stage. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD% (P1DDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves do not trend together, but actually diverge.

FIG. 9 shows the trend chart of yield loss & DBD % for the Plug1-W-Etch Back stage. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD % (P1EDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves do not match completely.

FIG. 10 shows the trend chart of yield loss & DBD % for the VIA1-Oxide1-DEP stage. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD % (V1DDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves which are almost a complete match.

FIG. 11 shows the trend chart of yield loss & DBD % for the Plug3-W-Etch Back stage. The chart includes the upper curve of Percent of Yield lost and the lower curve DBD % (P3EDBD %) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves which are almost a complete match.

The analysis resulting from the comparison of the sixth order polynomial curves of the DBD % curve as contrasted to the yield lost curves produces the conclusions tabulated in Table II.

FIGS. 12 and 13 show the correlation of 0.5 .mu.m SPTM logic C.sub.p yield lost and KLA In-line Monitor results for the six stages of FIGS. 6-11 combined. The sampling is for 2 wafers in 1 lot. The defect size is greater than 2 .mu.m.

In FIG. 12 the key BDC stands for Bad Die Count, and the key DBDC stands for Defective Bad Die Count. The chart includes the upper curve of six stages DBDC the and the lower curve of yield lost BDC as a function of the wafer number of the 45 wafers being inspected. There is the obvious correlation between the C.sub.p lost yield trend and the trend of accumulated defective bad die count.

FIG. 13 shows the accumulation of the DBDC of three stages Poly1-Etch; VIA1-Oxide1-Dep; and Plug3-W-Etch Back. The chart includes the curve of BDC (Yield lost) and the curve DBDC (P1A, V1D, and P3E) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves almost trend together.

FIG. 14 shows the accumulation of the DBDC of two stages VIA-Oxide1-Dep; and Plug3-W-Etch Back. The chart includes the curve of BDC (Yield lost) and the curve DBDC (V1D and P3E) as a function of the wafer number of the 45 wafers being inspected. When those polynomial curves are compared to see whether the curves are similar or dissimilar, it can be seen that the two polynomial curves trend together and almost match perfectly.

Table V shows the results of the methods to develop an upward trend as seen in FIG. 15 in a way that the killer defect problem has been overcome using the data in Table II, the trend charts in FIGS. 6-11, and the DBDC trend charts in FIGS. 12-14 to detect the killer stages. After adjusting the process in the killer stages the results in Table V and trend chart of FIG. 15 have been achieved.

According to the comparison of DBD % vs. Yield lost, the correlations between the defects of specific stages and yield loss can be found.

Calculation of trend charts of DBDC and yield loss and comparison thereof in accordance with the method of this invention points out the major killer stages.

While this invention has been described in terms of the above specific embodiment(s), those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the appended claims, i.e. that changes can be made in form and detail, without departing from the spirit and scope of the invention. Accordingly all such changes come within the purview of the present invention and the invention encompasses the subject matter of the claims which follow.

Method

Tool: KLA in-line defect Inspector, Yield Management System.

Method of test: To calculate and plot the trend chart of DBD % and DBDC from KLA in-line monitor results and yield bit map and to fit the trend chart of DBD% and DBDC with sixth order polynomial curves and to compare them with yield loss trend chart.

Test stages:

Test production: 0.5 .mu.m SPTM logic product.

Test results:

I. The correlation between yield loss and visually defective stage:

II.The major killing stages of yield loss by DBDC calculation:

Poly1-Etch: Front End Defects.

Plug1-Barrier: ILD Layer Defects.

PE-TEOS

BPTEOS

ILD-SOG

Plug1-W-Dep: W Film Defect.

Plug1-W-Etch Back: W Etch Defect.

VIA1-Oxide1-Dep: Metal1 and PE-Oxide Film Defects. Plug3-W-Etch Back: VIA2 Layer Defects.