High-Speed Motion Vector Decoding Circuit

The present invention relates to a motion vector decoding circuit, and, more particularly, to a motion vector decoding circuit which can be applied to a system such as a high-definition television (HDTV) for decoding motion vectors at high speed.

In a general image signal processing apparatus, a continuous digital image signal, such as that found in a HDTV, a digital VTR, or a multi-media system, is compressed using one of various encoding methods in order to transmit data more efficiently. Differential pulse coded modulation (DPCM) is one of the various encoding methods used to encode digital image signals. This method is based on a correlation of data between adjacent frames of images. In the DPCM method, a difference signal corresponds to a certain amount of data being generated to represent a mass of movement within regions between temporally adjacent frames. In contrast, there is no difference signal if the regions lack movement (i.e., portray the same image).

However, according to a motion compensated DPCM method, the certain amount of data can be reduced by finding the most similar segment in an adjacent frame to an image of a particular segment of a current frame, and encoding the image difference between these two segments. The motion compensated DPCM method encodes difference data between each segment of the current frame and the corresponding image segment of the adjacent frame, to thereby improve the transmission efficiency.

A motion vector used for the motion compensated DPCM method represents a direction and magnitude of movement between the image segments of the adjacent frame and the current frame in which the difference signal corresponding to the image segments of the current frame and the adjacent frame is smallest. The motion vector is encoded prior to being transmitted. An example of encoding the motion vector will be described as follows.

When the motion vectors are 3, 10, 30, 30, -14, -16, 27 and 24, the difference between two adjacent motion vectors, which is referred to as delta, becomes 3 (i.e., 3-0), 7 (i.e., 10-3), 20 (i.e., 30-10), 0, -44, -2, 43 and -3, respectively. When a motion vector is represented as 6 bits and the range of the motion vector is between -32 and 31, 48 bits are needed to represent 8 motion vectors. Thus, concerning difference data -44 and 43 exceeding the motion vector range between -32 and 31, the data -44 smaller than the minimum value -32 of the motion vector range is added to the value 64 of the motion vector range. That is, -44+64=20. The value 64 of the motion vector range is subtracted from the data 43 larger than the maximum value 31 of the motion vector range. That is, 43-64=-21.

A plurality of difference data which have been obtained is divided into a predetermined number of groups, and a residual code is allocated to each difference data in order to discriminate between various difference data belonging to the same group. Here, since the difference data of "0" has the highest probability, the residual code is not assigned thereto. To decode the encoded and transmitted motion vector, a conventional motion vector decoding operation is performed by a software conceptual method in a reduced instruction-set computer (RISC) or a microcontroller.

An image decoding system adapted in a HDTV system, as proposed by the MPEG-2 standard, requires a larger image size and a higher processing speed. Thus, the conventional software conceptual method is unacceptable as it places a great burden on the processor. Thus, a hardware apparatus is needed to reduce the burden imposed on the processor and exclusively perform a motion vector decoding operation.

To solve the above problem, it is an object of the present invention to provide a high-speed motion vector decoding circuit for decoding motion vectors at high speed by using dedicated hardware capable of parallel processing in, for example, a HDTV high-speed system adopting the MPEG-2 standards, in which parameters necessary for motion vector decoding are sequentially delayed and output via a pipeline architecture having delays.

To accomplish the above and other objects of the present invention, there is provided a high-speed motion vector high-speed decoding circuit. The decoding circuit includes an input port for receiving parameters necessary for motion vector decoding; a parameter store for storing the input parameters; motion vector decoding means for storing motion vector to be decoded as a previous motion vector and decoding the motion vector using the parameter stored in the parameter store and the previous motion vector; a dual primer for receiving the previous motion vector stored in the motion vector decoding means and generating a predetermined number of dual motion vectors; and a motion vector controller for controlling the operations of all the elements via the input parameters and selecting one between the previous motion vector and the dual motion vector, to output the selected result as a finally decoded motion vector.

The preferred embodiments are described with reference to the drawings wherein:

FIG. 1 is a block diagram showing an image decoding system adopting a high-speed motion vector decoding circuit according to the present invention.

FIGS. 2A and 2B are detailed block diagrams showing the motion vector decoder of FIG. 1.

A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

An image decoding system of FIG. 1 includes a high-speed motion vector decoding circuit 2 according to the present invention. The motion vector decoding circuit 2 receives parameters necessary for motion vector decoding and performs a motion vector decoding operation. The image decoding system also includes a variable length decoder (VLD) 1 for variable-length-decoding the received variable-length-encoded data, a first-in-first-out (FIFO) memory 3 for storing the decoded motion vector output from the motion vector decoding circuit 2, and a memory 4 for storing restored image data of at least one frame at a time. A motion compensator 5 performs a motion compensation operation using motion vectors, with respect to the outputs of an inverse-quantizer and inverse-discrete cosine transformer (IDCT) (not shown) and the image data stored in the memory 4. The IDCT outputs the inversely quantized and inversely discrete-cosine transformed data with respect to the variable-length-decoded data.

The motion vector decoding circuit 2 includes a parameter store 10 for storing parameters applied from the variable length decoder 1, and a motion vector decoder 20 for receiving the parameters and the previous motion vector, and for decoding the current motion vector. The motion vector decoding circuit also includes a previous motion vector store 40 for storing the decoded motion vector as a previous motion vector, a dual primer 50 for receiving the previous motion vector and generating a predetermined number of dual motion vectors, and a motion vector controller 30 for controlling each component of the circuit. A detailed construction of the motion vector decoder 20 is shown in FIGS. 2A and 2B.

Referring to FIGS. 2A and 2B, the motion vector decoder 20 implements a motion vector decoding method on dedicated hardware, in which the motion vector decoding method is described in section 7.6.3.1 of the document entitled "ITU-T H.262 ISO/IEC 13818-2 International Standard (March 1995, Lausan)."

The method is generally defined as follows:

Here, the operator "<<" means a shift left with zero fill, the operator "*" means multiplication, the operator ".parallel." means a logical OR operation, the operator "&&" means logical AND operation, and the operator "==" means an equal to symbol.

In FIG. 1, the VLD 1 receives the encoded data and variable-length-decodes the received data, to generate variable-length-decoded image data and parity data, that is, parameters necessary for motion vector decoding. The image data output from the VLD 1 is supplied to the motion compensator 5 via the inverse quantizer (not shown) and the inverse DCT (not shown). Also, the parameters are applied to the parameter store 10 and the motion vector controller 30 in the motion vector decoding circuit 2. The parameter store 10 stores the applied parameters, including code (f.sub.-- code) for determining a motion vector range, a motion vector code (m.sub.-- code), and a motion vector residual code (m.sub.-- resi). The motion vector decoder 20 reads the parameters stored in the parameter store 10 under control of the motion vector controller 30 and performs a motion vector decoding operation. The motion vector decoder 20 will be described below referring to FIGS. 2A and 2B.

In FIG. 2A, the motion vector decoder 20 first reads a motion vector code (m.sub.-- code) among the parameters stored in the parameter store 10. Delays 213, 225, 233 and 243 constitute a pipeline structure for delaying the incoming motion vector code (m.sub.-- code) by one clock pulse and for outputting the delayed result. During the time when the input motion vector code (m.sub.-- code) is delayed by one clock pulse by the delay 213, an absolute value calculator 211 determines an absolute value of the motion vector (m.sub.-- code), and subtracts "1" from the absolute value. A delay 212 delays the subtracted result and outputs the result to a first delta calculator 22. At this time, the motion vector code (m.sub.-- code.sub.-- 1d) delayed by one clock pulse in the delay 213 is also output to the first delta calculator 22.

Then, the motion vector decoder 20 reads the motion vector residual code (m.sub.-- resi) and the motion vector range determination code (f.sub.-- code) from the parameter store 10 and applies the same to the first delta calculator 22. The motion vector range determination code (f.sub.-- code) is also applied to a range controller 26. During the time when the delay 225 receives the one-clock delayed motion vector code (m.sub.-- code.sub.-- 1d) and delays the received code by one clock pulse again in the first delta calculator 22, a shifter 221 subtracts "1" from the applied motion vector range determination code (f.sub.-- code), obtains the number of effective bits of the motion vector residual code (m.sub.-- resi), left-shifts the obtained result to make it two-times the number (f) of bits, multiplies the obtained number of bits by the absolute value of the motion vector code applied from the delay 212, and then outputs the multiplied result to a delay 224. The delay 224 delays the input data and outputs the delayed result to a second delta calculator 23. The shifter 221 also masks the residual bit portion except for the effective bit portion, as "0" in the applied motion vector residual code (m.sub.-- resi) of a predetermined number of bits and outputs the masked result to a delay 223. The delay 223 delays the input data and outputs the delayed result to the second delta calculator 23. A condition logic unit 222 receives the one-clock delayed motion vector code (m.sub.-- code.sub.-- 1d) and the motion vector range determination code (f.sub.-- code) and logically processes these codes. The condition logic unit 222 outputs the motion vector code of "0" or a binary signal having a logic value of "1" when there is no motion vector residual code, or otherwise a logic value of "0" to the second delta calculator 23 via a delay 226.

An adder 231 in the second delta calculator 23 receives the respective outputs of the delays 223 and 224 and adds the outputs, to calculate a delta value by adding "1" applied to a carry input end Cin to the added result. The calculated delta value is delayed in a delay 232 and output to a delta determination portion 24. The delay 233 delays the motion vector code (m.sub.-- code.sub.-- 2d) delayed by two clock pulses via the delays 213 and 225, by one clock pulse again, and outputs the delayed result to the delta determination portion 24. The delay 234 receives the binary signal from the delay 226 and delays the received signal by one clock pulse, to output the delayed result to the delta determination portion 24.

In the delta determination portion 24, a delta determiner 241 receives the calculated delta value and the motion vector code (m.sub.-- code.sub.-- 3d) delayed by three clock pulses via the delays 213, 225 and 233, and selects one of the calculated delta value and the three-clock delayed motion vector code according to the input binary signal input from the delay 234 to determine the selected result as a final delta value. That is, the delta determiner 241 sets the calculated delta value as a final delta value if the binary signal is zero, and sets the three-clock delayed motion vector code as a final delta value if the binary signal is one. When the calculated delta value is determined as a final delta value, the delta determiner 241 reverses the sign of the finally determined delta value if the three-clock delayed motion vector code (m.sub.-- code.sub.-- 3d) is smaller than zero. The sign of the delta value is reversed by inverting individual bits constituting the finally determined delta value. Here, a process of adding "1" to the inverted delta value is needed, which is performed by an adder 252 included in the motion vector determination portion 25. The delta value finally determined in the delta determiner 241 is output to the motion vector determination portion 25 via a delay 242. A delay 243 which receives the three-clock delayed motion vector code (m.sub.-- code.sub.-- 3d) from the delay 233 delays a sign bit which is the most significant bit (MSB) of the motion vector code (m.sub.-- code.sub.-- 3d) by one clock pulse and outputs the delayed result to the motion vector determination portion 25. The motion vector determination portion 25 receives the finally determined delta value via an adder 252 and receives the one-clock delayed sign bit via the carry input end Cin of the adder 252. A divider 251 divides the previous motion vector PMV read from the previous vector store 40 by "2" according to a control signal PMV.sub.-- DIV applied from the motion vector controller 30 of FIG. 1, and outputs the result to the adder 252.

The motion vector controller 30 outputs a control signal PMV.sub.-- DIV having a value of "0" or "1" to the motion vector decoder 20, according to whether a picture type is a frame structure, and a motion vector is used as a field and vertical component in the motion vector decoded data applied from the VLD 1. Here, the motion vector controller 30 also outputs another control signal DBL.sub.-- PMV corresponding to the control signal PMV.sub.-- DIV.

The divider 251, based on the control signal PMV.sub.-- DIV, outputs the previous motion vector PMV to the adder 252 if the control signal PMV.sub.-- DIV is "0", and divides the previous motion vector PMV by "2" to output the divided result to the adder 252 if the control signal PMV.sub.-- DIV is "1". The adder 252 adds the previous motion vector PMV applied from the divider 251 and the finally determined delta value output from the delta determination portion 24, and adds a sign bit of the motion vector code applied via the carry input end Cin to the added result, to obtain a motion vector. The obtained motion vector is output to the range controller 26 via the delay 253.

The range controller 26 controls the range so that the motion vector exists within the boundary of the motion vector range determination code (f.sub.-- code). For this purpose, the range control unit 261 compares the motion vector input from the delay 253 with the motion vector range determined according to the motion vector range determination code (f.sub.-- code). Based on the result of this comparison, the range control unit 261 adds the motion vector range to the motion vector, if the motion vector is smaller than the minimum value of the motion vector range, and subtracts the motion vector range from the motion vector, if the former is greater than the maximum value of the latter, to thereby control the motion vector. The controlled motion vector is input to a multiplier 262. The multiplier 262 multiplies the controlled motion vector by "2" according to the control signal DBL.sub.-- PMV when the divider 251 divided the previous motion vector PMV by "2", and outputs the controlled motion vector as a decoded motion vector via the delay 263 when the divider 251 outputted the previous motion vector PMV as it is. The decoded motion vector is stored in the previous motion vector store 40. Here, the operation of each component is accomplished within one-clock pulse, and a high-speed motion vector decoding operation is accomplished via a pipeline process. Thus, a six-clock period of time is needed to decode one motion vector, and only a thirteen-clock period of time is required to decode eight motion vectors via the pipeline processing method and apparatus.

Returning to FIG. 1, the motion vector output from the motion vector decoder 20 is stored in the previous motion vector store 40, and is used as a previous motion vector for obtaining a next motion vector. The previous motion vector PMV stored in the previous motion vector store 40 is output to the motion vector decoder 20, the motion vector controller 30 and the dual primer 50 under the control of the motion vector controller 30. The dual primer 50 produces a plurality of dual motion vectors DP using the previous motion vector PMV under the control of the motion vector controller 30 when the currently decoded motion vector is a predictive-picture (P-picture). The produced motion vectors are output to the motion vector controller 30. Since a technique for producing a plurality of the dual motion vectors DP in the dual primer 50 is well-known, the detailed description thereof will be omitted.

The motion vector controller 30 selects the dual motion vector DP input from the dual primer 50, if the kind of motion vector is determined to be a P-picture based on the parameters applied from the VLD 1. In the other cases, the controller 30 selects the previous motion vector PMV input from the previous motion vector store 40. The selected result is then stored in the FIFO memory 3. The FIFO memory 3 stores the selected motion vector according to a write control signal FIFO.sub.-- WR generated by the motion vector controller 30, and outputs the stored motion vector to the motion compensator 5 in turn. The motion compensator 5 receives the image data designated by the motion vector among the restored image data of one frame stored in the memory 4 and adds the received data and the inverse-discrete-cosine-transformed image data, to then store and output the restored image data to the display.

As described above, the present invention relates to a high-speed motion vector decoding circuit, and uses dedicated hardware via a pipeline architecture. The pipeline architecture includes delays to enable the processing and decoding of a motion vector at high speed. As a result, the present invention can be used in a high-speed system such as a HDTV.

While only certain embodiments of the invention have been specifically described herein, it will apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.