Location Dependent Maximum Transition Run Length Code With Alternating Code Word Length and Efficient K Constraint

The present invention relates to digital communications systems and, more particularly to an encoding and decoding system in a disc drive.

In the field of digital communication systems, digital information is conveyed from a transmitter to a receiver through a channel. "Channel" is a generalized term that can include many different mediums. In data storage devices, such as magnetic disc drives, the channel includes a storage medium, and the digital information is transmitted to the storage medium and stored for some period of time before being recovered and delivered to the receiver.

A typical magnetic disc drive includes one or more rigid discs mounted for rotation on a hub or spindle. Each disc has an associated data head formed of a hydrodynamic bearing and a transducer, for communicating with the surface of the disc. An electromechanical actuator moves the data head radially over the disc surface for track seek operations and holds the transducer directly over a desired track on the disc surface for track following operations. A drive controller controls the disc drive based on commands received from a host system to retrieve information from the discs and to store information on the discs.

Information is typically stored in concentric data tracks on the disc surface. The direction of current through the transducer is controlled to encode magnetic flux reversals on the surface of the disc within the selected data track. In one type of coding, known as non-return-to-zero-inverse (NRZI) coding, a digital "1" is represented by a magnetic flux reversal from one bit position to the next in the data track, and a digital zero is represented by a lack of a magnetic flux reversal from one bit position to the next.

In retrieving data from the disc, the drive controller controls the electromechanical actuator so that the data head flies above the desired data track, senses the flux reversals stored in the data track, and generates a read signal based on those flux reversals. The read signal is typically conditioned and then decoded by the drive controller to recover the data represented by the flux reversals.

All channels, including disc drive storage channels, introduce noise into the signals they convey. To detect and sometimes to correct signal errors caused by this channel noise, a large number of coding techniques have been developed. These coding techniques convert data words formed of a number of data bits into code words formed of a number of code bits. Additional bits in the code words permit the detection and sometimes the correction of errors in the signals received from the channel.

The ratio of the number of data bits to the number of code bits is known as the code rate of the code. In general, the ability to detect and correct errors in a received signal increases as the code rate decreases because a lower code rate means a greater number of additional bits in the code word. However, each additional bit added by the encoder increases the time and energy needed to transmit the signal through the channel. Thus, to minimize the time and energy needed to send the code, the code rate should be minimized.

Depending on the detection scheme, the code imposes certain constraints on the code word pattern. For example, in a disc drive, the rotational speed of the spindle motor that rotates the magnetic media varies over time. This results in non-uniform time intervals between read signal voltage pulses. A phase locked loop (PLL) is used to lock the phase and frequency of the read timing clock to the phase and frequency of the read signal voltage pulses. To ensure that the PLL is updated regularly, a code can be used that limits the number of consecutive zeros to no greater than a maximum number "k". This kind of code is known as a run-length-limited (RLL) code with a "k"constraint. The smaller the value of "k", the better the performance of the PLL. However, the smaller the value of "k", the more difficult the code becomes to implement.

The code may also limit the number of consecutive ones in an encoded value to limit the effects of inter-symbol interference, which occurs when consecutive transitions in the transmitted signal interfere with each other. Such codes are known as maximum transition run (MTR) codes with an "L" constraint, where L is the maximum number of consecutive transitions allowed in the channel signal. For example, to avoid three or more consecutive transitions, codes with an MTR constraint L=2 can be designed. Although MTR codes reduce inter-symbol interference, they eliminate a large number of available code words making it difficult and sometimes impossible to implement MTR constraints with high code rates.

The present invention addresses these and other problems, and offers other advantages over the prior art.

One aspect of the present invention includes an encoder and method of encoding which encode successive data words into successive code words having alternating code word lengths. Each code word has a plurality of bit locations. A first maximum transition run constraint is imposed on a first set of the bit locations. Each bit location in the first set is spaced S bit locations apart from one another, where S is an integer greater than one. A second maximum transition run constraint, which is different than the first maximum transition run constraint, is imposed on a second set of the bit locations. The second set comprises each of the bit locations that are not in the first set. The alternating code word lengths and the value of S are defined such that corresponding bit locations in successive code words have the same maximum transition run constraint.

Another aspect of the present invention includes a decoder and a method of decoding a code word stream having alternating code word lengths and the above maximum transition run constraints.

FIG. 1 is a plan view of a disc drive in which the encoder and decoder of the present invention can be used.

FIG. 2 is a block diagram of a generalized communication system in which the encoder and decoder can be used.

FIG. 3 is an organizational layout of a code word stream showing the numbering and naming convention used with one embodiment of the present invention.

FIG. 4 is a block diagram of an encoder according to one embodiment of the present invention.

FIG. 5 is a block diagram of a decoder according to one embodiment of the present invention.

FIG. 6 is an organizational layout of a code word stream showing the code word length and MTR constraint variables according to one embodiment of the present invention.

FIG. 1 is a plan view of a disc drive 100 in which the coding scheme of the present invention can be used. Disc drive 100 includes a housing with a base plate 102 and a top cover 104 (sections of top cover 104 are removed for clarity). Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown). Disc pack 106 can include a plurality of individual discs which are mounted for co-rotation about a central axis. Each disc surface has an associated head 112 which carries one or more read and write transducers for communicating with the disc surface. Each head 112 is supported by a suspension 118 which is in turn supported by a track accessing arm 120 of an actuator assembly 122.

Actuator assembly 122 is rotated about a shaft 126 by a voice coil motor 124, which is controlled by servo control circuitry within internal circuit 128. Head 112 travels in an arcuate path 130 between a disc inner diameter 132 and a disc outer diameter 134. During write operations, actuator assembly 122 positions head 112 over the desired data track. Write circuitry within internal circuitry 128 encodes the data to be stored into successive code words and sends the code words in the form of a serial analog write signal to the write transducer on head 112 which encodes magnetic flux reversals within a magnetic layer on the disc surface. During read operations, the read transducer in head 112 senses the magnetic flux reversals and generates a serial analog read signal. The analog read signal is converted into a serial digital signal, which is provided to detector and decoder circuitry within internal circuitry 128 to produce a recovered data signal.

FIG. 2 is a block diagram of a generalized communication system 148 according to one embodiment of the present invention, which can be formed within disc drive 100, for example. Communication system 148 includes an encoder 150, which receives successive data words 152 and encodes the successive data words into successive code words 153. Each data word can include any number of symbols. In a binary system, for example, each symbol represents one logical data bit. In disc drive applications, a common data word length is eight bits. As described in more detail below, successive data words are encoded into successive code words having alternating code word lengths. In one embodiment, successive code words 153 alternate between eight bits and ten bits in length.

Parallel-to-serial converter 155 receives the successive code words 153, converts each code word into a serial representation and concatenates the serial representations to produce a serial stream of the code word bits 154. The encoding scheme used by encoder 150 imposes several constraints on the serial code word stream as discussed further below. Transmitter/channel precoder 156 receives the serial code word stream 154 and conditions the sequence so that it is optimized for the type of detector used to recover the signal from the channel. Transmitter/channel precoder 156 produces an encoded write signal 158, which is provided to channel 160.

In disc drive 100, channel 160 includes the write transducer in head 112, disc pack 106, and the read transducer in head 112. The encoded write signal is stored on the disc surface by the write transducer. During a read operation, the read transducer reads the stored, encoded information from the disc surface and conveys the encoded information to receiver/detector 162 as a read signal 164. Receiver/detector 162 amplifies and filters read signal 164, and then recovers the encoded information from the read signal using one of several known detection methods. For instance, receiver/detector 162 may use a Viterbi detector, Decision Feedback Equalization (DFE), Fixed-Delay Tree Search with Decision Feedback (FDTS/DF) or Reduced State Sequence detection (RSSE). After detecting and amplifying the signal from channel 160, receiver/detector 162 produces a recovered sequence of code word bits 165, which are provided to serial-to-parallel converter 163. The sequence of code word bits 165 is in a serial format at the input to serial-to-parallel converter 163.

Serial-to-parallel converter 163 groups the bits into code words and converts the code words from a serial format to a parallel format in which successively recovered code words have alternating code word lengths which correspond to the code word lengths generated by encoder 150. Serial-to-parallel converter 163 then outputs the successively recovered code words 166 in a parallel format to decoder 168. Decoder 168 uses the inverse of the coding rules used by encoder 150 and converts successive code words 166 into respective data words 170.

Encoder 150 imposes several constraints on the bit patterns in code word stream 153. Since the rotational velocity of the disc can vary over time, a phase locked loop (PLL) is used to lock the phase and frequency of the read timing clock to the phase and frequency of read signal 164. To ensure that the PLL is updated regularly, encoder 150 uses a code that limits the number of consecutive zeros in code word stream 153 to no greater than a maximum number "k". This kind of code is known as a run-length-limited (RLL) code with a "k" constraint. Encoder 150 also limits the number of consecutive ones in code word stream 154 to limit the effects of inter-symbol interference, which occurs when consecutive transitions in channel signal 158 interfere with each other. Such codes are known as maximum transition run (MTR) codes with an "L" constraint, where L is the maximum number of consecutive transitions allowed in channel signal 158.

In one example of the present invention, encoder 150 uses an 8/9 rate Location Dependent Maximum Transition Run (LDMTR) code with a "k" constraint of seven. The LDMTR code imposes different MTR constraint values for different pre-defined locations within each code word. For example, transition runs starting at even bit locations within code word stream 154 may have an MTR of three (L.sub.E =3) while transition runs starting at odd bit locations within code word stream 154 may have an MTR of two (L.sub.O =2). The 8/9 rate LDMTR code is achieved by encoding eight-bit data words into eight-bit code words and ten-bit code words alternately. Since the alternating code word lengths (e.g. eight and ten) are both even, corresponding bit locations in successive code words have the same MTR constraint. This allows encoder 150 to enforce the pre-defined MTR constraints over the boundaries between adjacent code words efficiently with a low complexity code.

FIG. 3 shows an organizational layout for a code word stream 178 that can appear as code word stream 154 or 165 of FIG. 2 in the above-example. Code word stream 178 is formed of three concatenated code words 180, 181 and 182. Code words 180 and 182 have code word lengths of eight bits, and code word 181 has a code word length of ten bits. The first bit in time is to the far left of stream 178 and later bits in time extend to the right. Line 184 assigns an integer to each bit in code words 180-182 based on its overall location within the respective code word. Under this numbering system, the first bit in each code word is the most significant bit and is numbered as bit seven for code words 180 and 182 and as bit nine for code word 181. The last bit in each code word is the least significant bit and is numbered as bit zero. Line 186 assigns an integer to each bit in code words 180-182 based on its temporal location within the overall code word stream 178.

Even/odd line 188 lies above line 186 and provides an "E" designation for each even bit in code word stream 178 and an "O" designation for each odd bit in code stream 178. The "E" and "O" designation is vertically aligned with its respective bit in code word stream 178. MTR line 188 designates the MTR constraint for each bit location in code words 180-182. Each even bit location in code word stream 178 has an MTR constraint of three, and each odd bit location in code stream 178 has an MTR constraint of two. Since the alternating code word lengths of code words 180-182 are both even, corresponding bit locations (as designated by line 184) in successive code words 180-182 have the same MTR constraint. This ensures that all MTR constraints are satisfied in the overall code stream 178 at the boundaries between the individual code words in the stream.

Encoder 150 generates the code words by using a state driven code table for mapping each data word pattern to a respective code word. The state driven code table is generated by collecting all the eight-bit and ten-bit patterns that satisfy the MTR constraints of L.sub.E =3 and L.sub.O =2, for example. There are 178 eight-bit patterns and 634 ten-bit patterns that satisfy the constraints.

The eight-bit patterns that satisfy the constraints are divided into two states, S0 and S1, and the ten-bit patterns that satisfy the constraints are divided into four states, S2, S3, S4 and S5. Table 1 shows the criteria used for dividing the patterns into respective states, where "X" designates a bit location having a binary value of "1" or "0".

For the eight-bit patterns in states S0 and S1, those patterns having a "1" in the most significant bit position are grouped into state S0. Those patterns having a "0" in the most significant bit position are grouped into state S1. For the ten-bit patterns in states S2, S3, S4 and S5, those patterns beginning with a "11", "1011", or "0111" are grouped into state S2. Those patterns beginning with a "100" or "1010" are grouped into state S3. Those patterns beginning with a "010" or "0110" are grouped into state S4. Those patterns beginning with a "00" are grouped into state S5.

The valid eight-bit patterns in states S0 and S1 are shown in hexadecimal form in Tables 2A and 2B, respectively.

The valid ten-bit patterns in states S2-S 5 are shown in hexadecimal form in Tables 3A-3D, respectively.

Since the state, S0 or S1, of the eight-bit code words can be uniquely determined by one most significant bit, and the state, S2, S3, S4 or S5, of the ten-bit code words can be uniquely determined by four most significant bits, error events of seven or less bits will at most cause decoding errors of two data words. Error events of eight to fifteen bits will, at worst, cause decoding errors of three data words.

To enforce the constraints of L.sub.E =3 and L.sub.O =2 such that invalid patterns do not occur at the boundaries when successive code words are concatenated with one another, each code word is associated with a next state pointer such that an eight-bit code word in state S0 or S1 always points to a ten-bit code word in state S2, S3, S4 or S5 and a ten-bit code word in state S2, S3, S4 or S5 always points to an eight-bit code word in states S0 or S1. The encoding process may start with either the eight-bit code words or the ten-bit code words.

Table 4 shows the valid next state pointers for each code pattern in states S0-S5, where "X"="0" or "1".

Code patterns in states S0 and S1 that end with "0" in the "least significant" bit position [0] or [0:1] in bit positions [1:0] may have states S2, S3, S4 and S5 as their next states. Code patterns in states S0 and S1 that end with "11" in bit positions [1:0] may only have states S4 and S5 as their next states. This enforces the MTR constraint of L.sub.O =2 on bit position [1] by ensuring that the first bit in the next successive code word in the code stream is a "0", as shown in the code patterns for states S4 and S5 in Table 1. Three "1's" are not possible at the boundary from states S0 and S1 to states S4 and S5, beginning at bit position [1].

Similarly, code patterns in states S2, S3, S4 and S5 that end with "0" in bit position [0] or "01" in bit positions [1:0] may have states S0 or S1 as their next states. Code patterns in states S2, S3, S4 and S5 that end with "11" in bit positions [1:0] may only have state S1 as their next state.

Using these state definitions, the mapping for an 8/9 rate code having a location dependent MTR constraint of L.sub.E =3 and L.sub.O =2 and with a "k" constraint of seven can be derived. Table 5 is a state diagram which maps each data word to a corresponding code word and next state value for each state S0-S5 in the example provided above. The eight-bit code words are represented by two hexadecimal values and the ten-bit code words are represented by three hexadecimal values. The data words are provided in the column labeled "DATA", the corresponding code words are provided in the columns labeled "CODE", and the corresponding next states are provided in the columns labeled "NXS".

An example of a decoding sequence through the state diagram shown in Table 5 can be explained with reference to the code word stream shown in FIG. 3. Hexadecimal line 200 provides a hexadecimal representation "81", "34A" and "D8" for code words 180, 181 and 182, respectively, in code word stream 178. State line 202 indicates the present state of decoder 168 as the respective code word is being decoded. Data line 204 indicates the corresponding decoded data word in hexadecimal form for code words 180 and 181. As code word 180 having a hexadecimal value of "81" is applied to decoder 168, decoder 168 is in state S0. Looking at the top left corner of Table 5, the corresponding data word for hexadecimal value "81" is either "00", "40", "80" or "C0", depending on the value of the next state pointer. In this example, the next state pointer points to state "S2 " (for code word 181) so the corresponding data word is "00". Code word 181 has a hexadecimal value of "34A". In the column corresponding to state S2, code "34A" corresponds to either data word "D5" or data word "DD", depending on whether the next state pointer is state S0 or S1. In this example, the next state pointer points to state S0 so the corresponding data word is "D5". This operation continues for each successive code word. The inverse of operation is used by encoder 150 to encode the data words.

In order to map eight-bit data words into eight-bit or ten-bit code words, only 2.sup.8 or 256 unique combinations of code word patterns and next state values are required for each state S0 -S5. Since each state has more than 256 combinations, undesirable code word patterns or long-run patterns with small Euclidian distances can be avoided by systematically eliminating them from the state diagram. For example, all code word pattern combinations that will cause long runs of zeroes, i.e. greater than the "k" constraint, can be eliminated. In the example provided in Table 5, enough patterns were eliminated to reduce the "k" constraint to seven while still keeping at least 256 combinations in each state. In addition, all code word patterns are eliminated that may cause long runs of "110110. . .", which is known as a quasi-catastrophic sequence that may force the detector to keep a long memory length.

FIG. 4 is a block diagram illustrating encoder 150 which, in the above-example, encodes successive data words into successive code words having alternating code word lengths of eight bits and ten bits. Encoder 150 includes eight-bit encoder 220 and ten-bit encoder 221. Eight-bit encoder 220 includes eight-bit data word input A[7:0] which is coupled to bus 222, eight-bit code word output Y[7:0] which is coupled to bus 223, next state pointer inputs S.sub.0 and S.sub.1 which are coupled to buses 224 and 225, respectively, and next state pointer outputs S.sub.2 -S.sub.5 which are coupled to buses 226-229, respectively. Ten-bit encoder 221 includes eight-bit data word input B[7:0] which is coupled to bus 230, ten-bit code word output Z[9:0] which is coupled to bus 232, next state pointer inputs S.sub.2 -S.sub.5 which are coupled to buses 226-229, respectively, and next state pointer outputs S.sub.0 and S.sub.1 which are coupled to buses 224 and 225, respectively. Incoming data words are time-multiplexed onto data word inputs A[7:0] and B[7:0], and the corresponding code words generated on code word outputs Y[7:0] and Z[9:0] are time-multiplexed into parallel-to-serial converter 155 (shown in FIG. 2).

The operation of eight-bit encoder 220 and ten-bit encoder 221, which implement the state diagram shown in Table 5, can be expressed in Boolean algebra and implemented in either hardware or software. The Boolean equations for eight-bit encoder 220 and ten-bit encoder 221 are provided in Tables 6A and 6B below, where".vertline." represents a bitwise logical OR, "&" represents a bitwise logical AND, ".vertline." represents a bitwise logical exclusive-OR, and "X" represents the inverse of X.

FIG. 5 is a block diagram illustrating decoder 168 which, in the above-example, decodes successive code words having alternating code word lengths of eight bits and ten bits into successive data words having eight bits. Decoder 168 includes eight-bit decoder 240 and ten-bit decoder 241. Eight-bit decoder 240 includes eight-bit code word input Y[7:0] which is coupled to bus 242, eight-bit code word output A[7:0] which is coupled to bus 243, invalid code word indicator output FA which is coupled to bus 244, next state pointer inputs S.sub.2 -S.sub.5 which are coupled to buses 245-248, respectively, and next state pointer outputs S.sub.0 -S.sub.1 which are coupled to buses 249 and 250, respectively. Ten-bit decoder 241 includes ten-bit code word input Z[9:0] which is coupled to bus 251, eight-bit code word output B[7:0] which is coupled to bus 252, invalid code word indicator output FB which is coupled to bus 253, next state pointer inputs S.sub.0 -S.sub.1 which are coupled to buses 249 and 250, respectively, and next state pointer outputs S.sub.2 -S.sub.5 which are coupled to buses 245-248, respectively. Incoming code words are time-multiplexed onto code word inputs Y[7:0] and Z[9:0] from serial-to-parallel converter 163 (shown in FIG. 2), and the corresponding decoded data words are time-multiplexed onto data word outputs A[7:0] and B[7:0].

The Boolean equations for eight-bit decoder 240 and ten-bit decoder 241 are provided in Tables 7A and 7B below.

The coding structure of the present invention can be expanded above the above-example to generate code words having a variety of alternating code word lengths and a variety of MTR constraints beginning at different pre-defined locations within individual code words. However, it is important that the alternating code word lengths and the MTR location dependency be defined such that corresponding bit locations in successive code words have the same MTR constraint and all MTR constraints are satisfied when the code words are concatenated to one another to form the code word stream.

This expansion can be defined in terms of variables, including code word length variables "Y" and "Z", MTR constraint variables "M" and "N", and an MTR location dependency variable "S". These variables are shown in FIG. 6 with reference to code word stream 178. Again, bit location line 184 is shown above code word stream 178. Code words 180-182 have alternating first and second code word lengths of "Y" bit locations (labeled 260) and "Z" bit locations (labeled 262), respectively. In the example shown in FIG. 6, Y=8 for code words 180 and 182, and Z=10 for code word 181. Encoder 150 imposes a first MTR constraint of "M" on a first set of the Y and Z bit locations, as shown by MTR constraint line 264. Each bit location in the first set is spaced "S" bit locations (labeled 266) apart from one another. In FIG. 6, S=2. Therefore, bit locations "7", "5", "3" and "1" in code words 180 and 182 each have an MTR constraint of M and are spaced two bit locations apart from one another (e.g. 7-5=2). Likewise, bit locations "9", "7", "5", "3" and "1" in code word 181 each have an MTR constraint of M and are spaced two bit locations apart from one another. The code word length variables Y (260) and Z (262) are preferably evenly divisible by the MTR location dependency variable S (266). In the example shown, Y=8 and Z=10, which are both evenly divisible by S, which is equal to two. The encoder imposes a second MTR constraint of "N", which is different than "M", on a second set of the Y and Z bit locations. The second set comprises each of the Y and Z bit locations that are not in the first set. For example, M may be equal to two and N may be equal to three.

In an alternative embodiment, the MTR location dependency variable S equals three. Therefore, every third bit location has an MTR constraint of M, and all remaining bit locations have an MTR constraint of N. For eight-bit data words, possible alternating code word lengths include nine and twelve, for example, since these lengths are evenly divisible by three.

In summary, the present invention provides an encoder 150 and a method of encoding successive data words 152 for transmission through a channel 160. The successive data words 152 are encoded into successive code words 153, 180, 181, 182 having alternating code word lengths Y (260) and Z (262). Each code word has a plurality of bit locations, such as Y[7:0] and Z[9:0]. A first MTR constraint of M is imposed on a first set of the bit locations, wherein each bit location in the first set is spaced S (266) bit locations apart from one another. S is an integer greater than 1. A second MTR constraint of N, which is different than the first MTR constraint, is imposed on a second set of the bit locations, wherein the second set comprises each of the bit locations that are not in the first set. The alternating code word lengths Y and Z and the value of S are defined such that corresponding bit locations in successive code words have the same maximum transition run constraint.

In one embodiment of the present invention, the method of encoding includes defining the alternating code word lengths Y and Z such that they are evenly divisible by S. For example, the method can define S=2 such that the first set of bit locations includes every other one of the plurality of bit locations. A maximum transition run constraint of three is imposed on the first set of the bit locations, such as every even bit location, and a maximum transition run constraint of two is imposed on the second set of the bit locations, such as every odd bit position, as shown in line 190 of FIG. 3. Successive data words 152 are encoded alternately into eight-bit code words 180 and 182 and ten-bit code words 181.

In one aspect of the invention, each code word 153, 180-182 is formed of a series of code symbols, such as binary "1's" and "0's", and the method of encoding further includes concatenating the successive code words together to form a serial code word stream 178. The number of consecutive bit locations in the serial code stream 178 that have identical code symbols is limited to a maximum of seven.

Another aspect of the present invention relates to a encoder 150 for encoding data words 152 into respective code words 153, 180-182. Encoder 150 includes a data word input A[7:0] and B[7:0] for receiving data words 152, a code word output Y[7:0] and Z[9:0] and a state machine 220, 221. The state machine includes a sequence of states which encodes successive data words 152 received on the data word input A[7:0] and B[7:0] into code words 153, 180-182 having alternating code word lengths Y and Z on the code word output Y[7:0] and Z[9:0]. Each code word 153, 180-182 has a plurality of bit locations. The sequence of states is arranged to impose a first MTR constraint of M on a first set of the plurality of bit locations. Each bit location in the first set is spaced S bit locations apart from one another, where S is an integer greater than one. The sequence of states is arranged to impose a second MTR constraint of N, which is different than the first MTR constraint, on a second set of the plurality of bit locations which comprises each of the bit locations that are not in the first set. The alternating code word lengths Y and Z and the value of S are defined by the state machine such that corresponding bit locations in successive code words 153, 180-181 have the same MTR constraint.

Another aspect of the present invention relates to a decoder 168 having a code word input 166, 242, 251, a data word output 170, 243, 252 and a state machine 241, 241. The state machine 240, 241 has a sequence of states which is arranged to decode successive code words into successive data words having a fixed data word length. The successive code words have alternating code word lengths 260 and 262, and each successive code word has a plurality of bit locations. Each code word has a first maximum transition run constraint M on a first set of the plurality of bit locations. Each bit location in the first set is spaced S bit locations apart from one another, with S being an integer greater than one. Each code word has a second maximum transition run constraint N, which is different than the first maximum transition run constraint, on a second set of the plurality of bit locations which include each of the bit locations that are not in the first set. The alternating code word lengths and the value of S are defined such that corresponding bit locations in successive code words have the same maximum transition run constraint. The sequence of states is arranged to apply the successive data words on the data word output 170, 243, 252.

Yet another aspect of the present invention relates to a method of decoding a code word stream 166 received from a storage channel. Successive code words from the code word stream 166 are decoded into a data word 170, 243, 252 having a fixed data word length. The successive code words have alternating first and second code word lengths 260 and 262 which are different from one another. Each each code word has a plurality of bit locations. A first maximum transition run constraint M is applied on a first set of the bit locations. Each bit location in the first set is spaced S bit locations apart from one another. S is an integer greater than one. A second maximum transition run constraint N, which is different than the first maximum transition run constraint M, is applied on a second set of the bit locations, wherein the second set includes each of the bit locations that are not in the first set. The value of S relative to the alternating code word lengths 260 and 262 is defined such that corresponding bit locations in successive code words have the same maximum transition run contraint.

In yet another aspect of the present invention, a disc drive storage channel 148 is provided which includes a transducer 112 capable of communicating with a data storage disc 106 and means for encoding data words 152 into code words 153, 180-182 which successively alternate between a first code word length Y and a second code word length Z and for imposing the constraints discussed above.

It is to be understood that even though numerous characteristics and advantages of various embodiments of the present invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the coding method and apparatus while maintaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, although the preferred embodiment described herein is directed to a coding system for a disc drive, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to other systems, like satellite communications or cellular phone systems, without departing from the scope and spirit of the present invention.