Method of Fabricating a Shallow-Trench Isolation Structure in an Integrated Circuit

1. Field of the Invention:

This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a shallow-trench isolation (STI) structure in an integrated circuit.

2. Description of Related Art:

The shallow-trench isolation (STI) structure is a widely used isolation structure in integrated circuits for electrically isolating the various active components in the integrated circuit. A conventional method of forming an STI structure includes a first step of forming a trench in the substrate through an anisotropic etching process, a second step of depositing oxide into the trench, and a final step of performing a chemicalmechanical polishing (CMP) process to planarize the top surface of the oxide in the trench. The oxide in the trench then serves as the intended STI structure. One benefit of using the STI structure is that its topmost surface is substantially level with the topmost surface of the substrate.

One drawback to the foregoing method, however, is that the CMP process scratches the top surface of the oxide in the STI structure, thus forming undesired microscratches in the top surface of the oxide in the STI structure. The forming of these microscratches then causes some problems in the resulting IC device. To better depict this drawback, the conventional STI fabrication method is schematically depicted, step-by-step, in full detail in the following with reference to FIGs. 1A-1E.

Referring first to FIG. 1A, in the first step, a semiconductor substrate 100 is prepared. Subsequently, a pad oxide layer 102 is formed over the substrate 100 for surface protection of the substrate 100. After this, a mask layer 104 is formed over the pad oxide layer 102, preferably from silicon nitride through a low-pressure chemical vapor deposition (LPCVD) process.

Referring next to FIG. 1B, in the subsequent step, a selective etching process is performed to etch into a selected area of the wafer. Etching proceeds successively through the mask layer 104 and the pad oxide layer 102 until reaching a predefined depth in the substrate 100. Through this process, a trench 106 is formed in the substrate 100.

Referring next to FIG. 1C, in the subsequent step, a thermal oxidation process is performed on the wafer, whereby the exposed part of the substrate 100 is oxidized to form a liner oxide layer 108 on the bottom and sidewalls of the trench 106. This liner oxide layer 108 is formed to such an extent as to come into junction with the pad oxide layer 102. Next, a dielectric material, preferably silicon oxide, is deposited through an atmospheric-pressure chemical vapor deposition (APCVD) process into the trench 106 and also over the top surface of the wafer to thereby form an insulating layer 110. After this, a densification process is performed on the wafer in such a manner as to place the wafer in a gaseous nitrogen environment under a high temperature condition, whereby the insulating layer 110 is densified.

Referring next to FIG. 1D, in the subsequent step, a chemical-mechanical polishing (CMP) process is performed on the wafer until reaching the top surface of the mask layer 104, whereby all the surface part of the insulating layer 110 that is laid above the mask layer 104 is removed (the remaining part is here designated by the reference numeral 110a and is here and hereinafter referred to as an insulating plug). The CMP technique is a widely used and well-known surface polishing process in semiconductor fabrication, so details thereof will not be further described.

One drawback to the use of the CMP process, however, is that it scratches the top surface of the resulting insulating plug 110a, thus forming undesired microscratches 112 in the top surface of the insulating plug 110a. These microscratches 112 result because it is necessary to over-polish the mask layer 104 during the CMP process so as to ensure that the overlying part of the insulating layer 110 is entirely removed. Since the mask layer 104 (which is formed from silicon nitride) is harder than the insulating layer 110 (which is formed from silicon oxide), the slurry used in the CMP process together with the particles from the polished mask layer 104 abrade the top surface of the insulating plug 110a, thus resulting in formation of the microscratches 112 in the top surface of the insulating plug 110a.

Referring next to FIG. 1E, in the subsequent step, the mask layer 104 is entirely etched away by using a hot phosphate solution as the etchant. Next, the pad oxide layer 102 is also entirely etched away by using hydrofluoric acid (HF) as the etchant. Through these two etching processes, the insulating plug 110a (FIG. 1D) is also partly etched away (the remaining part thereof is here designated by the reference numeral 110b for distinguishing purpose). The remaining insulating plug 110b and the liner oxide layer 108 in the previously formed trench 106 (FIG. 1B) in combination constitute the intended STI structure.

One drawback to the use of the HF solution, however, is that it would also etch into the microscratches 112 in the top surface of the insulating plug 110a (FIG. 1D), thus further enlarging the microscratches 112. When conductive layers, such as doped polysilicon layers, are being formed on both sides of the insulating plug 110b, some of the doped polysilicon can be accidentally deposited into the microscratches 112, thus resulting in a bridging effect across the insulating plug 110b. The bridging effect across the insulating plug 110b causes leakage current to flow across the insulating plug 110b, thus making the resulting STI structure lose its isolating ability. As a consequence, the resulting IC device may be unreliable in operation. Moreover, it can cause pattern distortion that makes the resulting IC device inoperable, thus decreasing the yield rate of the wafer fabrication.

It is therefore an objective of the present invention to provide a method for fabricating an STI structure in an integrated circuit, which can help eliminate the above-mentioned drawbacks of the prior art so as to prevent the bridging effect across the insulating plug of the resulting STI structure.

In accordance with the foregoing and other objectives of the present invention, a new method for fabricating an STI structure in integrated circuit is provided. The method of the invention includes the steps of: preparing a semiconductor substrate; preparing a semiconductor substrate; forming a trench in the substrate; depositing a dielectric material into the trench to thereby form an insulating layer in the trench; removing a surface part of the insulating layer, with the remaining part of the insulating layer serving as an insulating plug in the trench; forming a mending dielectric layer from a flowable dielectric material over the insulating plug; and performing an etch-back process on the mending dielectric layer until exposing the mask layer. Since the mending dielectric layer is in a flowable state when it is being coated over the wafer, it can fill up all the microscratches in the top surface of the insulating plug, thereby mending the microscratches. As a result, the method of the invention can help eliminate the drawback of the bridging effect across the insulating plug that would otherwise occur in the case of the prior art. The method of the invention can thus help the resulting IC device to be more reliable in operation and also can help increase the yield rate of the wafer fabrication.

The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

FIGs. 1A-1E are schematic, cross-sectional diagrams used to depict the steps involved in a conventional method for fabricating an STI structure in an integrated circuit; and

FIGS. 2A-2G are schematic, cross-sectional diagrams used to depict the steps involved in the method of the invention for fabricating an STI structure in an integrated circuit.

A preferred embodiment of the method of the invention for fabricating an STI structure in integrated circuit is disclosed in full details in the following with reference to FIGS. 2A-2G.

Referring first to FIG. 2A, in the first step, a semiconductor substrate 200, such as a P-type silicon substrate, is prepared. Subsequently, a pad oxide layer 202 is formed over the substrate 200 through a thermal oxidation process for surface protection of the substrate 200. After this, a mask layer 204 is formed over the pad oxide layer 202, preferably from silicon nitride through a chemical vapor deposition (CVD) process.

Referring further to FIG. 2B, in the subsequent step, a selective etching process, such as a photolithographic and etching process, is performed to etch into a selected area of the wafer in an anisotropic manner. Etching proceeds successively through the mask layer 204 and the pad oxide layer 202 until reaching a predefined depth in the substrate 200. Through this process, a trench 206 is formed in the substrate 200.

Referring next to FIG. 2C, in the subsequent step, a thermal oxidation process is performed on the wafer, whereby the exposed part of the substrate 200 is oxidized to form a liner oxide layer 208 on the bottom and sidewalls of the trench 206. This liner oxide layer 208 is formed to such an extent as to come into junction with the pad oxide layer 202. Next, a dielectric material, preferably silicon oxide, is deposited through an atmospheric-pressure chemical vapor deposition (APCVD) process into the trench 206 and also over the top surface of the wafer to thereby form an insulating layer 210. During the APCVD process, it is preferable to use tetra-ethyl-ortho-silicate (TEOS) as the deposition source. After this, a densification process is performed on the wafer at a temperature of about 1.000.degree. C. in an oxygen environment for a continuous period of from 10 to 30 minutes so as to densify the insulating layer 210. In this densification process, oxygen is used instead of nitrogen to allow the resulting insulating layer 210 to be denser.

Referring next to FIG. 2D, in the subsequent step, a chemical-mechanical polishing (CMP) process is performed on the wafer until reaching the top surface of the mask layer 204, whereby all the surface part of the insulating layer 210 that is laid above the mask layer 204 is removed (the remaining part is here designated by the reference numeral 210a and is here and hereinafter referred to as an insulating plug). As mentioned in the background section of this specification, microscratches 212 are undesirably formed in the top surface of the resulting insulating plug 210a during the CMP process.

Referring further to FIG. 2E, in the subsequent step, a flowable, low-K (low dielectric constant) dielectric material is coated over the entire top surface of the wafer to thereby form a coating (referred to as a mending dielectric layer 222 in this specification) to a thickness of from about 2,500 .ANG.=0 to 3,000 .ANG.. The flowable low-K dielectric material can be either a spin-on polymer (SOP) selected from the group consisting of Flare, SILK, and Parylene, or a spin-on glass (SOG) such as a flowable oxide (Fox). The mending dielectric layer 222 can be formed by, for example, first performing a spin coating process to coat the selected, flowable dielectric material over the entire top surface of the wafer, covering both the mask layer 204 and the insulating plug 210a, and then performing a thermal-treatment process to cure the coating. Owing to its flowable quality before being cured, the mending dielectric layer 222 fills up all the microscratches 212 in the top surface of the insulating plug 210a, thus mending the scratched insulating plug 210a. This effectively combines the insulating plug 210a and the mending dielectric layer 222 into an integrated insulating layer.

Referring next to FIG. 2F, in the subsequent step, an etch-back process, such as a wet etch-back process or a dry etch-back process, is performed to etch away the mending dielectric layer 222 until exposing the mask layer 204. Through this process, the remaining insulating plug 210a is free from microscratches since those portions of the mending dielectric layer 222 that are filled in the microscratches 212 are not removed.

Referring next to FIG. 2G, in the subsequent step, the mask layer 204 is entirely etched away by using a hot phosphate solution as the etchant. Next, the pad oxide layer 202 is also entirely etched away by using hydrofluoric acid (HF) as the etchant. Through these two etching processes, the insulating plug 210a (FIG. 2F) is also partly etched away (the remaining part thereof is here designated by the reference numeral 210b for distinguishing purpose). The remaining insulating plug 210b and the liner oxide layer 208 in the previously formed trench 206 (FIG. 2B) in the substrate 200 in combination constitute the intended STI structure. As demonstratively illustrated in FIG. 2G, the insulating plug 210b in the resulting STI structure is substantially free from microscratches in the top surface thereof. As a result, the drawback of bridging effect across the insulating plug 210b in the prior art is here eliminated.

In conclusion, the method of the invention is characterized by the provision of a mending dielectric layer over the scratched insulating plug of the STI structure so as to mend the microscratches formed in the top surface of the insulating plug that are undesirably resulting from the CMP process. Since the mending dielectric layer is in flowable state when it is being coated over the wafer, it can fill up all the microscratches in the top surface of the insulating plug, thereby mending the microscratches. As a result the method of the invention can help eliminate the drawback of the bridging effect across the insulating plug that would otherwise occur in the case of the prior art. The method of the invention can thus help the resulting IC device to be more reliable in operation and also can help increase the good yield rate of the wafer fabrication.

The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.