US 5,994,942 AGrant
Buffer Circuit With Wide Dynamic Range
Issue Date:1999-11-30
•8 Claims
•5 Drawing Sheets
Abstract
A buffer circuit including current sources and switches to connect and disconnect current sources to an output node. The switches are controlled by voltage detectors for comparing an input signal with a reference level. When the reference level is a predetermined value, the amplitude of an output signal swings up to V.sub.CC and swings down to V.sub.EE.
Metadata
Assignee
- Kabushiki Kaisha Toshiba
Inventor
- Masashi Itoh
Application Information
Application Number:US 9680640
Filing Date:1997-11-12
Priority Date:1994-08-17
Art Unit:286
Classifications
IPC:
H03K 508
Field of Search:
327316;108;79;74;67;54;309;312;321;323;478;432
Patent Drawings (5 sheets)
Description
Field of the Invention
The present invention generally relates to a buffer circuit, and more particularly, relates to a buffer circuit for receiving an output signal of a 1-bit digital-to-analog converter circuit.
Background of the Invention
A digital-to-analog converter (DAC) is employed to output an analog signal which is directly applicable to analog equipment such as speakers. However to provide an output signal of the DAC to analog equipment, a buffer circuit is required to supply enough electric current drive the equipment.
FIG. 1 shows conventional buffer circuits.
Both of the bases of a first npn-bipolar transistor Q1 and a second pnp-bipolar transistor Q2 are connected to an input node 11. A collector of the first transistor Q1 is connected to a first power supply node 12, and an emitter of the first transistor Q1 is connected to a second power supply node 13 via a first constant current source I.sub.1. An emitter of the second transistor Q2 is connected to the first power supply node 12 via a second current source I.sub.2, and a collector of the second transistor Q2 is connected to the second power supply node 13.
A base, collector, and emitter of a third npn-bipolar transistor Q3 are connected to the emitter of the second transistor Q2, the node I.sub.2, and an output node 14, respectively. A base, collector, and emitter of a fourth pnp-bipolar transistor Q4 are connected to the emitter of the first transistor Q1, the second power supply node I.sub.3, and the output node 14, respectively.
FIG. 2 shows a relationship between an input signal V.sub.in and output signal V.sub.out of the buffer circuit shown in FIG. 1.
First, when a level of the input signal V.sub.in is between V.sub.BE and V.sub.CC -V.sub.BE with reference to a ground level (0V), all of the transistors Q1, Q2, Q3, and Q4 are in a conductive state. Therefore, the output signal V.sub.out varies linearly in accordance with the input signal V.sub.in. V.sub.CC represents a power supply voltage, and V.sub.BE represents a threshold voltage of bipolar transistors.
Second, when the level of the input signal V.sub.in is higher than V.sub.CC -V.sub.BE with reference to the ground level (0V), a voltage across the base and emitter of the second transistor Q2 is lower than the threshold voltage V.sub.BE, and the second transistor Q2 is in a non-conductive state. Therefore, current of the second constant current source I.sub.2 flows into the base of the third transistor Q3, and the third transistor Q3 remains in the conductive state. A voltage across the base and emitter of the fourth transistor Q4 is lower than the threshold voltage V.sub.BE, and the fourth transistor Q4 is in a non-conductive state. Therefore, the output signal V.sub.out is clipped at a level of V.sub.CC -V.sub.BE.
Finally, when the level of the input signal V.sub.in is lower than V.sub.BE with reference to a ground level (0V), a voltage across the base and emitter of the first transistor Q1 is lower than the threshold voltage V.sub.BE, and the first transistor Q1 is in a non-conductive state. Therefore, all the current of the first constant current source I.sub.1 flows into the base of the fourth transistor Q4, and the fourth transistor Q4 remains in the conductive state. A voltage across the base and emitter of the third transistor Q3 is lower than the threshold voltage V.sub.BE, and the third transistor Q3 is in the non-conductive state. Therefore, the output signal V.sub.out is clipped at a level of V.sub.BE.
In the conventional buffer circuit, as described above, when the level of the input signal V.sub.in is lower than the threshold voltage V.sub.BE, the output signal V.sub.out is clipped at the level of V.sub.BE, and when the level of the input signal V.sub.in is higher than V.sub.CC -V.sub.BE, the output signal V.sub.out is clipped at the level of V.sub.CC -V.sub.BE. Namely, a dynamic range of the output signal is .vertline.V.sub.CC -2.times.V.sub.BE .vertline..
It is well known that the typical value for V.sub.BE of a bipolar transistor is 0.7V. Therefore, if the power supply voltage V.sub.CC is 3V, the dynamic range of the output signal is 1.6V (=3V-2.times.0.7V).
The narrow dynamic range leads to a distortion in the output signal. The distortion may be eliminated by attenuating the input signal. However, attenuating the input signal leads to deterioration in signal-to-noise (S/N) ratio. These problems are serious in low-supply-voltage circuits.
Summary of the Invention
It is an object of the invention to provide an improved buffer circuit that is not subject to the above described problems and disadvantages.
It is an additional object of the present invention to provide an improved buffer circuit wherein the dynamic ranges of the input and output signal are the same as the supply voltage.
In accordance with the present invention, the foregoing objects, among others, are achieved by providing a buffer circuit comprising an input node, an output node, an output stage coupled to the output node, first and second switch circuits coupled to the output node, a first current source coupled to the first switch circuit, and a second current source coupled to the second switch circuit. The second current source is coupled to a first power supply node, and the first current source is coupled to a second power supply node. The buffer circuit further comprises a first level detector including a first reference level generator and a first switch controller, the first reference level generator generating a first reference level; and a second level detector including a second reference level generator and a second switch controller, the second reference level generator generating a second reference level. Wherein, when a voltage level of the input node is lower than the first reference level, the first level detector controls the first switch circuit so as to couple the first current source to the output node, and when the voltage level of the input node is higher than the second reference level, the second level detector controls the second switch circuit so as to couple the second current source to the output node.
In accordance with another aspect of the present invention, the above stated objects are achieved by providing a buffer circuit comprising a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, the second collector being coupled to an output node, and the second emitter being coupled to the first base, with the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third base, with the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter coupled to the output node; and a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
Brief Description of the Drawings
A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description considered in connection with the accompanying drawings, in which:
FIG. 1 is a block diagram of a conventional buffer circuit;
FIG. 2 is a waveform chart showing the input and output signals of the conventional buffer circuit shown in FIG. 1;
FIG. 3 is a block diagram of a buffer circuit according to the present invention;
FIG. 4 is a block diagram showing details of the block diagram in FIG. 3;
FIG. 5 is a block diagram of a buffer circuit according to a first embodiment of the present invention;
FIG. 6 is a waveform chart showing the input and output signals of the buffer circuit shown in FIG. 5;
FIG. 7 a block diagram of a buffer circuit according to a second embodiment of the present invention;
FIG. 8 is a block diagram of a buffer circuit according to a third embodiment of the present invention;
FIG. 9 is a block diagram of a buffer circuit according to a fourth embodiment of the present invention;
FIG. 10 is a block diagram of a buffer circuit according to a fifth embodiment of the present invention; and
FIG. 11 is a block diagram of a buffer circuit according to a sixth embodiment of the present invention.
Description of Preferred Embodiments
Embodiments of the present invention will be described in detail with reference to the drawings.
Referring now to FIGS. 1 and 2, the abstract idea of the present invention will be explained. FIG. 3 is a block diagram of a buffer circuit according to the present invention.
The input signal V.sub.in is input to an input stage 11, and an output signal is output from an output stage 12. The input stage 11 may be a node for receiving a signal, and the output stage 12 may be for example, a single ended push-pull (SEPP) circuit. A first level detector includes a first switch controller 13a, which controls a switch circuit 15a, and a first reference level generator 14a. The switch circuit 15a connects or disconnects a first current source 16a and an output node 17. A second level detector includes a second switch controller 13b, which controls a switch circuit 15b, and a second reference level generator 14b. The switch circuit 15b connects or disconnects a second current source 16b and the output node 17.
When the level of the input signal is lower than a first reference level V.sub.1, generated by the first reference level generator 14a, the first switch controller 13a controls the first switch circuit 15a to connect the first current source 16a to the output node 17. When the level of the input signal is higher than a second reference level V.sub.2, generated by the second reference level generator 14b, the second switch controller 13b controls the second switch circuit 15b to connect the second current source 16b to the output node 17.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels of the reference level generators 14a and 14b vary, the dynamic range of the output signal varies in accordance with the reference levels.
In FIG. 4, the first and second level detectors are shown in detail. Each switch controller includes a differential amplifier D.A., and the reference level generators include a constant voltage source, respectively.
The first embodiment of the present invention will be explained with reference to FIG. 5.
A first npn-bipolar transistor Q11 and a second npn-bipolar transistor Q12 form a first differential amplifier. A base, collector, and emitter of the first transistor Q11 are connected to the input node 11, a first power supply node 12, and a second power supply node 13 via the first constant current source I.sub.1, respectively. A level of the first power supply node is a predetermined positive value, and a level of the second power supply node is a ground level.
A base, collector, and emitter of the second transistor Q12 are connected to the first level generator 15, the output node 14, and the second power supply node 13 via the first constant current source I.sub.1, respectively.
A third pnp-bipolar transistor Q13 and a fourth pnp-bipolar transistor Q14 form a second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and the first power supply node 12 via the second constant current source I.sub.2, respectively.
A base, collector, and emitter of the fourth transistor Q14 are connected to the second level generator 16, the output node 14, and the first power supply node 12 via the second constant current source I.sub.2, respectively.
The first reference level generator 15 applies the first reference level V.sub.1 across the base of the second transistor Q12 and the second power supply node 13, and the second reference level generator 16 applies the second reference level V.sub.2 across the base of the fourth transistor Q14 and the first power supply node 12. Namely, a voltage level of the base of the second transistor Q12 is V.sub.1, (where V.sub.EE =0), and a voltage level of the base of the fourth transistor Q14 is V.sub.CC -V.sub.2.
The amplitude of the swing of the output signal V.sub.out is determined by the levels V.sub.1 and V.sub.2 of the first and second reference level generators 15 and 16.
A base, collector, and emitter of a fifth npn-bipolar transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the first power supply node 12, and the output node 14, respectively.
A base, collector, and emitter of a sixth pnp-bipolar transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
FIG. 6 shows a relationship between the input signal V.sub.in and output signal V.sub.out of the buffer circuit shown in FIG. 5.
Note that the level V.sub.CC of the first power supply node 12 is a predetermined positive value, and the level V.sub.EE of the second power supply node 13 is the ground level. Suppose that the levels V.sub.1 and V.sub.2 satisfy the following equations (1) and (2), respectively.
First, suppose that the level V.sub.in of the input signal is higher than the ground level (0V) and is lower than the level V.sub.1 at the base of the second transistor Q12. (namely, V.sub.1 >Vin>0)
Under this condition, of the two transistors constituting the first differential amplifier, the first transistor Q11 is in a non-conductive state, and the second transistor Q12 is in a conductive state. Of the two transistors constituting the second differential amplifier, the third transistor Q13 is in a conductive state, and the fourth transistor Q14 is in a non-conductive state.
Consequently, the current driven by the first constant current source I.sub.1 flows from the first power supply node 12 into the second power supply node 13 via the fifth and second transistors Q15 and Q12. Therefore, an instant level of the input signal V.sub.in is output as the output signal V.sub.out via the third and fifth transistors Q13 and Q15 because the fifth transistor Q15 forms an emitter follower to the third transistor Q13.
Here, the level of the output signal V.sub.out from the output node 14 may decrease until the second transistor Q12 is saturated by the fifth transistor Q15. Namely, the minimum level V.sub.out(min) of the output signal is represented as follows.
(Where the saturation voltage V.sub.CE(sat) of the second transistor Q12 is zero volt.)
In equation (3), when V.sub.1 is equal to V.sub.BE, V.sub.out(min) is equal to zero (0V), the output signal V.sub.out swings down to the ground level (0V). However, when V.sub.1 is lower than V.sub.BE, the output signal V.sub.out does not swing down to the ground level because the second transistor Q12 never turns on.
When V.sub.1 is equal to or higher than (V.sub.CC /2) and V.sub.2 is lower than (V.sub.CC /2), the input signal is transferred to the output node 14 via the third and fifth transistors Q13 and Q15 because the first transistor Q11 never turns on.
(b)
When the level V.sub.in of the input signal is higher than the level V.sub.1 of the base of the second transistor Q12 and is lower than the level V.sub.CC -V.sub.2 at the base of the fourth transistor Q14. (namely, V.sub.CC -V.sub.2 >Vin>V.sub.1)
Of the two transistors constituting the first differential amplifier, the first transistor Q11 is in a conductive state, and the second transistor Q12 is in a non-conductive state. Of the two transistors constituting the second differential amplifier, the third transistor Q13 is in a conductive state, and the fourth transistor Q14 is in a non-conductive state.
Consequently, the fifth and sixth transistors Q15 and Q16 are in a conductive state to form the single ended push-pull circuit. Therefore, the instant level of the input signal V.sub.in is output as the output signal V.sub.out via the first, sixth, third, and fifth transistors Q11, Q16, Q13, and Q5.
(c)
Finally, when the level V.sub.in of the input signal is higher than the level V.sub.CC -V.sub.2 of the base of the fourth transistor Q14 and is lower than the level V.sub.CC at the first power supply node 12. (namely, V.sub.CC >Vin>V.sub.CC -V.sub.2)
Of the two transistors constituting the first differential amplifier, the first transistor Q11 is in a conductive state, and the second transistor Q12 is in a non-conductive state. Of the two transistors constituting the second differential amplifier, the third transistor Q13 is in a non-conductive state, and the fourth transistor Q14 is in a conductive state.
Consequently, the current driven by the second constant current source I.sub.2 flows from the first power supply node 12 into the second power supply node 13 via the fourth and sixth transistors Q14 and Q16. Therefore, the instant level of the input signal V.sub.in is output as the output signal V.sub.out via the first and sixth transistors Q11 and Q16 because the sixth transistor Q16 forms an emitter follower to the first transistor Q11.
Here, the level of the output signal Vout from the output node 14 may increase until the fourth transistor Q14 is saturated by the sixth transistor Q16. Namely, the maximum level V.sub.out(max) of the output signal is represented as follows.
(Where that the saturation voltage V.sub.CE(sat) of the fourth transistor Q14 is zero)
In equation (4), when V.sub.2 is equal to V.sub.BE, V.sub.out(max) is equal to V.sub.CC, and therefore, the output signal V.sub.out swings up to the power supply voltage V.sub.CC. However, when V.sub.2 is lower than V.sub.BE, the output signal V.sub.out does not swing up to the power supply voltage V.sub.CC because the fourth transistor Q14 never turns on.
When .vertline.V.sub.2 .vertline. is equal to or larger than .vertline.V.sub.CC /2.vertline. and .vertline.V.sub.1 .vertline. is smaller than .vertline.V.sub.CC /2.vertline., the input signal is transferred to the output node 14 via the first and sixth transistors Q11 and Q16 because the third transistor Q13 never turns on.
Particularly, when V.sub.1 is equal to or higher than (V.sub.CC /2)+V.sub.BE and V.sub.2 is equal to or higher than (V.sub.CC /2)+V.sub.BE, the input signal is not transferred to the output node 14.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels generated by the reference level generators vary, the dynamic range of the output signal varies in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to be an arbitrary value. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE.
Next, the second embodiment of the present invention will be explained with reference to FIG. 7.
The buffer circuit shown in FIG. 7 is characterized by configurations of reference level generators 15 and 16, and the constant current sources I.sub.1 and I.sub.2. A seventh npn-bipolar transistor Q17 and a first resistor R.sub.1 form the first reference level generator 15, and an eighth pnp-bipolar transistor Q18 and a second resistor R.sub.2 form the second reference level generator 16. A ninth npn-bipolar transistor Q19 forms the first constant current source I.sub.1, and a tenth pnp-bipolar transistor Q20 forms the second constant current source I.sub.2.
The configuration of the buffer circuit according to the second embodiment will be explained in detail below.
First and second transistors Q11 and Q12 form the first differential amplifier. The base, collector, and emitter of the first transistor Q11 are connected to the input node 11, the first power supply node 12, and a collector of the ninth transistor Q19 constituting the first constant current source I.sub.1, respectively. An emitter of the ninth transistor Q19 is connected to the second power supply node 13, which level is the ground level.
The base, collector, and emitter of the second transistor Q12 are connected to one node of the first resistor R.sub.1 constituting the first level generator 15, the output node 14, and the collector of the ninth transistor Q19, constituting the first constant current source I.sub.1, respectively. The other node of the first resistor R.sub.1 is connected to a base and collector of the seventh transistor Q17. An emitter and the base of the seventh transistor are connected to the second power supply node 13 and a base of the ninth transistor Q19, respectively.
The third and fourth transistors Q13 and Q14 form the second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and a collector of the tenth transistor Q20, constituting the second constant current source I.sub.2, respectively.
A base, collector, and emitter of the fourth transistor Q14 are connected to one node of the second resistor R.sub.2, constituting the second reference level generator 16, the output node 14, and the collector of the tenth transistor Q20 constituting the second constant current source I.sub.2, respectively. The other node of the resistor R.sub.2 is connected to a base and collector of the eighth transistor Q18. An emitter and the base of the eighth transistor Q18 are connected to the first power supply node 12 and a base of the tenth transistor Q20, respectively.
A third constant current source I.sub.3 is connected between a node of the first resistor R.sub.1 and a node of the second resistor R.sub.2. A base, collector, and emitter of the fifth transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the first power supply node 12, and the output node 14, respectively. A base, collector, and emitter of the sixth transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
An emitter of the tenth transistor Q20 is connected to the first power supply node 12.
In the above mentioned buffer circuit, suppose that the constant current generated by the third constant current source is I.sub.3, resistances of the first and second resistors are R.sub.1 and R.sub.2, and a voltage across the base and emitter of the transistors Q17 and Q18 is V.sub.BE, voltages applied to the base of the second and fourth transistors Q12 and Q14 are V.sub.BE +I.sub.3 .times.R.sub.1 and V.sub.CC -(V.sub.BE +I.sub.3 .times.R.sub.2), respectively. Namely, V.sub.1 and V.sub.2 are represented as follows.
The first resistor R.sub.1 is provided to prevent the first constant current source, or ninth transistor Q19, from saturating, and the second resistor R.sub.2 is provided to prevent the second constant current source, or tenth transistor Q20, from saturating.
In this embodiment, the third constant current source I.sub.3 is provided to drive the first and second reference level generators 15 and 16. Further, the first and second constant current sources I.sub.1 and I.sub.2 are also driven by the third constant current source I.sub.3.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels by the reference level generators 15 and 16 vary, the dynamic range of the output signal varies in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to an arbitrary value. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE.
Next, the third embodiment of the present invention will be explained with reference to FIG. 8.
The buffer circuit shown in FIG. 8 is characterized by configurations of the reference level generators 15 and 16, and the constant current sources I.sub.1 and I.sub.2. The seventh npn-bipolar transistor Q17 forms the first reference level generator 15, and the eighth pnp-bipolar transistor Q18 forms the second reference level generator 16. The ninth npn-bipolar transistor Q19 forms the first constant current source I.sub.1, and the tenth pnp-bipolar transistor Q20 forms the second constant current source I.sub.2. Each emitter area of the second and fourth transistors Q12 and Q14 is N-times larger than that of the transistors Q.sub.19 and Q.sub.20.
The configuration of the buffer circuit according to this embodiment will be explained in detail.
All of the first, second, fifth, seventh, and ninth transistors are npn-bipolar transistors, and all of the third, fourth, sixth, eighth, and tenth transistors are pnp-bipolar transistors.
The first and second transistors Q11 and Q12 form the first differential amplifier. A base, collector, and emitter of the first transistor Q11 are connected to the input node 11, the first power supply node 12, and a collector of the ninth transistor Q19 constituting the first constant current source I.sub.1, respectively. An emitter of the ninth transistor Q19 is connected to the second power supply node 13 whose level is the ground level.
The base, collector, and emitter of the second transistor Q12 are connected to the base and collector of the seventh transistor Q.sub.17 constituting the first level generator 15, the output node 14, and the collector of the ninth transistor Q19, respectively. An emitter and base of the seventh transistor Q17 are connected to the second power supply node 13 and a base of the ninth transistor Q19, respectively.
The third and fourth transistors Q13 and Q14 form the second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and a collector of the tenth transistor Q20 constituting the second constant current source I.sub.2, respectively. An emitter of the tenth transistor 20 is connected to the first power supply node 12.
A base, collector, and emitter of the fourth transistor Q14 are connected to a base and collector of the eighth transistor Q18 constituting the second reference level generator 16, the output node 14, and the collector of the tenth transistor Q20, respectively. The emitter and the base of the eighth transistor Q18 are connected to the first power supply node 12 and a base of the tenth transistor Q20, respectively.
The third constant current source I.sub.3 is connected between collectors of the seventh and eighth transistors. A base, collector, and emitter of the fifth transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the first power supply node 12, and the output node 14, respectively. A base, collector, and emitter of the sixth transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
In the above mentioned buffer circuit, when the constant current driven by the third constant current source is I.sub.3, voltages across the base and emitter of the transistors Q17 and Q18 are V.sub.BE, and voltages applied to the base of the second and fourth transistors Q12 and Q14 are V.sub.BE and V.sub.CC -V.sub.BE, respectively, V.sub.1 and V.sub.2 are represented as follows.
Therefore, the dynamic range of the output signal Vout is equal to .vertline.V.sub.CC .vertline..
An emitter area of the second transistor Q12 is N-times larger than that of the ninth transistor Q19 to prevent the first constant current source I.sub.1, or the ninth transistor Q19, from saturating. An emitter area of the fourth transistor Q14 is N-times larger than that of the tenth transistor Q20 to prevent the second constant current source I.sub.2, or the tenth transistor Q20 from saturating. A drop in V.sub.BE, or .DELTA.V.sub.BE, is represented as follows.
(V.sub.T : thermal voltage of the transistor, 26 mV)
For example, when a number "N" is 4, a voltage across the base and the emitter of the second transistor Q12 (V.sub.BE(Q12)) is lower than that of the ninth transistor Q19 (V.sub.BE(Q19)) by 36 mV. When a number "N" is 8, V.sub.BE(Q12) is lower than V.sub.BE(Q19) by 54 mV. Namely, the threshold voltages of the second and fourth transistors Q12 and Q14 are lower than those of the ninth and tenth transistors Q19 and Q20.
In this embodiment, the third constant current source I.sub.3 is provided to drive the first and second reference level generators 15 and 16. Further, the first and second constant current sources I.sub.1 and I.sub.2 are driven by the third constant current source I.sub.3.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels by the reference level generators 15 and 16 vary, the dynamic range of the output signal varies in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to be an arbitrary value. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, and the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE.
Next, the fourth embodiment of the present invention will be explained with reference to FIG. 9.
Compared with the buffer circuit according to the second embodiment, the buffer circuit shown in FIG. 9 is characterized by replacing the third constant current source I.sub.3 in FIG. 7 with a fourth constant current source I.sub.4, which is directly connected to the first power supply node 12.
The configuration of the buffer circuit according to this embodiment will be explained in detail.
All of the first, second, fifth, seventh, ninth, and eleventh transistors are npn-bipolar transistors, and all of the third, fourth, sixth, eighth, and tenth transistors are pnp-bipolar transistors.
The first and second transistors Q11 and Q12 form the first differential amplifier. A base, collector, and emitter of the first transistor Q11 are connected to the input node 11, one node of the second resistor R.sub.2 constituting the second reference level generator 16, and a collector of the ninth transistor Q19 constituting the first constant current source I.sub.1, respectively. An emitter of the ninth transistor Q19 is connected to the second power supply node 13 whose level is the ground level.
A base, collector, and emitter of the second transistor Q12 are connected to the one node of the first resistor R.sub.1 constituting the first reference level generator 15, the output node 14, and the collector of the ninth transistor Q19, respectively. The other node of the first resistor R.sub.1 is connected to a base and collector of the seventh transistor Q17. An emitter and the base of the seventh transistor are connected to the second power supply node 13 and the base of the ninth transistor Q19, respectively.
The third and fourth transistor Q13 and Q14 form the second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and the collector of a tenth transistor Q20 constituting the second constant current source I.sub.2, respectively.
The base, collector, and emitter of the fourth transistor Q14 are connected to one node of the second resistor R.sub.2, the output node 14, and the collector of the tenth transistor Q20, respectively. The other node of the resistor R.sub.2 is connected to a base and collector of the eighth transistor Q18. The emitter and the base of the eighth transistor Q18 are connected to the first power supply node 12 and a base of the tenth transistor Q20, respectively.
The fourth constant current source I.sub.4 is connected between the first power supply node and one node of the first resistor R.sub.1. A base, collector, and emitter of the fifth transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the first power supply node 12, and the output node 14, respectively. A base, collector, and emitter of the sixth transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
A base, collector, and emitter of the eleventh transistor Q21 are connected to the one node of the first resistor R.sub.1 constituting the first reference level generator 15, the bases of the eighth and tenth transistors Q18 and Q20, and the collector of the ninth transistor Q19, respectively.
The eleventh transistor Q21 is provided to drive the eighth and tenth transistors Q18 and Q20 even if the first transistor Q11 is in a non-conductive state. Namely, the third and tenth transistors Q13 and Q20 are in a conductive state because the eleventh transistor Q21 is in a conductive state, even if the first transistor Q11 is in a non-conductive state.
An emitter of the tenth transistor Q20 is connected to the first power supply node 12.
In the above mentioned buffer circuit, when constant current generated by the fourth constant current source is I.sub.4, resistances of the first and second resistors are R.sub.1 and R.sub.2, voltages across the base and emitter of the transistors Q17 and Q18 is V.sub.BE, and voltages applied to the base of the second and fourth transistors Q12 and Q14 are V.sub.BE +I.sub.4 .times.R.sub.1 and V.sub.CC -(V.sub.BE +I.sub.4 .times.R.sub.2), respectively, V.sub.1 and V.sub.2 are represented as follows.
The first resistor R.sub.1 is provided to prevent the first constant current source, or ninth transistor Q19, from saturating, and the second resistor R.sub.2 is provided to prevent the second constant current source, or tenth transistor Q20, from saturating.
In this embodiment, the fourth constant current source I.sub.4 is provided to drive the first reference level generator 15. Further, the first and second constant current sources I.sub.1 and I.sub.2, and the second reference level generator 16 are driven by the fourth constant current source I.sub.4.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels by the reference level generators 15 and 16 vary, the dynamic range of the output signal varies in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to be an arbitrary value. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, and the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE.
Next, the fifth embodiment of the present invention will be explained with reference to FIG. 10.
Compared with the buffer circuit according to the second embodiment, the buffer circuit shown in FIG. 10 is characterized by replacing the third constant current source I.sub.3 in FIG. 8 with the fourth constant current source I.sub.4, which is directly connected to the first power supply node 12.
The configuration of the buffer circuit according to this embodiment will be explained in detail.
All of the first, second, fifth, seventh, ninth, and eleventh transistors are npn-bipolar transistors, and all of the third, fourth, sixth, eighth, and tenth transistors are pnp-bipolar transistors.
The first and second transistors Q11 and Q12 form the first differential amplifier. A base, collector, and emitter of the first transistor Q11 are connected to the input node 11, a collector of the eighth transistor Q18 constituting the second reference level generator 16, and a collector of the ninth transistor Q19 constituting the first constant current source I.sub.1, respectively. An emitter of the ninth transistor Q19 is connected to the second power supply node 13 whose level is the ground level.
A base, collector, and emitter of the second transistor Q12 are connected to a base and collector of the seventh transistor Q17 constituting the first reference level generator 15, the output node 14, and the collector of the ninth transistor Q19, respectively. The emitter and the base of the seventh transistor are connected to the second power supply node 13 and a base of the ninth transistor Q19, respectively.
The third and fourth transistors Q13 and Q14 form the second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and the collector of the tenth transistor Q20 constituting the second constant current source, respectively.
A base, collector, and emitter of the fourth transistor Q14 are connected to a base and collector of the eighth transistor Q18 constituting the second reference level generator 16, the output node 14, and the collector of the tenth transistor Q20, respectively. The emitter and the base of the eighth transistor Q18 are connected to the first power supply node 12 and a base of the tenth transistor Q20, respectively.
The fourth constant current source I.sub.4 is connected between the first power supply node and the collector of the seventh transistor Q17. A base, collector, and emitter of the fifth transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the second power supply node 12, and the output node 14, respectively. A base, collector, and emitter of the sixth transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
A base, collector, and emitter of the eleventh transistor Q21 are connected to the base of the seventh transistor Q17, the bases of the eighth and tenth transistors Q18 and Q20, and the collector of the ninth transistor Q19, respectively.
An emitter of the tenth transistor Q20 is connected to the first power supply node 12.
The eleventh transistor Q21 is provided to drive the tenth transistor Q20 even if the first transistor Q11 is in a non-conductive state. Namely, the third and tenth transistors Q13 and Q20 are in a conductive state because the eleventh transistor Q21 is in a conductive state, even if the first transistor Q11 is in a non-conductive state.
In the above mentioned buffer circuit, when constant current generated by the fourth constant current source is I.sub.4, voltages across the base and emitter of the transistors Q17 and Q18 are V.sub.BE, and voltages applied to the base of the second and fourth transistors Q12 and Q14 are V.sub.BE and V.sub.CC -V.sub.BE, respectively, V.sub.1 and V.sub.2 are represented as follows.
Therefore, the dynamic range of the output signal Vout is equal to .vertline.V.sub.CC .vertline..
Each emitter area of the second and eleventh transistors Q12 and 021 is N-times larger than that of the ninth transistor Q19 to prevent the first constant current source I.sub.1, or the ninth transistor Q19, from saturating. An emitter area of the fourth transistor Q14 is N-times larger than that of the tenth transistor Q20 to prevent the second constant current source I.sub.2, or the tenth transistor Q20, from saturating. For example, when a number "N" is 4, the voltage across the base and the emitter of the second transistor Q12 (V.sub.BE(Q12)) is lower than that of the ninth transistor Q19 (V.sub.BE(Q19)) by 36 mV. When a number "N" is 8, V.sub.BE(Q12) is lower than V.sub.BE(Q19) by 54 mV. Namely, the threshold voltages of the second, fourth, and eleventh transistors Q12, Q14, and Q21 are lower than those of the ninth and tenth transistors Q19 and Q20.
In this embodiment, the fourth constant current-source I.sub.4 is provided to drive the first and second reference level generators 15 and 16. Further, the first and second constant current sources I.sub.1 and I.sub.2 are driven by the fourth constant current source I.sub.4.
With this configuration, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals are equal to the supply voltage. Moreover, if the reference levels generated by the reference level generators 15 and 16 vary, the dynamic range of the output signal varies in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to an arbitrary value. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, and the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE.
Next, the sixth embodiment of the present invention will be explained with reference to FIG. 11.
The buffer circuit according to this embodiment is characterized by providing a control node for receiving a control signal to vary the amplitude of the swing of the output signal.
The configuration of the buffer circuit according to this embodiment will be explained in detail.
All of the first, second, fifth, seventh, and twelfth transistors are npn-bipolar transistors, and all of the third, fourth, sixth, eighth, and thirteenth transistors are pnp-bipolar transistors.
The first and second transistors Q11 and Q12 form the first differential amplifier. A base, collector, and emitter of the first transistor Q11 are connected to the input node 11, the first power supply node 12, and the second power supply node 13 via the first constant current source I.sub.1, respectively.
A base, collector, and emitter of the second transistor Q12 are connected to one node of the first resistor R.sub.1 constituting the first reference level generator 15, the output node 14, and the second power supply node 13 via the first constant current source I.sub.1, respectively. The other node of the resistor R.sub.1 is connected to a base and collector of the seventh transistor Q17. An emitter of the seventh transistor Q17 is connected to the second power supply node 13.
The third and fourth transistor Q13 and Q14 form the second differential amplifier. A base, collector, and emitter of the third transistor Q13 are connected to the input node 11, the second power supply node 13, and the first power supply node 12 via the second constant current source I.sub.2, respectively.
A base, collector, and emitter of the fourth transistor Q14 are connected to one node of the second resistor R.sub.2 constituting the second reference level generator 16, the output node 14, and the first power supply node 12 via the second constant current source I.sub.2, respectively. The other node of the resistor R.sub.2 is connected to a base and collector of the eighth transistor Q18. An emitter and the base of the eighth transistor Q18 are connected to the first power supply node 12 and a base of the thirteenth transistor Q23, respectively.
The first resistor R.sub.1 and the seventh transistor Q17 form the first reference level generator 15 to apply the first reference level V.sub.1 across the base of the second transistor Q12 and the second power supply node 13. The second resistor R.sub.2 and the eighth transistor Q18 form the second reference level generator 16 to apply the second reference level V.sub.2 across the base of the fourth transistor Q14 and the first power supply node 12. The amplitude of the swing of the output signal is determined by the first and second reference levels V.sub.1 and V.sub.2.
A base, collector, and emitter of the fifth transistor Q15 are connected to the emitters of the third and fourth transistors Q13 and Q14, the first power supply node 12, and the output node 14, respectively. A base, collector, and emitter of the sixth transistor Q16 are connected to the emitters of the first and second transistors Q11 and Q12, the second power supply node 13, and the output node 14, respectively.
A base, collector, and emitter of the twelfth transistor Q22 are connected to the control node 30, the one node of the second resistor R.sub.2, and the second power supply node 13 via a third resistor R.sub.3, respectively. The twelfth transistor Q22 forms a controllable current source.
The base, collector, and emitter of the thirteenth transistor Q23 are connected to the base to the eighth transistor Q18, the one node of the first resistor R.sub.1, and the first power supply node 12, respectively. The eighth and thirteenth transistors Q18 and Q23 form a current mirror circuit.
With this configuration, the level of the control signal applied to the control node 30 is varied to vary the amount of current flowing through the controllable current source, or the twelfth transistor Q22. Namely, suppose that current flowing through the controllable current source is I.sub.var, the voltages across the base and emitter of the transistors Q17 and Q18 are V.sub.BE, and voltages applied to the base of the second and fourth transistors Q12 and Q14 are V.sub.BE +I.sub.var .times.R.sub.1 and V.sub.CC -(V.sub.BE +I.sub.var .times.R.sub.2), respectively. Namely, V.sub.1 and V.sub.2 are represented as follows.
From the equations (3) and (4), V.sub.out(min), V.sub.out(max) have already been known.
Therefore, V.sub.out(min) and V.sub.out(max) are represented as follows.
It is apparent from these equations that the dynamic range of the output signal is controlled by the control signal applied to the control node 30. Consequently, the amplitude of the output signal is easily controlled in digital signal processing, and muting is also achieved easily.
According to the present invention, the buffer circuit can be operable at a low power supply voltage, and the dynamic range of the input and output signals is equal to the supply voltage. When the level of the first power supply node 12 is V.sub.CC and the level of the second power supply node 13 is zero (0V), the widest dynamic range (.vertline.V.sub.CC .vertline.) is available with V.sub.1 and V.sub.2 being V.sub.BE, and the narrowest dynamic range (0) is available with V.sub.1 and V.sub.2 being (V.sub.CC /2)+V.sub.BE. Thus, the problems in the conventional buffer circuit are overcome.
Moreover, if the reference levels generated by the reference level generators 15 and 16 are varied, the dynamic range of the output signal is varied in accordance with the reference levels. Namely, the amplitude of the swing of the output signal may be selected to be an arbitrary value by the control signal applied to the control node 30.
While there has been illustrated and described what are presently considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for devices thereof without departing from the true scope of the invention. In addition many modifications may be made to adapt a particular situation or material to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention include all embodiments falling within the scope of the appended claims.
Claims
What is claimed is:
1. A buffer circuit comprising: a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, and the second collector being coupled to an output node, the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third emitter, the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter being coupled to the output node; and a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node, and further comprising a third current source, wherein the first reference level generator includes a first resistor and a seventh transistor coupled in series between the second base and the second power supply node; the second reference level generator includes a second resistor and an eighth transistor coupled in series between the fourth base and the first power supply node; the first current source includes a ninth transistor, wherein the ninth transistor and the seventh transistor form a first current mirror circuit; the second current source includes a tenth transistor, wherein the tenth transistor and the eighth transistor form a second current mirror circuit; and the third current source is coupled between the first and second resistors.
2. A buffer circuit comprising: a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, and the second collector being coupled to an output node, the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third emitter, the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter being coupled to the output node; and a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node, and further comprising a third current source, wherein the first reference level generator includes a seventh transistor having a seventh base, a seventh emitter, and a seventh collector, the seventh base and the seventh collector being coupled to the second base, and the seventh emitter being coupled to the second power supply node; the second reference level generator includes an eighth transistor having an eighth base, an eighth emitter, and an eighth collector, the eighth base and the eighth collector being coupled to the fourth base, and the eighth emitter being coupled to the first power supply node; the first current source includes a ninth transistor having a ninth base, a ninth emitter, and a ninth collector, the ninth transistor and the seventh transistor forming a first current mirror circuit; the second current source includes a tenth transistor having a tenth base, a tenth emitter, and a tenth collector, the tenth transistor and the eighth transistor forming a second current mirror circuit; a threshold voltage of the second transistor is lower than that of the ninth transistor; a threshold voltage of the fourth transistor is lower than that of the tenth transistor; and the third current source is coupled between the seventh collector and the eighth collector.
3. The buffer circuit according to claim 2, wherein an area of the second emitter is larger than an area of the ninth emitter; and an area of the fourth emitter is larger than an area of the tenth emitter.
4. A buffer circuit comprising: a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, and the second collector being coupled to an output node, the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third emitter, the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter being coupled to the output node; a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node, and further comprising a third current source; a third current source; and an eleventh transistor having an eleventh base, an eleventh emitter, and an eleventh collector, wherein the first reference level generator includes a first resistor and a seventh transistor coupled in series between the second base and the second power supply node; the second reference level generator includes a second resistor and an eighth transistor coupled in series between the fourth base and the first power supply node; the first current source includes a ninth transistor, and the ninth transistor and the seventh transistor form a first current mirror circuit; the second current source includes a tenth transistor, and the tenth transistor and the eighth transistor form a second current mirror circuit; the first collector is coupled to the first power supply node via the second reference level generator; the third current source is coupled between the first power supply node and the first reference level generator; and the eleventh base being coupled to the first reference level generator, the eleventh collector being coupled to the eighth and tenth bases, and the eleventh emitter being coupled to the ninth collector.
5. A buffer circuit comprising: a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, and the second collector being coupled to an output node, the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third emitter, the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter being coupled to the output node; a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node, and further comprising a third current source; and a third current source and an eleventh transistor having an eleventh base, an eleventh emitter, and an eleventh collector, wherein: the first reference level generator includes a seventh transistor having a seventh base, a seventh emitter, and a seventh collector, the seventh base and the seventh collector being coupled to the second base, and the seventh emitter being coupled to the second power supply node; the second reference level generator includes an eighth transistor having an eighth base, an eighth emitter, and an eighth collector, the eighth base and the eighth collector being coupled to the fourth base, and the eighth emitter being coupled to the first power supply node; the first current source includes a ninth transistor having a ninth base, a ninth emitter, and a ninth collector, the ninth transistor and the seventh transistor forming a first current mirror circuit; the second current source includes a tenth transistor having a tenth base, a tenth emitter, and a tenth collector, the tenth transistor and the eighth transistor forming a second current mirror circuit; the first collector being coupled to the first power supply node via the second reference level generator; the third current source being coupled between the first power supply node and the first reference level generator; the eleventh base being coupled to the first reference level generator, the eleventh collector being coupled to the eighth base and the tenth base, and the eleventh emitter being coupled to the ninth collector; a threshold voltage of the second transistor and the eleventh transistor being lower than that of the ninth transistor; and a threshold voltage of the fourth transistor being lower than that of the tenth transistor.
6. The buffer circuit according to claim 5, wherein: an area of the second emitter and the eleventh emitter is larger than an area of the ninth emitter; and an area of the fourth emitter is larger than an area of the tenth emitter.
7. A buffer circuit comprising: a first transistor having a first base, a first collector, and a first emitter, the first base being coupled to an input node and the first collector being coupled to a first power supply node; a second transistor having a second base, a second collector, and a second emitter, the second base being coupled to a first reference level generator, and the second collector being coupled to an output node, the first and second transistors constituting a first differential amplifier; a third transistor having a third base, a third collector, and a third emitter, the third base being coupled to the input node and the third collector being coupled to a second power supply node; a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth base being coupled to a second reference level generator, the fourth collector being coupled to the output node, and the fourth emitter being coupled to the third emitter, the third and fourth transistors constituting a second differential amplifier; a first constant current source coupled between the first and second emitters and the second power supply node; a second constant current source coupled between the third and fourth emitters and the first power supply node; a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base being coupled to the third and fourth emitters, the fifth collector being coupled to the first power supply node, and the fifth emitter being coupled to the output node; a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base being coupled to the first and second emitters, the sixth collector being coupled to the second power supply node, and the sixth emitter being coupled to the output node, and further comprising a third current source; and a variable current source and a ninth transistor, wherein: the first reference level generator includes a first resistor and a seventh transistor coupled in series between the second base and the second power supply node; the second reference level generator includes a second resistor and an eighth transistor coupled in series between the fourth base and the first power supply node; the variable current source is coupled to the second reference level generator for driving the second reference level generator; the ninth transistor and the eighth transistor form a current mirror circuit; and the ninth transistor is coupled to the first reference level generator for driving the first reference level generator by the variable current source.
8. The buffer circuit according to claim 7, wherein the variable current source includes a tenth transistor having a base coupled to a control node, and a variable current is controlled by a control signal applied to the control node.
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