Modified Gate Structure for Non-Volatile Memory and Its Method of Fabricating the Same

1. Field of the Invention

The present invention relates to semiconductor integrated circuit fabrication technology. More particularly, the present invention relates to a modified gate structure for non-volatile memory and its method of fabricating the same.

2. Description of the Related Art

Non-volatile memory devices have been widely applied in electrical appliances, computers, instruments, etc., on account of a programmable facility and static storage after power-off FIG. 1 schematically a conventional gate structure of a non-volatile memory in a cross-sectional view. In the drawing, reference numeral 10 designates a semiconductor substrate. A first silicon dioxide layer 12 having a thickness of about 80.about.200 .ANG. and a dielectric constant of about 3.9 is formed on the substrate 10 on which a first polysilicon layer 13 is deposited as a floating gate of a non-volatile memory device. Then, an O/N/O layer 14 is formed on the first polysilicon layer 13. For example, the O/N/O layer 14 is configured with a three-layer structure comprising a second silicon dioxide layer of about 50 .ANG., a silicon nitride layer of about 200 .ANG., and a third silicon dioxide layer of about 50 .ANG.. Then, a second polysilicon layer 19 is deposited on the O/N/O layer 14 to be a control gate of the non-volatile memory device.

FIG. 2 schematically depicts an equivalent circuit diagram of the conventional gate structure pertaining to capacitive elements as shown FIG. 1, wherein the substrate 10 is grounded. In FIG. 2, C.sub.1 represents the capacitance between the control gate 19 and the floating gate 13, C.sub.2 represents the capacitance between the floating gate 13 and the substrate 10, and both are connected in series. V.sub.1 designates an voltage applied to the control gate, which is coupled to the floating gate 13 through the capacitance C.sub.1 as a voltage V.sub.2, wherein V.sub.2 =[C.sub.1 /(C.sub.1 +C.sub.2)]V.sub.1. Accordingly, the applying voltage V.sub.1 should be so high enough that the coupled voltage V.sub.2 is able to induce electrons injection by means of tunneling effect into the floating gate 13.

General speaking, a non-volatile memory device with the conventional gate structure depicted in FIG. 1 should be powered by quite a high applying voltage V.sub.1 (e.g., 12 V or more) inconvenient for circuit designers and users.

To lower the desired applying voltage V.sub.1, but sustain enough coupled voltage V.sub.2 for inducing tunneling effect, increasing of the capacitance C.sub.1 is a feasible approach. Usually, two ways are utilized to increase the capacitance C.sub.1 by: (1) increasing the capacitance area and (2) replacing the O/N/O with high dielectric constant material such as tantalum oxide (Ta.sub.2 O.sub.5) or BST (BaSrTiO.sub.3). However, the former will consume additional layout area which is unfavorable to integrated circuit miniaturization. The latter may deteriorate tantalum oxide (Ta.sub.2 O.sub.5) or BST while generally subjected to an annealing treatment after the formation of tantalum oxide or BST wherein oxygen contained therein may react with silicon to form silicon dioxide. Furthermore, reducing gas such as nitrogen employed during the subsequent processes causes tantalum oxide or BST defects through which a leakage current flows.

It is therefore an object of the present invention to provide a modified gate structure for a non-volatile memory device, which can avert the formation of silicon dioxide during an annealing treatment subjecting to tantalum oxide or BST.

It is another object of the present invention to provide a modified gate structure for a non-volatile memory device which can keep tantalum oxide or BST from exposing reducing gas used during subsequent processes without suffering from leakage.

The present invention achieves the above-indicated objects by providing a modified gate structure formed over a substrate. The modified gate structure from bottom to top comprises a first dielectric layer, a first conductive layer, a second dielectric layer formed on said first conductive layer, a third dielectric layer, a refractory metal layer, and a second conductive layer. The third dielectric layer is made of tantalum oxide or BST, and the refractory metal layer can be made of tungsten, platinum, titanium, molybdenum, and tantalum.

According to the present invention, the modified gate structure for a non-volatile memory device makes use of the second and third dielectric layers to acquire higher effective dielectric constant as compared with that of the conventional O/N/O material. Therefore, the corresponding capacitance can be greatly increased to lower the required applying voltage. Moreover, the second dielectric layer acts as a leakage barrier, and further the refractory metal layer is used to protect the tantalum oxide or BST from deterioration as well as invasion of reducing gas during subsequent processes.

The following detailed description, given by way of examples and not intended to limit the invention to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:

FIG. 1 schematically a conventional gate structure of a non-volatile memory in a cross-sectional view;

FIG. 2 schematically depicts an equivalent circuit diagram of the conventional gate structure pertaining to capacitive elements as shown FIG. 1;

FIGS. 3A-3G schematically depicts the process flow of manufacturing a gate structure of one preferred embodiment in accordance with the present invention; and

FIGS. 4A-4B schematically depicts the process flow of manufacturing a gate structure of another preferred embodiment in accordance with the present invention.

FIGS. 3A-3G schematically depicts the process flow of manufacturing a gate structure of one preferred embodiment in accordance with the present invention. However, a drain region and a source region have been omitted from the drawings because the present invention emphasizes the gate structure of the non-volatile memory device. The following will describe the process flow of forming a gate structure in detail in conjunction with the accompanying FIGS. 3A-3G

First, referring to FIG. 3A, a first dielectric layer 22 is formed on a substrate 20. Preferably, the first dielectric layer 22 is a thermally-grown silicon dioxide, having a thickness of about 80.about.200 .ANG. and a dielectric constant of about 3.9, while the substrate 20 is a silicon substrate. Sequentially, as shown in FIG. 3B, a first conductive layer 23 is formed to cover the first dielectric layer 22. Preferably, the first conductive layer 23 is a CVD-deposited polysilicon layer or amorphous silicon layer.

Then, referring to FIG. 3C, a second dielectric layer 24 is formed on the first conductive layer 23. Preferably, the second dielectric layer 24 is a thermally-grown or CVD-deposited silicon dioxide layer having a thickness of about 20.about.50 .ANG. and a dielectric constant of about 3.9. Thereafter, a third dielectric layer 25 is formed on the second dielectric layer 24 as shown in FIG. 3D. Preferably, the third dielectric layer 25 is provided with a dielectric constant greater than that of silicon dioxide or silicon nitride. For instance, the third dielectric layer 25, having a thickness of about 200.about.300 .ANG., may be made of tantalum oxide (dielectric constant is about 25) or BST (dielectric constant is about 100) formed by means of chemical vapor deposition or physical vapor deposition.

Next, as shown in FIG. 3E, a refractory metal layer 26 is formed on the third dielectric layer 25. Preferably, the refractory metal layer 26 can be made of tungsten, platinum, titanium, molybdenum, or tantalum. After that, an annealing treatment is performed to make the third dielectric layer 25 to be provided with a high dielectric constant. Moreover, a second conductive layer 29 is formed on the refractory metal layer 26, and, preferably, is a CVD-deposited polysilicon or amorphous silicon layer. Then, the second conductive layer 29, the refractory metal layer 26, the third dielectric layer 25, the second dielectric layer 24, the first conductive layer 23, and the first dielectric layer 22 are sequentially patterned and etched to formed a gate 30 by means of photolithography and, for example, plasma etching processes.

Referring to FIGS. 4A-4B, the process flow of a gate structure for a non-volatile memory device of one preferred embodiment of the present invention is schematically depicted. First, as shown in FIG. 4A, a first dielectric layer 22, preferably, a thermally-grown silicon dioxide layer, is formed to cover the substrate 20 and having a thickness of about 600.about.800 .ANG.. Then, a portion of the first dielectric layer 22 within the extent of the gate 30 (as shown in FIG. 3G) is thinned by means of photolithography and etching to form a local thinner portion 22A having a thickness of about 80.about.200 .ANG. as shown in FIG. 4B. Accordingly, the capacitance C.sub.2 between the floating gate 23 and the substrate 20 can be decreased so as to lower the applying voltage V.sub.1. However, the subsequent process steps are all similar to those depicted in FIGS. 3B.about.3G and have been omitted without redundancy.

According to the present invention, the modified gate structure for a non-volatile memory device makes use of silicon dioxide/tantalum oxide or silicon dioxide/BST two-layer structure so that effective dielectric constants are high up to 13.1 and 19.5, respectively, as compared with the conventional O/N/O layer (a silicon dioxide layer of about 50 .ANG., a silicon nitride layer of about 200 .ANG., and another silicon dioxide layer of about 50 .ANG.) of about 5.7. Therefore, the corresponding capacitance C.sub.1 can be greatly increased to lower the required applying voltage V.sub.1. Moreover, the second dielectric layer 24 acts as a barrier to avoid leakage, and further the refractory metal layer 25 is used to protect the tantalum oxide or BST from deterioration as well as invasion of reducing gas during subsequent processes.

While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents.