Method of Fabricating CMOS Transistors With a Planar Shallow Trench Isolation

1. Field of the Invention

The invention relates to a method of fabricating CMOS (Complementary Metal-Oxide-Semiconductor) transistors, and more particularly, to a method of fabricating CMOS transistors with planar shallow trench isolations.

2. Description of the Prior Art

In the present days, shallow trench isolation (STI) structures are recognized as an important configuration to fabricate CMOS transistors because the STI technologies offer lots of advantages. For example, a bird's beak is entirely eliminated and channel-stop dopant redistribution is reduced, and the structure is fully recessed to offer the potential of a completely planar surface when compared with the local oxidation of silicon (LOCOS) technology. In addition, the problem of field-oxide thinning in narrow isolation spaces does not occur. Furthermore, the threshold voltage is constant as a function of channel width because the narrow-channel effect found in LOCOS is also eliminated.

Because the STI structures have attractive advantages, there are amounts of processes continuously disclosed. Perera et al proposed an isolation method using oxide filled shallow trenches focus primarily at isolating CMOS devices and which has been developed for 0.25 .mu.m SRAM (Static Random Access Memory) fabrication (refer to "Trench Isolation for 0.45 .mu.m Active Pitch and Below" in IEDM Tech. Dig. P.679, 1995.) Fazan et al proposed an STI process that a vertical B field implant and forming of disposable spacers are combined to avoid devices reverse narrow width effects (refer to "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs" in IEDM Tech. Dig., p. 57, 1993.) Nag et al show an ICP (Inductive Coupled) HDP--(High Density Plasma) CVD (Chemical Vapor Deposition) process to obtain a low budget and high throughput approach as well as provide good gap-fill, low moisture uptake at 0.3 .mu.m spacing (refer to "Comparative Evaluation of Gap-Fill Dielectrics in Shallow Trench Isolation for Sub-0.25 .mu.m Technologies" in IEDM Tech. Dig., p841, 1996.)

Typically, a relative shallow trench isolation is first etched to form a recess structure in the silicon substrate, and then refilled with an insulator material. The surface is planarized after refill to complete the isolation structure. However, the STI process is hard to form a planar trench isolation (refer to "A Novel Planarization of Oxide-Filled Shallow-Trench Isolation" in J. Electrochem. Soc., vol., 144, p 315, 1997 disclosed by Cheng et al.), and usually, the STI technology requires a complicated planarization procedure. Conventionally, a combination of dry etch and CMP (Chemical Mechanical Polishing) with an extra mask to prevent dishing in wide field regions has been proposed to planarize a device surface. Another traditional approach applying only dry etch planarization requires a LOCOS isolation in wide field areas that will significantly increase the process complexity. A requirement has been arisen to disclose an STI process that forms CMOS transistors with planar surface and lower budgets.

Accordingly, the present invention discloses a method to form CMOS transistors with planar shallow trench isolations. After a twin well being formed, pad oxide/nitride films are deposited on a silicon substrate. When a photoresist film is patterned to define active regions, the silicon substrate is recessed by using the patterned photoresist film as a mask. Then, a liquid-phase-deposition (LPD) oxide film is grown for shallow trench isolations. A high temperature annealing procedure is then performed to densify the LPD oxide film. Finally, the CMOS transistors are fabricated on the silicon substrate after the pad oxide/nitride films are removed.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross section of a silicon substrate representative of when a silicon nitride film is formed over a pad oxide film on the silicon substrate;

FIG. 2 illustrates a cross-sectional view of the silicon substrate representative of when phosphorous ions are implanted to form an N-well in the silicon substrate;

FIG. 3 illustrates a cross-sectional view of the silicon substrate representative of when boron ions are implanted to form a P-well in the silicon substrate by using photoresist film as a mask covered the N-well;

FIG. 4 represents a cross section illustrative of when the photoresist film is removed;

FIG. 5 demonstrates a cross section representative of when another photoresist film is completely patterned on the nitride film for defining active regions;

FIG. 6 shows a cross-sectional view illustrative of when the silicon substrate is recessed by using the photoresist film as a mask;

FIG. 7 is a cross section representative of when a liquid-phase-deposition (LPD) oxide layer is grown on the recess structure of the silicon substrate;

FIG. 8 depicts a cross section of the silicon substrate that a high temperature anneal is performed to densify the LPD oxide layer after the photoresist is striped; and

FIG. 9 is a cross section of the silicon substrate after a CMOS transistor is fabricated on the silicon substrate.

FIG. 1 is a cross section of a silicon substrate 101 representative of when a nitride film 103 with a thickness of about 500 to 2000 .ANG. (angstrom) is formed over a pad oxide film 102. The pad oxide layer 102 is composed of silicon dioxide with a thickness of about 30 to 500 .ANG.. FIG. 2 illustrates a cross-sectional view representative of when phosphorous ions are implanted to form an N-well 104 in the silicon substrate 101. The depth of the N-well 104 is about 0.3 to 3.0 .mu.m, and the implanted phosphorous ions are at an energy about 200 KeV to 5.0 MeV, and at a dose between 1E12 to 1E14 atoms/cm.sup.2. FIG. 3 illustrates a cross-sectional view representative of when boron ions are implanted to form a P-well 106 in the silicon substrate 101 by using photoresist film 105 as a mask covered the N-well 104. The implanted boron ions are at an energy about 200 KeV to 4.0 MeV, and at a dose between 1E12 to 1L14 atoms/cm.sup.2.

Referring to FIG. 4, which represents a cross section illustrative of when the photoresist film 105 is striped. FIG. 5 demonstrates a cross section representative of when a photoresist film 107 is completely patterned on the nitride film 103 to define active regions. Then, a recess procedure is performed to form a recess structure 108 with a depth of about 0.1 to 1.0 .mu.m on the silicon substrate 101 by using the photoresist film 107 as a mask. Please note that conventional processes for forming recess structures can be applied in the invention. FIG. 6 shows a cross-sectional view illustrative of when the silicon substrate is completely recessed. Next, a liquid-phase-deposition (LPD) oxide film 109 is grown with a thickness of about 0.1 to 1.5 .mu.m to fill the recess structure 108. LPD is a room-temperature method for SiO.sub.2 formation, and the LPD oxide films can be obtained by adding either H.sub.3 BO.sub.3 or Al to a hydrofluosilicic acid (H.sub.3 SiF.sub.6) solution saturated with silica. An article titled "The Physicochemical Properties and Growth Mechanism of Oxide (SiO.sub.2- F.sub.x) by Liquid Phase Deposition with H.sub.2 O Addition Only" disclosed by Yen et al. in J. Electrochem. Soc., vol. 141, p.3177, 1994 proposed the mechanism while growing the LPD oxide films.

FIG. 7 shows a cross section representative of when the LPD oxide film 109 is completely grown. Finally, a high temperature O.sub.2 anneal is performed to densify the LPD oxide layer 109 after the photoresist film 107 is removed. The high temperature O.sub.2 anneal performs under a circumstance having a temperature in a range of 700 to 1100.degree.C. FIG. 8 depicts a cross section after the high temperature anneal is performed to densify the LPD oxide layer 109. Obviously, the method proposed in the present invention can be easily achieved by using a simpler process and lower thermal budget than the conventional STI technologies.

When the isolation regions are completely made for semiconductor devices, sequence processes for fabricating CMOS transistors are thus continued. For example, in FIG. 9 that shows a cross section illustrative of when a gate structure 110, and p+ layer 112 as source and drain for the PMOSFET, and forming a gate structure 111, and n+ layer 113 as source and drain for the NMOSFET.

As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.