Flash Eeprom Device Employing Polysilicon Sidewall Spacer as an Erase Gate

1. Field of the Invention

The present invention relates to a memory device and, in particular, to a source-side-injection Electrically Erasable Programmable Read Only Memory (EEPROM) device based on a Flash cell which employs a sidewall polysilicon spacer as an Erase Gate (EG).

2. Discussion of the Prior Art

In order to realize a Flash EEPROM array having a density of 16 Mbits or higher, technology innovations in both memory cell structure and array architecture are required. In the past, Intel's well-know "T-shaped" ETOX cell has been intensively utilized in Flash memory applications because of its small cell size and simple stack gate structure. Examples of such devices are described by Jinbo et al., "A 5V-Only 16 Mb Flash Memory with Sector Erase Mode", IEEE JSSC, P. 1547, 1992 and by Atsumi et al., "A 16 Mb Flash EEPROM with a New Self-Data-Refresh Scheme for a Sector Erase Operation", IEEE JSSC, P. 461, 1994. However, the conventional operation issues, such as high programming current and high erase band-to-band tunneling current place severe limitations on the power supply (V.sub.cc) scalability and cell size scalability. In fact, band-to-band tunneling current limits V.sub.cc scaling in an ETOX memory array with a large sector size (i.e. 512K bits per sector) architecture. Furthermore, band-to-band tunneling current limits cell size scaling because a source junction as deep as 0.2 um is required for a 0.35 um technology. That means source lateral diffusion takes more than one third of the transistor channel length and cell scalability is severely limited.

Source side injection Flash memory cells using a polysilicon sidewall spacer as a select gate (SG) are introduced to address the high programming current issue associated with the ETOX cell. Examples of such devices are described by Wu et al., "Electrically Programmable Memory Device Employing Source Side Injection", U.S. Pat. No. 4,794,565, 1988 and by Naruke et al., "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side", IEEE IEDM, P. 603, 1989. However, an individual polysilicon-sidewall-spacer line has to be strapped with a metal line in order to be switched as a word line during a read cycle and thus, memory array layout becomes metal pitch limited. Furthermore, the issue of high band-to-band tunneling current during erase was not addressed.

Jeng et al., "Single Transistor Non-volatile Electrically Alterable Semiconductor Memory Device with a Re-crystallized Floating Gate", U.S. Pat. No. 5,067,108, 1991, proposed a source-side-injection Flash cell with a non-self-aligned select transistor. This cell is erased by a poly-to-poly tunneling mechanism and thus, band-to-band tunneling current is eliminated. With this approach, an independent select transistor with a silicide gate is used to replace the sidewall spacer select transistor and thus, metal strapping is not necessary. However, this cell has two transistors in series plus a source coupling region and thus, cell size is inherently large. Furthermore, the select gate channel length is alignment sensitive and the source junction has to sustain a high voltage, both of which undesirably limit further cell scaling.

It is therefore the object of this invention to provide a memory device based on one of several disclosed compact Flash cells and associated memory arrays which requires low currents for both program and erase operations, and thus, the device is suitable for low V.sub.cc, low power, high density Flash memory applications.

Each of inventive cells has a control gate overlapping a sized-up floating gate (by "sized-up", it is meant that the length of the floating gate is longer than the length of the control gate) to form a stack gate. The stack gate is side by side with a sidewall spacer erase gate with a thin poly tunnel oxide between the erase gate and the floating gate, with a thicker dielectric layer between the erase gate and the control gate. Each of inventive cells is built on a P-type semiconductor substrate with self-aligned N-type source and drain regions. Each of inventive cells is programmed by channel hot electron injection at the source side of the floating gate transistor and erased by poly-to-poly tunneling through the poly tunnel oxide. Since the poly tunnel oxide thickness is minimized, a high lateral field (at the injection point) and a fast programming speed can be obtained. In addition, cell programming current is limited to less than 1 uA which enables the memory array based on this cell to be programmed in a page mode. Therefore, high speed programming with low power consumption can be achieved. By using a poly-to-poly erase scheme, band-to-band tunneling current during erase is advantageously eliminated. Therefore, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells can be erased simultaneously without a power consumption concern and further V.sub.cc scaling becomes possible. Since both program and erase power consumption are low, the inventive cell is suitable for low V.sub.cc, low power applications.

Based on the inventive cell, a NOR-type Flash EEPROM array is organized with bit lines running in the vertical direction while control gate word lines, source lines and erase gate lines run in the horizontal direction. This array is divided into sectors in which cell data can be altered by sector erase followed by page write.

This array is fabricated with a triple polysilicon process in which the sized-up floating gate poly is defined by the control gate sidewall dielectric spacer in a self-aligned etch process. After stack gate formation, a poly tunnel oxide is grown before forming the poly sidewall spacer erase gate. Since a deep N-well and a deep source junction are not used, the process complexity is comparable to that of the ETOX architecture. By reducing the depth of the source junction, this cell size is comparable to the ETOX cell.

In another embodiment of the invention, bit line parasitic capacitance in high speed applications is addressed. Namely, since the erase gate is conductive during a normal read operation, the erase gate channel introduces an additional gate capacitance component to the bit line capacitance. In order to minimize the bit line capacitance, an alternative cell design with the sidewall spacer erase gate on the source side of the stack gate is introduced for high speed applications.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following description of the preferred embodiments and accompanying description of the drawings and tables.

FIG. 1a is a sectional view illustrating an inventive source side injection cell which employs a sidewall polysilicon spacer on the drain side as an erase gate;

FIG. 1b is a cell schematic which shows the cell terminals of FIG. 1a;

FIG. 1c is a sectional view illustrating an alternative cell which employs a sidewall polysilicon spacer on the source side as an erase gate;

FIG. 1d is a cell schematic which shows the cell terminals of FIG. 1c;

FIG. 1e is a sectional view illustrating another alternative cell which employs an independent non-self-aligned select transistor at the drain side as an erase gate as well as a select gate (SG);

FIG. 1f is a sectional view illustrating another alternative cell which employs an independent non-self-aligned select transistor at the source side as an erase gate as well as a select gate;

FIG. 1g is a sectional view illustrating another alternative cell which employs an independent non-self-aligned select transistor as an erase gate as well as a select gate for a virtual ground memory array approach;

FIG. 1h is a layout of a virtual ground memory array based on the cell of FIG. 1g;

FIG. 2a is a layout around the source line contact of an array based on the cell of FIG. 1a;

FIG. 2b is a layout around the erase gate contacts of the array based on the cell of FIG. 1a;

FIG. 3 is a schematic of the memory array based on the cell of FIG. 1a;

FIG. 4a is a layout around the source line contact of an array based on the cell of FIG. 1c;

FIG. 4b is a layout around the erase gate contact of the array based on the cell of FIG. 1c;

FIG. 5 is a schematic of the memory array based on the cell of FIG. 1c;

FIGS. 6a, 6b, 6c and 6d are sectional views during a variety of process steps for an inventive cell which employs a sidewall polysilicon spacer on the drain side as an erase gate; and

FIGS. 7a, 7b, 7c and 7d are sectional views during a variety of process steps for an inventive cell which employs an independent select transistor on the drain side as a select gate.

In keeping with the objects of this invention, a more detailed description is given for the inventive cells, Flash EEPROM arrays based on these cells and their fabrication processes.

FIG. 1a is a sectional view of an inventive cell 114. A semiconductor substrate 100 of a first conductivity type (P-type) has a source region 105 and a drain region 108 of opposite conductivity type (i.e. both N-type) formed therein. Extending between the source region 105 and the drain region 108 is an active channel region 113. A floating gate (FG) 103 is surmounted by and sized-up from a control gate (CG) 101 to form a stack gate with a layer 102 of oxide/nitride/oxide (ONO) in between. According to the present invention, the stack gate structure is a non-mutually-aligned semiconductor structure, formation of which will be described below in the context of wafer processing. Between the floating gate 103 and the substrate 100 is a floating gate oxide layer 104.

Positioned above channel region 113 and to the side of stack gate 101, 103 is a polysilicon spacer 107 which is used as an erase gate (EG). A layer 106 between the control gate 101 and the erase gate 107 is a dielectric layer which has to be thick enough to prevent any leakage current therebetween. A poly tunnel oxide layer 109, through which cell erase tunneling takes place, is formed between the floating gate 103 and the erase gate 107. An erase gate oxide 112 is formed between the erase gate 107 and the channel region 113. Floating gate 103 and erase gate 107 are fabricated from polysilicon material while control gate 101 comprises polysilicon and tungsten silicide (WSi) materials to minimize the word line resistance. FIG. 1b is a cell schematic which lists cell terminals, namely control gate 101, drain 108, source 105 and erase gate 107.

Cell 114 is programmed by a well known source-side channel-hot-electron-injection mechanism to reach a high threshold voltage (V.sub.th) state (higher than V.sub.cc). To program cell 114, control gate 101 is biased at V.sub.pp (around 10V), erase gate 107 is biased around its threshold voltage, source 105 is biased at V.sub.src (around 4.5V) while drain 108 is biased near 0V. Under such bias conditions, channel hot electrons are generated within the erase-gate depletion region and injected onto floating gate 103 due to the presence of a high control gate bias. Since the thickness of poly tunnel oxide 109 (around 150 .ANG.) is minimized, a high lateral field is achieved within the erase gate depletion region and a fast programming speed can be obtained. In addition, cell programming current is determined by the erase gate bias which can be limited to 1 uA or less. Such a low current programming scheme enables an array 214 (see FIG. 2a) based on cell 114 to be programmed in page mode; that is to program one row of cells 114 at a time. Therefore, high speed programming with low power consumption can be achieved.

Cell 114 is erased by poly-to-poly tunneling through poly tunnel oxide layer 109. To erase cell 114, erase gate 107 is biased at V.sub.pe (around 10V), drain 108 is biased at an intermediate voltage (around V.sub.cc) while control gate 101 is grounded and source 105 is left floating. Under such bias conditions, electrons tunnel through poly tunnel oxide 109 and cell 114 is shifted towards a low threshold voltage state. The drain voltage is provided to reduce the field across erase gate oxide 112. Dielectric layer 106 between erase gate 107 and control gate 101 has to be thick enough (around 300 .ANG.) to eliminate leakage current therebetween. By using the poly-to-poly erase scheme, band-to-band tunneling current during erase is eliminated. Without the band-to-band tunneling current concern, a deep source junction is not used and cell size can be significantly reduced. Furthermore, a large sector of cells 114 can be erased simultaneously without a power consumption concern. In contradistinction to the invention, band-to-band tunneling current limits V.sub.cc scaling in the ETOX architecture with a large sector size (i.e. 512K bits per sector). In the present invention, using the poly-to-poly erase mechanism, cell 114 provides a solution for further V.sub.cc scaling, without compromising the sector size.

Because erase gate 107 is always conducting during the read operation, cell 114 shares the same over-erase issue as the conventional ETOX cell. To address this issue, a reverse programming scheme after an erase operation is used to shift the cell threshold voltage to a positive value. The bias condition of reverse programming in the inventive cell 114 is the same as that of normal programming except that control gate is biased at V.sub.pr which is around 7V. After reverse programming, a narrow cell threshold voltage distribution with a controllable mean value (around 0.5V) can be obtained and the over-erase issue can be solved.

Cell 114 is read by biasing control gate 101 at V.sub.cc (or a higher voltage for the pumped word line design), erase gate 107 around V.sub.cc and drain 108 around 1V while source 105 is grounded. The erase gate voltage needs to be high enough so that it won't limit cell read current, provided that there is no floating gate charge loss. The drain bias voltage is determined by the erase gate bias as well as the cell soft write characteristics. Since the spacing between erase gate 107 and floating gate 103 is minimized, there is no discontinuity within the conducting channel 113 and a high cell read current can be obtained.

An alternative approach in operating cell 114 is to use polysilicon sidewall spacer 107 as a select gate (SG) as well as an erase gate. With this approach, erase gate 107 is switched as the word line during read and the over-erase issue can be eliminated. To read cell 114, control gate 101 is biased at a reference voltage around V.sub.cc, erase gate 107 word line is biased at V.sub.cc (or a higher voltage for the pumped word line design) and drain 108 is biased around 1V while source 105 is grounded.

By moving the sidewall spacer erase gate 107 from the drain side to the source side, an alternative cell 120 can be obtained as shown in FIG. 1c. The operation of cell 120 is the same as that of cell 114 except that source and drain biases are transposed during both the erase and the program operations (compare Table 1 and Table 2 located immediately before the claims). To program cell 120, drain 108 is biased at a voltage around 4.5V while source 105 is grounded. To erase cell 120, source 105 is biased at a voltage around V.sub.cc while drain 108 is left floating. Since channel high voltage (which is around 4.5V) is applied to drain 108, cell 120 can be programmed only in a byte mode. Referring to FIG. 4a, although cell 120 cannot be programmed in a page mode, this cell 120 does offer the following advantages: (1) erase gate 107 is at the source side and the bit line capacitance is reduced; (2) erase gate lines 207 and source lines 205 (both horizontal-running) can be respectively connected with the first metal layer (metal 1) lines (not shown for clarity of illustration) which run in the vertical direction. Thus, A bit line segmentation scheme can be implemented with the second metal (metal 2) main bit line running in the vertical direction to further reduce the bit line capacitance.

Cell 120 is read by biasing control gate 101 at V.sub.cc (or a higher voltage for the pumped word line design), erase gate 107 around V.sub.cc and drain 108 around 1V while source 105 is grounded. Because erase gate 107 is always conducting during the read operation, cell 120 shares the same over-erase issue as the conventional ETOX cell. To address this issue, a reverse programming scheme after an erase operation is used to shift the cell threshold voltage to a positive value. To reverse-program cell 120, drain 108 is biased at V.sub.bp which is around 4.5V, control gate 101 is biased at V.sub.pr which is around 7V, erase gate 107 is biased at V.sub.eg which is around V.sub.th +0.5V and source 105 is biased around 0V. After reverse programming, a narrow cell threshold voltage distribution with a controllable mean value (around 0.5V) can be obtained and the over-erase issue is solved.

An alternative approach in operating cell 120 is to use polysilicon sidewall spacer 107 as a select gate (SG) as well as an erase gate. With this approach, erase gate 107 is switched as the word line during read and the over-erase issue can be eliminated. To read cell 120, control gate 101 is biased at a reference voltage around V.sub.cc, erase gate 107 word line is biased at V.sub.cc (or a higher voltage for the pumped word line design) and drain 108 is biased around 1V while source 105 is grounded.

Another alternative cell 121 which is similar to cell 114, is shown in FIG. 1e. In cell 121, the polysilicon sidewall spacer erase gate (e.g. see reference numeral 107 of FIG. 1a) is replaced by an independent non-self-aligned select gate 122 which functions as an erase gate as well as a select gate. Since select gate 122 is switched as a word line in cell 121 (as opposed to cell 114, in which control gate 101 is switched as a word line) during read, cell 121 cannot be over-erased even if the threshold voltage of the floating gate transistor is negative. Therefore, reverse programming is not required. Cell 121 is erased by poly-to-poly tunneling through poly tunnel oxide 109 between floating gate 103 and select gate 122 and programmed by source side channel hot electron injection between floating gate 103 and channel 113 at portions adjacent to select gate 122. To program cell 121, control gate 101 is biased at V.sub.pp (around 10V), select gate 122 is biased around its threshold voltage, source 105 is biased at V.sub.src (around 4.5V) while drain 108 is biased near 0V. To erase cell 121, select gate 122 is biased at V.sub.pe (around 10V), drain 108 is biased at an intermediate voltage (around V.sub.cc) while control gate 101 is grounded and source 105 is left floating.

Another alternative cell 123 which is similar to cell 120, is shown in FIG. 1f. In cell 123, the polysilicon sidewall spacer erase gate (e.g. see reference numeral 107 of FIG. 1c) is replaced by an independent non-self-aligned select gate 122 which functions as an erase gate as well as a select gate. Since select gate 122 is switched as a word line in cell 123 (as opposed to cell 120, in which control gate 101 is switched as a word line) during read, cell 123 cannot be over-erased even if the threshold voltage of the floating gate transistor is negative. Therefore, reverse programming is not required. Cell 123 is erased by poly-to-poly tunneling through poly tunnel oxide 109 between floating gate 103 and select gate 122 and programmed by source side channel hot electron injection between floating gate 103 and channel 113 at portions adjacent to select gate 122. To program cell 123, control gate 101 is biased at V.sub.pp (around 10V), select gate 122 is biased at a voltage slightly higher than its threshold voltage, drain 108 is biased around 4.5V while source 105 is biased near 0V. To erase cell 123, select gate 122 is biased at V.sub.pe (around 10V), source 105 is biased at an intermediate voltage (around V.sub.cc) while control gate 101 is grounded and drain 108 is left floating.

Another alternative cell 124 shown in FIG. 1g, having a select gate lying on both source 105 and drain 108 diffusion regions, is designed to be used in a virtual ground memory array. In such a virtual ground array, the select gate 125 word lines run perpendicularly to both control gate 101 polysilicon lines and source 105, drain 108 diffusion lines (see array layout shown in FIG. 1h). Also shown in FIG. 1h are field oxide region 210 and channel region 113. The sectional view shown in FIG. g is obtained along line A--A. Since the select gate 125 is switched as a word line during read, cell 124 cannot be over-erased even if the threshold voltage of the floating gate transistor is negative. Therefore, reverse programming is not required. Cell 124 is erased by poly-to-poly tunneling through poly tunnel oxides 109 and 109a between opposing sides of floating gate 103 and select gate 125. Cell 124 is programmed by source side channel hot electron injection between floating gate 103 and channel 113 at portions adjacent to select gate 125 transistor. As shown in FIG. 1g, in addition to thin dielectric layer 109, the other thin dielectric layer 109a is disposed between floating gate 103 and a portion of select gate 125. Thin dielectric layer 109a has substantially the same thickness as layer 109 and is formed at the same time. To program cell 124, control gate 101 is biased at V.sub.pp (around 10V), select gate 125 is biased at a voltage slightly higher than its threshold voltage, source 105 is biased at V.sub.src (around 4.5V) while drain 108 is biased near 0V. To erase cell 124, select gate 125 is biased at V.sub.pe (around 10V), drain 108 and source 105 are biased at an intermediate voltage (around V.sub.cc) while control gate 101 is grounded.

A NOR-type memory array 214 implemented with a plurality of cells 114, is shown in FIG. 2a. This layout is near a source contact 216. A similar layout around erase gate contacts 219 is shown in FIG. 2b. As seen in FIG. 2a, control gate word lines 201, diffusion source lines 205 and erase gate polysilicon lines 207 run in the horizontal direction and drain bit lines 208 run in the vertical direction. Also shown in FIG. 2a are field oxide 210 and drain bit line contacts 215 while metal lines are not included for clarity. In this architecture, vertically-running metal 1 lines strap bit lines 208 while horizontally-running metal 2 lines strap source lines 205 and erase gate lines 207. In order to reduce the capacitance associated with bit lines 208, a bit line segmentation scheme can be implemented by running metal 3 main bit lines in the vertical direction.

In this architecture, memory sector size is quite flexible and can be as small as two rows of cells. For a typical Flash memory architecture with 512Kbits per sector, one sector can cover 512 rows of cells. Erase gate lines 207 of an entire sector can be tied together to simplify the decoding. On the other hand, erase gate lines 207 could be further decoded to small blocks to reduce the charging and discharging current during switching between program and program verify operations. Since two neighboring rows of cells 114 (which share a row of drain contacts 215) always belong to the same sector, the neighboring erase gate lines 207 can be connected together. Therefore, two neighboring erase gate lines 207 share one metal 2 line and cell layout is not metal 2 pitch-limited. Combining a small cell size with a non-metal-pitch-limited array, the array size is significantly smaller compared with existing memory arrays based on existing source side injection cells and thus, this array 214 is suitable for high density Flash EEPROM applications.

FIG. 3 is a schematic of array 214 in accordance with the array layouts shown in FIG. 2a and FIG. 2b. Table 1 lists array operation conditions in which the CG(i) page 201 (one row worth of cells) is selected during program; the particular cell 114 located at the intersection of the control gate line CG(i) 201 and the bit line BL(i) 208 is selected for read; the erasing sector covers all of the cells 114 shown in the figure and the reverse programming is carried out one row of cells 114 at a time.

Due to a low cell programming current, this array 214 can be programmed in a page mode as well as in a byte mode. During a page program operation, an entire row of cells 114 are programmed simultaneously according to data presented at individual bit lines 208. When a "0" data is to be programmed into a given cell 114, the specific bit line 208 is biased at around 0V and hot electron injection occurs. If the input data is a "1", the specific bit line 208 is biased at V.sub.cc and hot electron injection cannot occur; nor can the electron tunneling because of a 4.5V source bias. Thus, the specific cell 114 remains in the erase state. For a very low V.sub.cc application (i.e. V.sub.cc =2V or lower), a page can be further divided into several sections and a program operation can be carried out one section at a time to reduce the source current and thus, the charge pump size. For such a design, bit lines 208 of those unselected sections are biased at V.sub.cc to prevent any program disturb.

During a sector erase operation, an entire sector of cells 114 is erased simultaneously. Since poly-to-poly tunneling is used for the erase, the DC component of erase current is virtually zero. A bit line bias of V.sub.cc minimizes the erase gate to bit line leakage. With this design, the thickness of erase gate oxide 112 can be thinner and the erase gate channel length can be shorter which improves cell scalability. During erase, bit line charging current can be reduced when the bit line segmentation scheme is implemented.

The other NOR-type memory array 220 implemented with the cell 120 is shown in FIG. 4a. This layout is near a source contact 216. A similar layout around an erase gate contact 219 is shown in FIG. 4b. As seen in FIG. 4a, control gate word lines 201, diffusion source lines 205 and erase gate polysilicon lines 207 run in the horizontal direction and drain bit lines 208 run in the vertical direction. Also shown in FIG. 4a are field oxide 210 and drain bit line contacts 215 while metal lines are not included for clarity of illustration.

In this architecture, both source 105 and erase gate 107 of a cell 120 are respectively connected to sources 105 and erase gates 107 of all other cells 120 of the same sector. Within a sector, metal 1 lines running in the vertical direction are used not only to strap local bit lines 208 but also to connect diffusion source lines 205 and polysilicon erase gate lines 207. Thus, metal 2 lines which also run in the vertical direction, can be set aside for strapping main bit lines (not shown for clarity) to implement bit line segmentation.

FIG. 5 is an array 220 schematic in accordance with the array 220 layouts shown in FIG. 4a and FIG. 4b. Table 2 lists array operation conditions in which cell 120 located at intersection of the control gate line CG(i) 201 and the bit line BL(i) 208 is selected for read, program and reverse program operations. All cells 120 of an entire sector are erased simultaneously (note that all cells 120 in FIG. 5 belong to one sector). Since cell sources 105 of an entire sector are connected together, this array 220 can be programmed only in a byte mode. However, a lower bit line capacitance improves memory access speed and makes this architecture superior for high speed applications. Furthermore, low power consumption for both program and erase operations, which is inherent to the cell 120, makes this architecture suitable for low V.sub.cc, low power and high speed applications.

The fabrication process of the cell 114 is similar to that of a conventional ETOX cell up to the second poly etch step. After etching the second poly, process steps include:

1) forming a dielectric spacer 106 on the sidewall of the second poly with the spacer thickness between 350 .ANG. and 650.ANG. (FIG. 6a);

2) etching the floating gate poly 103 using the oxide cap 601 and the dielectric spacer 106 as hard masks (FIG. 6b; note that the sized-up floating gate 103 is defined by control gate spacer 106);

3) implanting Boron to shift the erase gate threshold voltage to around 1V;

4) stripping the exposed floating gate oxide layer 104 on the silicon surface (FIG. 6b);

5) growing an erase gate oxide 112 with thickness between 50 .ANG. and 250 .ANG. (FIG. 6c);

6) growing a poly tunnel oxide 109 on the sidewall of the floating gate poly during step (5) (FIG. 6c);

7) depositing and etching back erase gate poly (poly 3) to form a polysilicon sidewall spacer 107 with thickness between 0.1 um and 0.3 um (FIG. 6c);

8) forming poly 3 contact pads with a photolithography mask during step (7);

9) stripping poly 3 spacer at the source side of the cell with a photolithography mask;

10) etching the field oxide along the source lines using control gate poly and floating gate poly as hard masks;

11) implanting N.sup.+ Arsenic for peripheral NMOS transistors as well as array cells;

12) stripping poly 3 spacer of peripheral transistors followed by an N.sup.- implant;

13) implanting P.sup.+ Boron for the peripheral PMOS transistors (FIG. 6d).

Since deep N-well and deep source junction are not used, the process complexity of cell 114 is comparable to that of the ETOX cell. By reducing the depth of the source junction, this cell 114 is comparable in size to the ETOX cell.

The fabrication process of cell 120 is similar to that of cell 114 except that erase gate polysilicon is used as a hard mask for etching field oxide 210 along source diffusion lines 205 during step (10). In addition, one additional mask is needed to remove the poly 3 sidewall spacers on the drain side of cell 120 and both drain side and source side of PMOS transistors between step (10) and step (11).

The fabrication processes of cells 121 and 123 are similar to that of cell 114 up to step (4) (see above) when exposed floating gate oxide 104 on the silicon surface is stripped (see FIGS. 7a, 7b). After stripping the floating gate oxide, a select gate oxide 126 and a poly tunnel oxide 109 are grown at the same time. A non-self-aligned select gate 122 is then formed by depositing and etching a third polysilicon layer with a photolithography mask (see FIG. 7c). After select gate 122 formation, the fabrication process can be completed by a standard CMOS lightly doped drain (LDD) process (see FIG. 7d) followed by a backend metal process.

The fabrication process of cell 124 is similar to those of cells 121 and 123 except that a buried N.sup.+ implant is performed to form buried diffusion source region 105 and drain region 108 before growing select gate oxide 126 and poly tunnel oxides 109, 109a simultaneously (see FIG. 1g). A non-self-aligned select gate 125 is then formed by depositing and etching a third polysilicon layer with a photolithography mask. After select gate 125 formation, the fabrication procees can be completed by a standard CMOS lightly doped drain (LDD) process followed by a backend metal process.

It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. For example, either of cells 114, 120, 121, 123 or 124 might be preferred for a given application as will be readily understood by those skilled in the art. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalent be covered thereby.

Table 1 lists operation conditions for the array based on the cell of FIG. 1a; and

Table 2 lists operation conditions for the array based on the cell of FIG. 1c.