US 5,987,744 AGrant
Method for Supporting One or More Electronic Components
Issue Date:1999-11-23
•8 Claims
•10 Drawing Sheets
Abstract
A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes. For example, the support layer can be formed by etching a sheet of conductive material, the compound layers can be formed by placing a conductive paste in via holes in a dielectric layer, and the conductive layers can be formed by lamination followed by etching to form traces.
Metadata
Assignee
- Prolinx Labs Corporation
Inventors
- James J. D. Lan
- Steve S. Chiang
- Paul Y. F. Wu
- John Y. Xie
Application Information
Application Number:US 8883483
Filing Date:1997-07-01
Priority Date:1996-04-10
Art Unit:379
Classifications
IPC:
H01K 310
Field of Search:
29216427830;852;825;83218;2097
Patent Drawings (10 sheets)
Description
Field of the Invention
This invention relates to a method for eliminating a drilling step and optionally a plating step used in fabrication of a substrate for supporting one or more electronic components such as integrated circuit die, and to the substrate resulting therefrom. In particular, this invention relates to a ball grid array structure having a support layer formed of a conductive material, the support layer having holes with isolated conductive islands located in the holes.
Background of the Invention
A semiconductor die (also called an "integrated circuit" chip or IC chip), with electrical circuitry formed therein can be mounted on a "ball grid array" (BGA) substrate using, for example, flip chip (also called "controlled collapse chip connection") structure 111 (FIG. 1A), wire bond structure 112 or tape automated bond (TAB) structure 113 described in "Ball Grid Array Technology", edited by John H. Lau, McGraw-Hill, 1995 that is incorporated by reference herein in its entirety. See also U.S. Pat. Nos. 5,420,460, 5,409,865, 5,397,921, 4,940,181 and 5,216,278.
FIG. 1B discloses a BGA package 120 with an IC chip 128 mounted on BGA substrate 125's first side 121 using wire bond structure 112 (FIG. 1A), and an array (also called "area array") of solder balls 122A-122J (where J is the number of balls) attached to BGA substrate 125's second side 123. BGA substrate 125 has a number of plated vias 125A-125K (where K is the number of vias) that electrically couple IC chip 128 to solder balls 122A-122J. BGA package 120 is typically assembled independent of, and then mounted on a structure, such as a printed circuit board 126.
Lau states at page 38 of his book referenced above "[a]s the PCB technologies push themselves to smaller plated vias, better tolerances, and finer lines and spaces, this next-generation BGA can result in carriers that can theoretically be the same size as the chip in the horizontal dimensions."
Although theoretically possible, many practical difficulties preclude manufacture of such chip sized carriers or packages. For example, the diameter of a plated via in an IC package limits the number of vias that can be formed in a given area, which in turn limits the smallest possible size of an IC package.
Moreover, the cost of fabricating the smallest possible IC package using conventional processes is very high, as compared to the cost of making a larger IC package. Such conventional processes include use of a glass-fiber embedded polymer (such as bismaleimide-triazine ("BT") from Mitsubishi Gas Chemical Corp. Japan) as a core layer. The core layer typically has a thickness of 2 milli-inches to 30 milli-inches. Such a core layer provides structural support to an IC package typically built around the core layer.
Use of such a core layer requires the associated steps of drilling via holes, and plating the drilled via holes. Such drilling and plating steps typically account for the majority of the cost of forming a BGA package or a printed circuit board using conventional processes and materials.
Summary
In accordance with this invention, a structure for supporting one or more electronic components is formed of multiple layers, including a support layer formed of a conductive material, such as a sheet of copper, that is thicker than any other layer in the structure to thereby provide structural support to all other layers in the structure. In one embodiment the support layer is formed from the sheet of conductive material by etching to remove conductive material from predetermined annular regions to thereby simultaneously form islands and one or more portions having annular gaps, hereinafter "isolation gaps," surrounding the islands. The isolation gaps are filled with a dielectric material to form isolation rings that are located between the support layer portions and the islands.
A support layer as described above provides structural support for e.g. a ball grid array package built around the support layer. Conductive islands in the support layer allow circuitry formed on one side of the support layer to be electrically connected to circuitry formed on the other side of the support layer. Such a support layer therefore eliminates the need for a conventional core layer of BT material.
Use of a support layer with conductive islands as described above also eliminates the prior art need for drilling and plating holes to form vias in the support layer. Etching a conductive sheet as described above is cheaper, faster and simpler than conventional drilling. Moreover, etching provides better yield and allows formation of a smaller dimension conductive element than possible by drilling. Furthermore, portions of a support layer can be used as a ground plane or as a power plane, thereby eliminating the need for such additional layers in the structure. A portion of the support layer can also be used as a heat sink for absorbing heat generated by, for example, an integrated circuit die attached to a side of the support layer.
A multilayered structure in accordance with this invention also includes two compound layers formed on two sides of the support layer. Each compound layer includes a layer of dielectric material (hereinafter "dielectric layer") with a number of via holes. Each via hole is formed adjacent to a conductive island such that a conductive element located in the via hole is electrically coupled to the conductive island. The structure also includes two layers of conductive material (hereinafter "conductive layers") formed on the two respective compound layers such that a trace of a first conductive layer is coupled to a trace of a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer.
A multilayered structure in accordance with this invention can be formed by a number of processes described below, either alone or by some combination thereof. In one embodiment, a support layer is formed from a sheet of copper on which is screen printed (or spray coated) a layer of photoimageable dielectric material, followed by imaging and developing the dielectric material to form via holes. The via holes are filled with a conductive paste (e.g. 50% by volume of conductive particles dispersed in 50% by volume of binding material) using a stencil printer. Then a conductive layer is formed on the compound layer, for example by lamination. Next, a number of isolation gaps and islands are simultaneously formed in the support layer by etching. In an optional step, isolation rings can be placed in each isolation gap, for example by screen printing a dielectric material, or by dispensing with a syringe. Then, a dielectric layer is formed on the support layer, followed by formation of via holes and filling the via holes, thereby to form a second compound layer. If the optional step is not used the isolation gaps are filled during formation of the dielectric layer. Next, a second conductive layer is formed on the second compound layer. Then, the two conductive layers are printed and etched to form traces on the two sides. Therefore, a trace on one side of the multilayered structure is electrically coupled to a trace on the other side of the structure through a conductive element, and island and another conductive element.
If during filling of the isolation gaps in the optional step, a portion of the dielectric material protrudes outside of the support layer, the protruding portion can be removed by an optional polishing step, to form a substantially flat surface necessary for further processing.
In other variations of the process described above, conductive elements in the via holes and traces can be formed by plating. For example, in one variation, the via holes and the conductive layers are plated simultaneously, followed by printing and etching of the conductive layers to define traces. In another variation, via holes and predetermined regions of the compound layer are plated to form the conductive elements and traces in the predetermined regions. This second variation eliminates the need for the printing and etching steps used in the first variation.
In another embodiment of the invention, the compound layers are formed simultaneously on two sides of a conductive sheet followed by simultaneous formation of the conductive layers on the two compound layers. The isolation gaps and the conductive islands in the conductive sheet are formed towards the end of the entire process, i.e. after formation of the compound and conductive layers. In this embodiment, at least one of the dielectric layers has a number of annular gaps (hereinafter "access gaps") adjacent to locations of to-be-formed isolation gaps in the support layer. Then via holes in the dielectric layers are filled with a conductive paste (as described above).
Next, two conductive layers are formed on the respective two dielectric layers, for example, by lamination. Then, traces are defined in the two conductive layers. During a trace definition step, the conductive layers' annular areas that cover access gaps in the dielectric layers are also etched to ensure access by an etching solution to the support layer. Then the support layer is etched to form the isolation gaps. Alternatively, as noted above, conductive elements in the via holes and conductive traces can be formed by plating.
As compared to sequential formation, simultaneous formation of compound layers and conductive layers results in a substantially flat structure which reduces the problem of warpage of the structure. Moreover, simultaneous lamination eliminates an additional lamination step otherwise required by a sequential process, and thereby reduces cost. Furthermore, as compared to a sequential process, simultaneous formation steps described above reduce the processing time required to form a structure, thereby increasing throughput and further reducing cost. Finally, simultaneous formation results in a symmetric thermal history on the two sides of a structure, thereby reducing the possibility of delamination due to warpage during operation of the structure.
In yet another embodiment of the invention, a removable substrate, such as a sheet of nickel, is used to form a support layer. Specifically, a dielectric material is screen printed or spray coated on the removable substrate at locations of to-be-formed isolation gaps, to form dielectric isolation rings.
Alternatively, a photoimageable dielectric material can be applied on the removable substrate at locations of to-be-formed isolation gaps by imaging and developing. Then a conductive material is plated on the removable substrate at all regions free of the dielectric material to thereby form a support layer that includes the dielectric rings and the plated material.
Adhesion between the plated material and the isolation rings can be improved by either a curing step after the support layer is formed, or by an adhesion improving step (for example by increasing roughness) before the plating step. Then the removable substrate is removed, e.g. peeled off from the support layer. The support layer is processed by one or more steps described above, for example, by sandwiching between two compound layers followed by formation of two conductive layers. Use of a photoimageable process to form an isolation ring allows the isolation ring to be made substantially smaller than possible in some other embodiments. Moreover, the process of this embodiment eliminates the step of placing the isolation ring into the isolation gaps, and therefore reduces cost, although a plating step is required.
In still another embodiment of the invention, a sheet of conductive material is etched at predetermined locations to form a support layer having a number of through holes. Then a dielectric material is applied, for example by a spray coater, on both sides of the support layer as well as inside the through holes to form dielectric layers on the support layer and reel shaped dielectric elements around the through holes respectively. Thereafter, a number of conductive elements are formed in holes in the dielectric elements, for example by filling with a conductive paste. In this step, conductive paste is also filled in via holes in the dielectric layers. The dielectric elements insulate the conductive elements from the support layer.
Brief Description of the Drawings
FIG. 1A illustrates, in cross-sectional views, three different conventional structures for mounting an integrated circuit chip on a ball grid array substrate.
FIG. 1B illustrates, in a perspective view, a conventional ball grid array package mounted on a printed circuit board.
FIG. 2A illustrates, in a cross-sectional view, a ball grid array package including a multilayered structure for supporting a die in accordance with the invention.
FIG. 2B illustrates, in an enlarged cut-away perspective view a portion of the structure of FIG. 2A in box 2B.
FIGS. 3A-3I illustrate, in cross-sectional views, a process for forming a structure in one embodiment of the invention.
FIG. 3J illustrates a variation of the process illustrated in FIGS. 3A-3I.
FIGS. 4A-4D illustrate, in cross-sectional views, another process for forming a structure in accordance with the invention.
FIGS. 5A-5D illustrate, in cross-sectional views, yet another process for forming a structure in accordance with the invention.
FIGs. 6A-6C illustrate, in cross-sectional views, still another process for forming a structure in accordance with the invention.
FIGS. 7A-7D illustrate, in cross-sectional views, still another process for forming a structure in accordance with the invention.
FIGS. 8A-8B illustrate in a cross-sectional view and an enlarged view, respectively, similar to FIGS. 2A-2B, a die attached by conductive balls to the multilayered structure.
Detailed Description
In accordance with this invention, a multilayered structure for supporting one or more electronic components includes a support layer formed of a conductive material, such as a sheet of copper, that is thicker than any other layer in the structure. The support layer has a number of conductive islands separated from other portions of the support layer by isolation gaps that are annular in shape. A ring of dielectric material (also called "isolation ring") is located in each of the isolation gaps. Other layers of the multilayered structure are formed around and supported by the support layer.
In one specific embodiment, an integrated circuit package 200 (FIG. 2A) includes a structure 201 on which is mounted an integrated circuit die (also called "IC die") 202. Specifically, IC die 202 is attached to structure 201 by a die attach adhesive 203, and a number of bond wires 204A-204N (where N is the number of bond wires) electrically couple pads 202A-202N (FIG. 2B) to contacts 201A-201N of structure 201. For clarity, not all parts, e.g. pads 202A-202N, bond wires 204A-204N and contacts 201A-201N are shown in FIGS. 2A-2B.
Structure 201 also includes a number of conductive balls (also called "substrate balls") 205A-205M (where M is the number of substrate balls, and in one variation M=N) formed on a side 206 that is opposite to the side 207 on which is mounted IC die 202. IC package 200 also includes an encapsulant 208 formed on side 207 of structure 201, to thereby enclose IC die 202, bond wires 204A-204N and contacts 201A-201N.
Structure 201 is a multilayered structure that includes support layer 210 formed of a conductive material, such as a sheet of copper. Support layer 210 is sandwiched between dielectric layers 220 and 230 which in turn are sandwiched between conductive layers 240 and 250. Support layer 210 has a number of annular isolation gaps 211A, 211B . . . and a corresponding number of conductive islands 212A, 212B . . . surrounded by isolation gaps 211A-P, 211B . . . Conductive islands 212A, 212B . . . have a dimension Die.(e.g. larger diameter of a conical frustrum) smaller than the smallest diameter Dhi of the wall of portion 215 of support layer 210 such that isolation rings 213A, 213B . . . are formed between islands 212A, 212B . . . and portion 215 when a dielectric material is placed in isolation gaps 211A, 211B . . .
In this particular variation of the embodiment, support layer 210 also includes another portion 216 on which is mounted IC die 202, and portion 216 is coupled to a source (not shown) of ground reference voltage, to thereby allow portion 216 to function as a ground reference plane. Moreover, portion 216 functions as a heat sink to absorb the heat generated by IC die 202. Portion 216 passes the heat to conductive elements, e.g. element 232I, that then pass the heat to the substrate balls, e.g. ball 205I. Also in this particular variation, portions 215 and 216 of support layer 210 are separated from each other by a channel 217, thereby to allow portion 215 to be used as, for example, a power reference plane.
As noted above, support layer 210 is sandwiched between compound layers 220 and 230 that are formed on the two sides 219A and 219B respectively of support layer 210. Each of compound layers 220 and 230 includes respectively dielectric layers 221 and 231 in which are formed a number of via holes 221A, 221B . . . and via holes 231A, 231B . . . 231I. Compound layers 220 and 230 also include a number of conductive elements 222A, 222B . . . and 232A, 232B . . . 232I located in the respective via holes 221A, 221B . . . and 231A, 231B . . . 231I.
Structure 201 also includes conductive layers 240 and 250 that are formed on compound layers 220 and 230 and etched to form contacts 201A, 201B . . . and 251A-251I respectively. Contacts 201A, 201B . . . are suitable for coupling to pads 202A, 202B of IC die 202, while contacts 251A-251I are suitable for coupling to substrate balls 205A-205I. During etching of conductive layers 240 and 250, traces, e.g. traces 241A, 241B, are also formed on compound layers 220 and 230. Structure 201 also includes protective layers formed of, for example, a solder mask material, such as layer 260 on portions of conductive layer 250 and compound layer 230, to thereby protect structure 201.
Each of isolation gaps 211A, 211B . . . has a height equal to thickness Ts of support layer 210, thereby to physically isolate each of islands 212A-212N from portion 215 of layer 210. In this particular embodiment, each isolation gap has an inner diameter Dhi of, e.g. 14 milli-inches, that is smaller than an outer diameter Dho of e.g. 16 milli-inches. Moreover, in this particular variation of the embodiment, during the etching step, an optional channel 217 of a height equal to sheet thickness Ts is also formed, thereby to isolate portion 215 from another portion 216 of layer 210.
In one embodiment (FIG. 2B) support layer 210 is thicker than any other layer in multilayered structure 201 and thereby provides structural support to all other layers built around support layer 210. For example, support layer 210 has a thickness Ts=5 milli-inches, while all other layers 220, 230 and 260 have a thickness around 2 milli-inches. Use of etching as described below to form support layer 210 eliminates the need for drilling holes and the associated costs and time needed to form a prior art IC package using a BT core layer.
Structure 201 described above in reference to FIGS. 2A-2B can be formed by a number of processes. For example, in one specific embodiment, a support layer is formed from a sheet 311 of conductive material, e.g. copper. Sheet 311 has a thickness Ts in the range of, for example, 3-20 milli-inches, preferably 5 milli-inches. Sheet 311 can be of a large size sufficient to form a large number of IC package substrates simultaneously, which ball grid array substrates are obtained by dividing, e.g. by etching or routing at the end of the process (prior to mounting IC die). For example, a sheet 311 of area 18 inches by 24 inches can be processed as described below in reference to FIGS. 3A-3H, and then routed into 150substrates, each of an appropriate area, e.g. 1.3 inches by 1.3 inches, prior to mounting of IC die to form the package illustrated in FIG. 3I. Many of the reference numerals in FIGS. 3A-3I, 4A-4D, 5A-5D, 6A-6D, 7A-7D and 8A-8B are derived by adding 100, 200, . . . 600 to reference numerals in FIGS. 2A-2B that identify similar features.
In this embodiment, a compound layer 330 is formed on a side 319B of sheet 311 (FIG. 3A) followed by formation of a conductive layer 350 on compound layer 330 (FIG. 3B). Specifically, an adhesive layer (such as an oxide layer not shown) can be formed on side 319B of conductive sheet 311 followed by formation of a layer 331 of dielectric material for example by screen printing. In addition to or instead of an adhesive layer, a rough surface can be formed by e.g. etching or grinding, to improve adhesion of the applied dielectric material. The dielectric material used to form dielectric layer 331 in two alternative variations of this embodiment is nonphotoimageable or photoimageable. If a nonphotoimageable dielectric material is used to form dielectric layer 331, a number of via holes, e.g. via holes 331A-331M, are formed in dielectric layer 331 during the screen printing step. Alternatively, if a photoimageable dielectric material is used, the photoimageable dielectric material can be screen printed or spray coated followed by imaging and developing the dielectric material to form via holes 331A-331M.
Next, conductive elements 332A-332M can be formed by filling via holes 331A-331M with a material, such as a conductive paste of the type described briefly below and in detail in U.S. patent application Ser. No. 08/538,886, filed Oct. 4, 1995, that was incorporated by reference above. A conductive paste contains a binding material that is heavily loaded with conductive particles, for example, particles 333A-333S (FIG. 3C) in binding material 334 such that each of particles 333A-333S is in physical contact with one or more of particles 333A-333S so as to form a conductive element 332A through binding material 334.
Thereafter, a conductive layer 350 (FIG. 3D) is formed on compound layer 330, for example by lamination. Next, sheet 311 is etched to form a number of islands 312A, 312B . . . by printing and etching annular regions 313A, 313B . . . surrounding the to-be-formed islands 312A, 312B . . . thereby to form isolation gaps 311A, 311B . . . In this particular embodiment, islands 312A, 312B . . . each have a smaller diameter D is (FIG. 3E) of, e.g. 4 milli-inches, and a larger diameter Dil of e.g. 6 milli-inches, due to isotropic etching.
Next, in an optional step, a dielectric material is filled in various isolation gaps, e.g. isolation gap 311A (FIG. 3F) to form an isolation ring 313A surrounding island 312A. If a portion 391A (FIG. 3f) of the dielectric material protrudes outside of side 319A, the protruding portion can be polished off in another optional step.
Then, compound layer 320 (FIG. 3G) is formed in a manner similar to that described above for compound layer 330. The dielectric material of dielectric layer 321 included in compound layer 320 is removed from a region 326 over portion 316, thereby to expose a surface 316A of portion 316 (FIG. 3H). Moreover, a conductive layer 340 is formed. Conductive layers 340 and 350 are etched to form a group of traces 341A, 341B . . . and a second group of traces 351A, 351B . . . Traces 341A, 341B . . . are coupled to the respective conductive elements 322A, 322B . . . Similarly, conductive traces 351A-351I are coupled to conductive elements 332A-332I. Islands 312A, 312B . . . are in contact with conductive elements 322A, 322B . . . and 332A, 332B . . . Therefore, traces 341A, 341B . . . are coupled to traces 351A, 351B. Moreover, portions of support layer 310, such as portions 315 and 316 are in contact with certain of the conductive elements, e.g. portion 316 contacts conductive element 332I (FIG. 3G). Then, a solder mask material is applied to form layers 360 and 370 (FIG. 3H) on dielectric layers 320 and 330 and conductive layers 340 and 350. A contact coating, e.g. of nickel and gold Ni/Au can be applied to copper contacts 301A-301N prior to formation of layers 360 and 370 if necessary. Finally, structure 310 is routed, scored, punched or etched, followed by attachment of an IC die, wire bonding, molding (with encapsulant 308) and attachment of solder balls to complete formation of an integrated circuit package 390 (FIG. 3I). As noted above, a portion 316 can be used as a reference plane for, for example, a ground reference voltage. Similarly, portion 315 can be used as a reference plane for, for example, a power reference voltage signal. Alternatively, portions 315 and 316 can be electrically coupled to each other to form a single reference plane.
Although in one variation of the embodiment, conductive layers 340 and 350 are formed by lamination, in another variation of the embodiment, conductive layers 340 and 350 are formed by plating. In the latter variation, instead of filling via holes 331A, 331B . . . with a conductive paste, the conductive material used in the plating step is also plated into via holes 331A, 331B . . . in a manner well known in the art, as described in U.S. Pat. No. 5,097,593. In a variation of the process described above in reference to FIGS. 3A-3H, a second compound layer 320 and a second conductive layer 340 (FIGS. 3G and 3H) are not formed. Instead, bond wires, e.g. wire 304A, are directly attached to conductive islands, e.g. island 312B, as illustrated in FIG. 3J, after application of a Ni/Au layer on island 312B. In this particular variation, islands are formed approximately as solid cylinders, e.g. by jet etching.
Although in one embodiment, layers 330, 350, 320 and 340 are formed sequentially as described above in reference to FIGS. 3A-3H, such layers can be formed simultaneously. In another embodiment of the invention, compound layers 420 and 430 (FIG. 4A) are formed simultaneously on the two sides 419A and 419B, respectively, of sheet 411. Specifically, dielectric layers 421 and 431 are formed on the respective sides 419A and 419B simultaneously, for example, by use of a photoimageable dielectric material. Then, via holes 421A, 421B . . . and 431A, 431B . . . are formed in the respective dielectric layers 420 and 430, by imaging and developing. During the imaging and developing steps, a number of annular openings 471A, 471B . . . are formed in dielectric layer 430 at locations adjacent to the to-be-formed isolation gaps in sheet 411. Via holes 421A, 421B . . . and 431A, 431B . . . in respective dielectric layers 421 and 431 are filled with a conductive paste (described above) to form conductive elements 422A, 422B . . . and 432A, . . . respectively.
Then, two conductive layers 440 and 450 (FIG. 4B) are formed on compound layers 420 and 430 respectively, for example, by lamination. Then, traces 441A, 441B . . . and 451A, 451B . . . are defined in conductive layers 440 and 450, for example, by etching. During this step, conductive layers 440 and 450 are also etched in annular areas 472A, 472B . . . that cover annular openings 471A, 471B . . . thereby to expose annular openings 471A, 471B . . . . If thickness Ts (FIG. 4B) of sheet 411 is sufficiently small (for example, Ts=3 milli-inches which is larger than thickness Tc=2 milli-inches of conductive layers 440 and 450), isolation gaps 411A, 411B . . . (FIG. 4C) can be formed (e.g. by etching) during the trace definition step. If such a process is used, traces 441A, 441B . . . and 451A, 451B . . . are protected with a coating, e.g. Ni/Au or Sn or solder prior to etching to form isolation gaps 411A, 411B . . .
In the example described above, thickness Td of compound layers 421 and 431 is about 2 milli-inches, which is also smaller than thickness Ts of support layer 410.
In another variation of the embodiment, conductive layers 440 and 450 are protected, for example, by application of a resist material (not shown) after formation of traces 441A, 441B . . . and 451A, 451B . . ., and then sheet 411 is etched through annular gaps 471A, 471B . . . to thereby form isolation gaps 411A, 411B . . . . Then, solder mask layers 460 and 480 are formed on a compound layer 420 and conductive layer 440 on one side and on compound layer 430 and conductive layer 450 on the other side, thereby to form structure 401 (FIG. 4D). Then, conductive balls 405A, 405B . . . (e.g. formed of solder) and a die (not shown) are attached to structure 401, followed by wire bonding (or flip chip die attach step) and encapsulation to complete formation of a ball grid array package.
In another embodiment, instead of using microfilled via material as described above in reference to FIGS. 3A-3I and 4A-4D, conductive elements are formed by plating of via holes in a dielectric layer, as described below in reference to FIGS. 5A-5D. Specifically, a dielectric material is used to form a dielectric layer 531 on side 519A of sheet 511 (FIG. 5A). Dielectric layer 531 has a number of via holes 531A-531I, that are formed by imaging and developing a photoimageable material used to form layer 531. Each of via holes 531A-531I has a diameter Dv of, for example, 6 milli-inches which is larger than twice the thickness Tc (e.g. 2 milli-inches) of a conductive layer 550 to be formed next. Next, conductive layer 550 is formed on dielectric layer 531, for example, by plating. During formation of conductive layer 550, via holes 531A-531I of dielectric layer 531 are plated such that a number of conductive elements 532A-532I are formed in via holes 531A-531I. Conductive elements 532A-532I are formed in contact with the side 519B of sheet 511.
Next, sheet 511 is etched on side 519A, in annular regions 572A-572I, thereby to form isolation gaps 511A-511I (FIG. 5B) surrounding islands 512A-512I, in a manner similar to that described above for FIG. 3D. Then, a dielectric layer 521 (FIG. 5C) is formed on side 519A on support layer 510. During formation of dielectric layer 521, isolation gaps 511A-511I can be filled to form isolation rings 513A-5131 around respective conductive islands 512A-512I. A number of via holes 521A-521I are formed in dielectric layer 521, for example, by stencil printing, or alternatively by imaging and developing a photoimageable dielectric material used to form layer 521. Then, a conductive layer 540 is formed on dielectric layer 521, such that via holes 521A-521I are plated, to form conductive elements 522A-522I. Although conductive elements 522A-522I and 532A-532I are illustrated in FIGS. 5A-5D as having a cup shape, such conductive elements can have other shapes (e.g. solid cylinder).
Then, conductive layers 540 and 550 are etched to form traces 541A, 541B . . . and 551A, 551B Thereafter, protective layers 560 and 580 are formed, for example, by applying a solder mask material to thereby complete formation of structure 501. After die attach, wire bonding and molding (not shown in FIGS. 5A-5D), solder balls 505A-505I are formed on the respective traces of structure 501, to complete formation of a ball grid array package.
In another embodiment of the invention, a removable substrate 690 (FIG. 6A) such as a sheet of nickel is used to form a support layer of the invention. Specifically, a dielectric material is screen printed (or spray coated) on a first side 690A of removable substrate 690 at predetermined locations, thereby to form annular isolation rings, e.g. rings 613A, 613B . . . Alternatively, a photoimageable dielectric material can be applied all over removable substrate 690. After imaging and developing, dielectric material remains as isolation rings 613A, 613B . . . at the predetermined locations. Thereafter, a conductive material is plated on removable substrate 690 at all regions that are free of dielectric material, i.e. at all regions other than isolation rings 613A, 613B . . . (e.g. portion 615 and islands 612A, 612B), to thereby form support layer 610 (FIG. 6B). Thereafter, removable substrate 690 is removed, e.g. peeled off (FIG. 6C). Thereafter, two compound layers are formed on the two sides 610A and 610B, and a conductive layer is formed on each of the compound layers in a manner similar to the steps discussed above, for example in reference to FIGS. 3A-3D.
Adhesion between plated material 611 and isolation rings 613A, 613B . . . can be improved by either a curing step after support layer 610 is formed, or by an adhesion improving step, for example by increasing roughness of isolation rings 613A, 613B . . . before the plating step.
In yet another embodiment of the invention, a sheet 711 (FIG. 7A) of conductive material is etched at predetermined locations 701A and 701B to form through holes 711A and 711B (FIG. 7B). Through holes 711A and 711B each have a diameter Dt1 that is at least a multiple of thickness Ts of sheet 711. For example, in one variation of the embodiment, Dt1 is 8 mils, while Ts is 2 mils.
Then, a dielectric material is applied, for example by a spray coater, on the surfaces of holes 711A and 711B as well as on the sides 719A and 719B of sheet 711. Such application of dielectric material forms dielectric layers 720, 730 (FIG. 7C) and a number of reel shaped dielectric elements 791A, 791B . . . around holes 711A, 711B . . . Each of dielectric layers 720 and 730 has a thickness Td that is smaller than diameter Dt1 such that even after application of the dielectric material, through holes 790A, 790B . . . remain in dielectric elements 791A, 791B . . . Through holes 790A, 790B . . . have a diameter Dt2 of, for example, 4 milliinches. Dielectric layers 720 and 730 also have a number of via holes 720A-720I and 730A-730I that are formed, for example by imaging and developing or, alternatively, during a screen printing step.
Thereafter, a number of conductive elements are formed in through holes 790A, 790B . . . , for example by filling with a conductive paste to form solid cylindrical conductive elements 712A, 712B . . . (FIG. 7D). Moreover, via holes 720A-720I and 730A-730I are also filled with the conductive paste to form e.g. thermal vias. Finally, conductive layers 740 and 750 are formed on the compound layers 720 and 730 followed by etching to form traces, e.g. traces 741A, 741B, 751A and 751B. In this particular embodiment, the conductive elements, e.g. elements 712A and 712B, are insulated from portions of sheet 711 by reel shaped dielectric elements 791A, 791B . . .
Numerous modifications and adaptations of the embodiments described above would be obvious in view of the enclosed disclosure. For example, although formation of only two compound layers and only two conductive layers has been described above, any number of compound layers and conductive layers can be formed around a conductive support layer in accordance with the invention.
Although die 202 (FIGS. 2A, 2B) is illustrated as being coupled to multilayered structure 201 by bond wires 204A-204N, in another embodiment, die 802 (FIGS. 8A, 8B) is attached to multilayer substrate 801 by a number of conductive balls (also called die attach balls) 804A, 804B . . . 804N. Specifically, a number of pads 802A-802N of die 802 are coupled by the respective die attach balls 804A-804N to contacts 801A-801N of multilayered structure 801. Multilayered structure 801 has a number of traces of the type similar to traces 241A and 241B (FIG. 2B) and also has other parts similar to those discussed above in reference to structure 201.
Moreover, although a structure of three conductive layers has been described above, two such structures can be laminated to each other to form a structure of six conductive layers. For example, in FIGS. 3G and 3H, after conductive layer 340 is formed and etched instead of a protective layer 370 being formed, a third compound layer (not shown) can be formed. Then two such structures can be laminated, with the third compound layers of the two structures facing each other, to form a single six layered structure.
Accordingly, various modifications and adaptations of the above described embodiments are encompassed in the appended claims.
Claims
We claim:
1. A method of forming a structure for supporting one or more electronic components, said method of comprising: forming a first compound layer on a sheet of conductive material, said first compound layer comprising a first dielectric layer with a first via hole at a predetermined location, said first compound layer further comprising a first conductive element located in said first via hole; forming a first conductive layer on said first compound layer; etching said sheet to form a support layer comprising a conductive island and a conductive portion, wherein said conductive island is located at said predetermined location and further wherein said conductive portion is separated from said conductive island by an isolation gap; etching said first conductive layer to form a plurality of first traces a predetermined first trace being electrically coupled to said conductive island by said first conductive element; and forming a second compound layer on said second side of said support layer; forming a second conductive layer on said second compound layer; and etching said second conductive layer to form a plurality of second traces such that a predetermined second trace is electrically coupled to said predetermined first trace through said conductive island.
2. The method of claim 1 further comprising forming a plurality of annular gaps in said first dielectric layer during formation of said first compound layer.
3. The method of claim 2 wherein said sheet is etched after etching of said first conductive layer and said second conductive layer.
4. A method of forming a structure for supporting one or more electronic components, said method of comprising: forming a first compound layer on a sheet of conductive material, said first compound layer comprising a first dielectric layer with a first via hole at a predetermined location, said first compound layer further comprising a first conductive element located in said first via hole; forming a first conductive layer on said first compound layer; etching said sheet to form a support layer comprising a conductive island and a conductive portion, wherein said conductive island is located at said predetermined location and further wherein said conductive portion is separated from said conductive island by an isolation gap; etching said first conductive layer to form a plurality of first traces, a predetermined first trace being electrically coupled to said conductive island by said first conductive element; and applying an adhesive layer on said sheet prior to forming said compound layer.
5. A method of forming a structure for supporting one or more electronic components, said method comprising: forming two compound layers simultaneously on two sides of a sheet of conductive material, each of said compound layers comprising a dielectric layer with a plurality of via holes at predetermined locations, one of said dielectric layers having a plurality of gaps, with each gap exposing a portion of said sheet; placing a conductive paste in each of said via holes; forming a conductive layer on each of said compound layers; etching said conductive layers simultaneously to form traces and to expose gaps in said compound layers; etching said sheet through said gaps to form a number of isolation gaps in said sheet; and filling in said isolation gaps with a dielectric material to form isolation rings.
6. The method of claim 5 wherein during said step of filling, protective layers are formed on said compound layers and said conductive layers.
7. The method of claim 5 wherein said gaps are annular in shape.
8. A method of forming a structure for supporting one or more electronic components, said method comprising: etching a plurality of through holes in a sheet of conductive material; applying a dielectric material to exposed surfaces of the through holes in said sheet and applying said dielectric material to both sides of said sheet: forming via holes in each of said dielectric layers at predetermined locations; forming a conductive element in each of said through holes and in each of said via holes, wherein said forming a conductive element comprises filling said through holes with conductive paste; forming conductive layers on each of the dielectric layers; and etching the conductive layers to form traces.
Patent Citations (191)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3335327 | 1967-08-01 | Damon et al. | |
| US3384879 | 1968-05-01 | Stahl et al. | |
| US3615913 | 1971-10-01 | Shaw | |
| US3808576 | 1974-04-01 | Castonguay et al. | |
| US3857683 | 1974-12-01 | Castonguay | |
| US3923359 | 1975-12-01 | Newsam | |
| US4024629 | 1977-05-01 | Lemoine et al. | |
| US4090667 | 1978-05-01 | Crimmins | |
| US4146863 | 1979-03-01 | Mollenhoff | |
| US4238839 | 1980-12-01 | Redfern et al. | |
| US4245273 | 1981-01-01 | Feinberg et al. | |
| US4247981 | 1981-02-01 | Walters | |
| US4386051 | 1983-05-01 | Edgington | |
| US4399372 | 1983-08-01 | Tanimoto et al. | |
| US4413272 | 1983-11-01 | Mochizuki et al. | |
| US4420820 | 1983-12-01 | Preedy | |
| US4424578 | 1984-01-01 | Miyamoto | |
| US4433331 | 1984-02-01 | Kollaritsch | |
| US4434134 | 1984-02-01 | Darrow et al. | |
| US4455495 | 1984-06-01 | Masuhara et al. | |
| US4458297 | 1984-07-01 | Stopper et al. | |
| US4488262 | 1984-12-01 | Basire et al. | |
| US4491860 | 1985-01-01 | Lim | |
| US4507756 | 1985-03-01 | McElroy | |
| US4507757 | 1985-03-01 | McElroy | |
| US4547830 | 1985-10-01 | Yamauchi | |
| US4562639 | 1986-01-01 | McElroy | |
| US4565712 | 1986-01-01 | Noguchi et al. | |
| US4566186 | 1986-01-01 | Bauer et al. | |
| US4569120 | 1986-02-01 | Stacy et al. | |
| US4569121 | 1986-02-01 | Lim et al. | |
| US4585490 | 1986-04-01 | Raffel et al. | |
| US4590589 | 1986-05-01 | Gerzberg | |
| US4609241 | 1986-09-01 | Peterson | |
| US4642160 | 1987-02-01 | Burgess | |
| US4651409 | 1987-03-01 | Ellsworth et al. | |
| US4652974 | 1987-03-01 | Ryan | |
| US4678889 | 1987-07-01 | Yamanaka | |
| US4689411 | 1987-08-01 | Dick et al. | |
| US4700116 | 1987-10-01 | Inoue et al. | |
| US4700214 | 1987-10-01 | Johnson | |
| US4710592 | 1987-12-01 | Kimbara | |
| US4721868 | 1988-01-01 | Cornell et al. | |
| US4726991 | 1988-02-01 | Hyatt et al. | |
| US4731704 | 1988-03-01 | Lochner | |
| US4732780 | 1988-03-01 | Mitoff et al. | |
| US4748490 | 1988-05-01 | Hollingsworth | |
| US4757359 | 1988-07-01 | Chiao et al. | |
| US4780670 | 1988-10-01 | Cherry | |
| US4786904 | 1988-11-01 | Graham, III et al. | |
| US4789760 | 1988-12-01 | Koyama et al. | |
| US4791075 | 1988-12-01 | Lin | |
| US4792646 | 1988-12-01 | Enomoto | |
| US4792835 | 1988-12-01 | Sacarisen et al. | |
| US4796074 | 1989-01-01 | Roesner | |
| US4796075 | 1989-01-01 | Whitten | |
| US4799128 | 1989-01-01 | Chen | |
| US4799984 | 1989-01-01 | Rellick | |
| US4803595 | 1989-02-01 | Kraus et al. | |
| US4808967 | 1989-02-01 | Rice et al. | |
| US4821142 | 1989-04-01 | Ushifusa et al. | |
| US4823181 | 1989-04-01 | Mohsen et al. | |
| US4829404 | 1989-05-01 | Jensen | |
| US4839864 | 1989-06-01 | Fujishima | |
| US4840924 | 1989-06-01 | Kinbara | |
| US4841099 | 1989-06-01 | Epstein et al. | |
| US4845315 | 1989-07-01 | Stopper | |
| US4847732 | 1989-07-01 | Stopper et al. | |
| US4864165 | 1989-09-01 | Hoberman et al. | |
| US4873506 | 1989-10-01 | Gurevich | |
| US4874711 | 1989-10-01 | Hughes et al. | |
| US4876220 | 1989-10-01 | Mohsen et al. | |
| US4881114 | 1989-11-01 | Mohsen et al. | |
| US4882611 | 1989-11-01 | Blech et al. | |
| US4888574 | 1989-12-01 | Rice et al. | |
| US4888665 | 1989-12-01 | Smith | |
| US4892776 | 1990-01-01 | Rice | |
| US4893167 | 1990-01-01 | Boudou et al. | |
| US4897836 | 1990-01-01 | Fitzpatrick et al. | |
| US4899205 | 1990-02-01 | Hamdy et al. | |
| US4910418 | 1990-03-01 | Graham et al. | |
| US4910584 | 1990-03-01 | Mizuo | |
| US4914055 | 1990-04-01 | Gordon et al. | |
| US4915983 | 1990-04-01 | Lake et al. | |
| US4916809 | 1990-04-01 | Boudou et al. | |
| US4920454 | 1990-04-01 | Stopper et al. | |
| US4924287 | 1990-05-01 | Orbach | |
| US4933738 | 1990-06-01 | Orbach et al. | |
| US4935584 | 1990-06-01 | Boggs | |
| US4937475 | 1990-06-01 | Rhodes et al. | |
| US4940181 | 1990-07-01 | Juskey, Jr. et al. | |
| US4943538 | 1990-07-01 | Mohsen et al. | |
| US4949084 | 1990-08-01 | Schwartz et al. | |
| US4964948 | 1990-10-01 | Reed | |
| US4969124 | 1990-11-01 | Luich et al. | |
| US4970579 | 1990-11-01 | Ardt et al. | |
| US4974048 | 1990-11-01 | Chakravorty et al. | |
| US4977357 | 1990-12-01 | Shrier | |
| US4992333 | 1991-02-01 | Hyatt | |
| US5003486 | 1991-03-01 | Hendel et al. | |
| US5014002 | 1991-05-01 | Wiscombe et al. | |
| US5027191 | 1991-06-01 | Bourdelaise et al. | |
| US5030113 | 1991-07-01 | Wilson | |
| US5055321 | 1991-10-01 | Enomoto et al. | |
| US5055973 | 1991-10-01 | Mohsen | |
| US5060116 | 1991-10-01 | Grobman et al. | |
| US5068634 | 1991-11-01 | Shrier | |
| US5077451 | 1991-12-01 | Mohsen | |
| US5087589 | 1992-02-01 | Chapman et al. | |
| US5092032 | 1992-03-01 | Murakami | |
| US5097593 | 1992-03-01 | Jones et al. | |
| US5099149 | 1992-03-01 | Smith | |
| US5099380 | 1992-03-01 | Childers et al. | |
| US5106773 | 1992-04-01 | Chen et al. | |
| US5108541 | 1992-04-01 | Schneider et al. | |
| US5120679 | 1992-06-01 | Boardman et al. | |
| US5136366 | 1992-08-01 | Worp et al. | |
| US5142263 | 1992-08-01 | Childers et al. | |
| US5144567 | 1992-09-01 | Oelsch et al. | |
| US5148265 | 1992-09-01 | Khandros et al. | |
| US5148355 | 1992-09-01 | Lowe et al. | |
| US5155577 | 1992-10-01 | Chance et al. | |
| US5159535 | 1992-10-01 | Desai et al. | |
| US5166556 | 1992-11-01 | Hsu et al. | |
| US5170931 | 1992-12-01 | Desai et al. | |
| US5181096 | 1993-01-01 | Forouhi | |
| US5181859 | 1993-01-01 | Foreman et al. | |
| US5189387 | 1993-02-01 | Childers et al. | |
| US5191511 | 1993-03-01 | Sawaya | |
| US5196724 | 1993-03-01 | Gordon et al. | |
| US5200652 | 1993-04-01 | Lee | |
| US5203075 | 1993-04-01 | Angulas et al. | |
| US5210940 | 1993-05-01 | Kawakami et al. | |
| US5216278 | 1993-06-01 | Lin et al. | |
| US5218679 | 1993-06-01 | Hasegawa et al. | |
| US5220490 | 1993-06-01 | Weigler et al. | |
| US5229549 | 1993-07-01 | Yamakawa et al. | |
| US5231751 | 1993-08-01 | Sachdev et al. | |
| US5233217 | 1993-08-01 | Dixit et al. | |
| US5248517 | 1993-09-01 | Shrier et al. | |
| US5250228 | 1993-10-01 | Baigrie et al. | |
| US5250470 | 1993-10-01 | Yamaguchi | |
| US5258643 | 1993-11-01 | Cohen | |
| US5260519 | 1993-11-01 | Knickerbocker et al. | |
| US5260848 | 1993-11-01 | Childers | |
| US5262352 | 1993-11-01 | Woo et al. | |
| US5262754 | 1993-11-01 | Collins | |
| US5264729 | 1993-11-01 | Rostoker et al. | |
| US5282271 | 1994-01-01 | Hsieh et al. | |
| US5282312 | 1994-02-01 | DiStefano et al. | |
| US5287620 | 1994-02-01 | Suzuki et al. | |
| US5291062 | 1994-03-01 | Higgins, III | |
| US5294750 | 1994-03-01 | Sakai et al. | |
| US5300208 | 1994-04-01 | Angelopoulos et al. | |
| US5311053 | 1994-05-01 | Law et al. | |
| US5317801 | 1994-06-01 | Tanaka et al. | |
| US5319238 | 1994-06-01 | Gordon et al. | |
| US5321322 | 1994-06-01 | Verheyen et al. | |
| US5329153 | 1994-07-01 | Dixit | |
| US5345106 | 1994-09-01 | Doering et al. | |
| US5347258 | 1994-09-01 | Howard et al. | |
| US5349248 | 1994-09-01 | Parlour et al. | |
| US5362676 | 1994-11-01 | Gordon et al. | |
| US5367764 | 1994-11-01 | DiStefano et al. | |
| US5377124 | 1994-12-01 | Mohsen | |
| US5397921 | 1995-03-01 | Karnezos | |
| US5404637 | 1995-04-01 | Kawakami | |
| US5408130 | 1995-04-01 | Woo et al. | |
| US5409865 | 1995-04-01 | Karnezos | |
| US5410806 | 1995-05-01 | Schneider | |
| US5420456 | 1995-05-01 | Galbi et al. | |
| US5420460 | 1995-05-01 | Massingill | |
| US5421083 | 1995-06-01 | Suppelsa et al. | |
| US5435480 | 1995-07-01 | Hart et al. | |
| US5436412 | 1995-07-01 | Ahmad et al. | |
| US5438166 | 1995-08-01 | Carey et al. | |
| US5464790 | 1995-11-01 | Hawley | |
| US5468995 | 1995-11-01 | Higgins, III | |
| US5481795 | 1996-01-01 | Hatakeyama et al. | |
| US5487218 | 1996-01-01 | Bhatt et al. | |
| US5502889 | 1996-04-01 | Casson et al. | |
| US5537108 | 1996-07-01 | Nathan et al. | |
| US5572409 | 1996-11-01 | Nathan et al. | |
| US5574311 | 1996-11-01 | Matsuda | |
| US5583376 | 1996-12-01 | Sickler et al. | |
| US5583378 | 1996-12-01 | Marrs et al. | |
| US5612574 | 1997-03-01 | Summerfelt et al. | |
| EPX336359 | 1989-10-01 | ||
| EPX510900A2 | 1992-10-01 | ||
| JPX59-13368 | 1984-01-01 | ||
| JPX61-287152 | 1986-12-01 |
Non-Patent Literature (36)
- Hwang, Jennie S., "Solder Paste in Electronics Packaging Technology and Applications in Surface Mount, Hybrid Circuits, and Component Assembly", Van Nostrand Reinhold, 1992, pp. xv-xx and 59-62.
- "Polyswitch Resettable Fuses for Circuit Protection Information Package", Raychem Corporation, Electronics Division, Nov. 9, 1992.
- G.R. Ruschau et al., "Critical Volume Fractions in Conductive Composites", Journal of Composite Materials, vol. 26, No. 18/1992, pp. 2727-2735.
- S. Chiang, et al., "Conductive Channel in ONO Formed by Controlled Dielectric Breakdown", 1992 Symposium on VLSI Technology Digest of Technical Papers, pp. 20-21.
- S. Chiang, et al., "Antifuse Structure Comparison for Field Programmable Gate Arrays", IEDM, 1992, pp. 611-614.
- K. Gordon, et al., "Conducting Filament of the Programmed Metal Electrode Amorphous Silicon Antifuse", IEDM, 1993, pp. 27-30.
- C. Hu, "Interconnect Devices for Field Programmable Gate Array", IEDM, 1992, pp. 591-594.
- "Matsushita Team Eliminates Holes in High-Density PCB", Tsuda, Nikkei Electronics Asia, Mar. 1995 pp. 69-70.
- "Printed Circuit Board Design Guidelines For Ball Grid Array Packages", Johnston, Motorola, Inc., pp. 255-260.
- "An Enhanced Performance Low Cost BGA Package", Marrs, etc., Amkor Electronics, Inc., pp. 214-225.
- "A Large Format Modified TEA CO.sub.2 Laser Based Process For Cost Effective Small Via Generation", J.M. Morrison etc., MCM 1994 Proceedings, pp. 369-377.
- "The Application of Laser Process Technology to Thin Film Packaging", T.F. Redmond etc., IEEE, 1992, pp. 1066-1071.
- "A New Circuit Substrate For MCM-L", Yusuke Wada etc., ICEMCM, 1995, pp. 59-64.
- "Rigid-Flex" The Old and the New, Jahn Stopperan, Shendahl, Inc., 1990, 4 pages.
- "High-Performance Scalable Switch Design", Joshua Silver, ASIC & EDA, Jun. 1994, pp. 38-48.
- "Dielectric Based Antifuse For Logic and Memory ICs", Esmat Hamdy etc., IEEE 1988, pp. 786-789.
- "Advanced Single Poly BiCMOS Technology For High Performance Programmable TTL/ECL Applications", Ali Iranmanesh etc., IEEE Bipolar Circuits and Technology Meeting, 1990, 4 pages.
- "Conducting Filament of the Programmed Metal Electrode Amorphose Silicon Antifuse", Kathryn E. Gordon etc., IEEE, 1993, pp. 27-30.
- "Interconnect Devices for Field Programmable Gate Array", Chenming Hu, IEEE, 1992, pp. 591-594.
- "Antifuse Structure Comparison For Field Programmable Gate Arrays", Steve Chiang etc., IEEE, 1992, pp. 611-614.
- ASM Handbook, vol. 3, "Alloy Phase Diagrams", ASM International, believed to be published prior to Apr. 10, 1996, 4 pages.
- "Interplay of Energies in Circuit Breaker and Fuse Combinations", Bernie DiMarco etc., IEEE, 1991, pp. 1765-1769.
- "Laser Personalization of NMOS Digital Topologies", James B. Gullett etc., IEEE, 1983, pp. 1249-1252.
- "I/O Buffering System to a Programmable Switching Apparatus", Wen-Jai Hsieh etc., Official Gazette, Jan. 25, 1994, one page.
- "Characteriziang Quickturn ASICS: It's Done With Mirrors", Ron Iscoff, Semiconductor International, Aug. 1990, 6 pages.
- "An Ultra High Speed ECL Programmable Logic Device", Fred Ki etc., IEEE Bipolar Circuits and Technology Meeting, 1990, 5 pages.
- "Distribution Fuses of Nearest Future", T. Lipski, 3rd International Conference on Future Trends in Distribution Switch Gear, Jul. 26, 1990, pp. 41-45.
- "An Advancement in the Design and Application of Current-Limiting Fuses", R. Ranjan etc., General Electric Company, believed to be published prior to Apr. 10, 1996, pp. 36-40.
- "A Novel MOS PROM Using a Highly Resistive Poly-Si Resistor", Masafumi Tanimoto etc., IEEE, 1980, 4 pages.
- "CMOS Resistive Fuse Circuits", Hae-Seung Lee etc., Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1990, pp. 109-110.
- "CMOS Resistive Fuses For Image Smoothing and Segmentation", Paul C. Yu etc., IEEE, 1992, pp. 545-553.
- Letter to Hugo Goris from J. Rapaille, Philips Components, dated Jul. 6, 1994, two pages.
- "Process Considerations In Restructurable VLSI For Wafer-Scale Integratin", P. W. Wyatt, etc., IEDM, 1984, pp. 626-629.
- "A Laser Linking Process For Restructurable VLSI", G. H. Chapman, etc., CLEO, Apr., 1982, pp. 1-4.
- "TAIYO PSR-4000 Photoimageable Solder Mask (Two-Part Aqueous Developing System)", Taiyo America, Inc., Feb. 24, 1992, pp. 1-8.
- "Ball Grid Array Technology", John H. Lau, McGraw-Hill, Inc., 1995, p. 38.