High Impedance Signal Conversion Circuit and Method

The present invention generally relates to electronic circuits, and, more particularly to a circuit for converting voltages.

In modern technologies, electronic devices, such as computers, printers, scanners, modems, are getting more and more compatible and interchangeable. Also, supply voltages for such devices are decreasing.

FIG. 1 is a simplified block diagram of a prior art arrangement of device 10 with supply voltage V.sub.S1 (e.g., so-called rail-to-rail voltage) and device 20 having supply voltage V.sub.S2 .ltoreq.V.sub.S1. Convenient examples for the voltages are V.sub.S1 =5 volts and V.sub.S2 =3.3 volts. Device 10 may send signals 15 having temporarily a voltage V.sub.1 <V.sub.S1 to device 20. Second device 20 must accommodate V.sub.S1. Device 20 receives signal 15 by voltage divider 30 serving as a signal conversion circuit. Voltage divider 30 has resistors 31 and 32 serially coupled to common reference 35 of circuits 10 and 20. With magnitudes R.sub.A and R.sub.B of resistors 31 and 32, respectively, voltage divider 30 provides an intermediate voltage V.sub.2 : ##EQU1## Voltage divider 30 consumes a current I: ##EQU2## Such a current leads to power consumption in device 10 which is not convenient. In other words, circuit 10 must have enough drive capability to accommodate a low input impedance of the conversion circuit (e.g., voltage divider 30) in device 20. The impedance of circuit 20 should be high, not low. A configuration as in FIG. 1 is especially inconvenient when circuit 10 is a battery powered interface whose battery is discharged by current I.

The present invention seeks to provide an improved signal conversion circuit which mitigates or avoid the above mentioned and other disadvantages and limitations of the prior art.

FIG. 1 illustrates a simplified block diagram of a prior art arrangement of a first circuit with a first supply voltage and a second circuit with a second supply voltage;

FIG. 2 illustrates a simplified block diagram of a circuit of the present invention;

FIG. 3 illustrates a simplified circuit diagram of a circuit in a first embodiment of the present invention; and

FIG. 4 illustrates a simplified circuit diagram of a circuit in a second embodiment of the present invention.

FIG. 2 illustrates a simplified block diagram of signal conversion circuit 100 (hereinafter circuit 100) of the present invention. Circuit 100 comprises variable current source 150, network 110 of elements 115 and control unit 130. Preferably, elements 115 of network 110 are serially coupled. Network 110 has an impedance Z. Impedance Z is intended to include ohmic resistors R, capacities C, inductances L and combinations thereof. Network 110 receives input voltage V.sub.X and provides measurement voltage V.sub.M and output voltage V.sub.Y. Preferably, the voltages are related as:

with factors a and b being complex numbers. Preferably, a and b are real numbers between 0 and 1. Conveniently, network 110 has at least two elements 115 in a voltage divider configuration. But this is not essential.

Current source 150 generates current I.sub.S. Control unit 130 receives measurement voltage V.sub.M and controls current source 150 such that:

with the fraction line for division. In other words, the current I.sub.S through network 110 follows a fraction (e.g., V.sub.M) of the input voltage V.sub.X. Control unit 130 is conveniently an amplifier which does not require the full swing of V.sub.X, but accommodates the smaller swing of voltage V.sub.M. Conveniently, impedance Z is substantially independent from input voltage V.sub.X.

Before explaining details of the present invention in connection with FIG. 3, conventions used herein are explained. The term "transistor" is intended to include any device having at least two main electrodes and a control electrode. The impedance between the main elements is controlled by a signal applied to the control electrode. The transistors used to implement the present invention are, preferably, field effect transistors (FET) having source (S) and drain (D) as main electrodes and a gate (G) as control electrode. For convenience, the abbreviations also appear in the figures. Since FET are typically symmetrical components, the true designation of "source" and "drain" is only possible once a voltage is impressed on the terminals. The designation of sources (S) and drains (D) herein should therefore be interpreted in the broadest sense. Transistors can also be bipolar transistors with, for example, collectors and emitters as main electrodes and bases as control electrodes, or other devices. The present invention is useful but not limited to CMOS-technology using P-channel FET ("P-FET") and N-channel FET ("N-FET"). The terms "first type" (e.g., for P-FET 260) and "second type" (e.g., for N-FET 240) are intended to distinguish complementary transistors of opposite conductivity. For convenience, FIG. 3 illustrate the gates (G) of P-FET by small circles.

FIG. 3 illustrates a simplified circuit diagram of circuit 200 in a preferred embodiment of the present invention. Circuit 200 is based on circuit 100 of FIG. 2. Circuit 200 comprises resistors 210, 220 and 230, transistors 240, 250 and 260, and operational amplifier (op amp) 270. Transistors 250 and 260 are preferably, P-FETs and transistor 240 is an N-FET. Circuits 200 receives a supply voltage V.sub.S between reference lines 201 and 202. Circuit 200 receives an input voltage V.sub.X at input terminal 203 and provides an output voltage V.sub.Y at output terminal 204. For convenience, voltages are referred to line 202. Transistors 250 and 260 form current mirror 265 (dashed frame). Resistors 210 and 220 form voltage divider 215 (dashed frame). Transistor 250 has the function of a variable current source 150.

The source (S) of transistor 260 is coupled to line 201. The drain (D) of transistor 260 is coupled to resistor 210 at node 205. Resistor 210 is serially coupled to line 202 via node 206 and resistor 220. Input terminal 203 is coupled to node 205; and output terminal 204 is coupled to node 206. Node 206 is coupled to non-inverting input 271 of op amp 270. Inverting input 272 of op amp 270 is coupled to the source (S) of transistor 240 and coupled to line 202 via resistor 230. Output 273 of op amp 270 is coupled to the gate (G) of transistor 240. The drain (D) of transistor 240 is coupled to the drain (D) and to the gate (G) of transistor 250 and to the gate (G) of transistor 260. The source (S) of transistor 250 is coupled to line 201.

Resistors 210, 220, and 230 have resistance magnitudes R.sub.1, R.sub.2, and R.sub.3, respectively. The source-drain path of transistor 260 provides current I.sub.S which flows into node 205. Input current I.sub.X also flows into node 205 and is combined with current I.sub.S to provide current I.sub.R trough resistors 210 and 220:

Equation (6) is the application of Kirchhoff's Node Law. For convenience of explanation, the currents from node 206 to output terminal 204 and to input 271 of op amp 270 are neglected. Input voltage V.sub.X appears across resistors 210 and 220 between nodes 205 and line 202. Output voltage V.sub.Y and measurement voltage V.sub.M appear across resistor 220 between node 206 and line 202. In the example of FIG. 3, output voltage and measurement voltage are substantially equal (.apprxeq.):

Voltages V.sub.M depends on input voltage V.sub.X and the values R.sub.1 of resistor 210 and R.sub.2 of resistors 220 according to the well known relation for voltage dividers: ##EQU3## with the symbol * for multiplication. The source-drain paths of transistors 240 and 250 carry current I.sub.A conveniently defined in the direction from line 201 to line 202. Op amp 270, resistor 230 and transistor 240 form a voltage controlled current source. Current I.sub.A is related to V.sub.M trough the magnitude R.sub.3 of resistor 230:

Transistors 250 and 260 of current mirror 265 provide current I.sub.S by scaling current I.sub.A with a substantially proportional factor k:

Factor k is a real number and related to the magnitudes R.sub.3 and R.sub.2 as:

Preferably, the magnitudes of resistors 220 and 230 are substantially equal (.apprxeq.):

so that factor k is about k.apprxeq.1. But other values can also be used.

Assume that transistor 260 is disconnected from circuit 200 and input voltage V.sub.X causes current I.sub.R through resistors 210 and 220 according to: ##EQU4## Such an arrangement would have low impedance and would take energy from input terminal 203. According to the invention, current I.sub.R is substantially provided by variable currents source 150 (e.g., transistor 260):

I.sub.X can be neglected and assumed to be around zero:

Changes in the magnitude of I.sub.S are controlled according to changes in the magnitude of input voltage V.sub.X. Using equations (8), (9), and (10), I.sub.S is calculated as: ##EQU5## It is also convenient when currents I.sub.S and I.sub.A are also substantially equal:

Resistors 210 and 220 are, conveniently related as:

Factor r is conveniently a real number from almost zero (r.apprxeq.0) to r.apprxeq.10 or higher. Preferably, factor r has a value of about:

It is an important advantage of the present invention that circuit 200 can be used in modern low voltage applications. For convenience, voltages are considered as absolute values .vertline..vertline.. The supply voltage .vertline.V.sub.S .vertline. is larger to or substantially equal (.gtoreq.) to the sum of the drain-source voltage .vertline.V.sub.DS .vertline. of transistor 260 (line 201 and node 205) and input voltage V.sub.X (node 205 to line 202):

Transistor 260 preferably operates in the saturation region so that the voltage .vertline.V.sub.DS .vertline. is a saturation ("SAT") voltage .vertline.V.sub.DSAT .vertline.. Input voltage V.sub.X can be expressed by R.sub.1, R.sub.2, and I.sub.S. Supply voltage .vertline.V.sub.S .vertline. can also be estimated as:

When circuit 200 is implemented on a monolithic chip with a CMOS-process, supply voltage .vertline.V.sub.S .vertline. can be as low as, for example and not intended to be limiting 1.8 volts.

Circuit 200 of the present invention is compared to resistor arrangement 31/32 in device 20 of the prior art. By simulation, similar sine signals are applied as input signals and the input currents are measured. The simulation method is SPICE, but other simulation methods well known in the art would lead to similar results. Resistance magnitude are, for example,

(a) First, a voltage V.sub.1 was applied across resistors 31 and 32 (cf. FIG. 1) of prior art circuit 20. In a well known representation, voltage V.sub.1 is expressed as:

with frequency F, time t, .pi..apprxeq.3.14 . . . , and "sin" for the sine function. The usual abbreviations "DC" and "AC" stand for "direct current" and for "alternating current", respectively. The frequency was F.apprxeq.5 MHz. A resulting current I, similarly expressed as:

was determined with I.sub.DC .apprxeq.100 .mu.A and I.sub.AC .apprxeq.5 .mu.A.

(b) Second, a similar voltage V.sub.X .apprxeq.V.sub.1 with the same frequency F was applied to circuit 200 of the present invention. A resulting current I.sub.X was determined with I.sub.DC '.apprxeq.2 .mu.A and I.sub.AC '.apprxeq.1 .mu.A. Circuit 200 has input current I.sub.X which is about 5 times (for AC) and 50 times (for DC) lower than input current I of prior art arrangement 31/32. In other words, circuit 200 has a high input impedance and does not significantly load the source of I.sub.X.

FIG. 4 illustrates a simplified circuit diagram of circuit 200' in a second embodiment of the present invention. Circuit 200' is a variation of circuit 200 (FIG. 3) without optional transistor 240. Primed reference numbers in FIG. 4 correspond to unprimed numbers in FIG. 3. For simplicity, voltages and currents are not illustrated in FIG. 4. Circuit 200' comprises transistors 250' and 260', resistors 210', 220', and 230' and op amp 270'. Transistors 250' and 260' are, preferably, P-FETs. Circuit 200' has a first current path from line 201 to line 202 with serially coupled source (S) and drain (D) of transistor 260', node 205', resistor 210', node 206', and resistor 220'.

Circuit 200' has a second current path with the source (S) of transistor 250' coupled to line 201', the drain (D) of transistor 250' coupled to line 202' via resistor 230'. Output 273' of op amp 270' is coupled to the gates (G) of transistors 250' and 260'. Non-inverting input 271' of op amp 270 is coupled to the drain (D) of transistor 250'. Inverting input 272' of op amp 270 is coupled to node 206'.

The operation of circuit 100 and its embodiments in circuits 200 and 200' can be described as a method of the present invention. The method provides a substantially constant impedance between a first node (e.g., node 205) and a second node (e.g., line 202) which receive a voltage V.sub.X. The method comprises the following steps:

(1) A partial voltage V.sub.M is measured between reference points located between the nodes. The reference points are, for example, node 206 and line 202 (FIG. 3). One of the reference points can be obtained, for example, by a resistor voltage divider (e.g., resistors 210 and 220) between the nodes.

(2) A current I.sub.S is provided to the first node. The current I.sub.S has a variable magnitude which corresponds to a magnitude of a current I.sub.X which is caused by V.sub.X across a resistance (e.g., R.sub.1 +R.sub.2) between the nodes. Current I.sub.S can be provided by converting the partial voltage V.sub.M to a current I.sub.A (e.g., in op amp 270) and mirroring the current I.sub.A (by e.g., transistors 250 and 260).

While the invention has been described in terms of particular structures, devices and methods, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow.