Signal Modulating Method, Signal Modulating Apparatus, Signal Demodulating Method and Signal Demodulating Apparatus

This invention relates to a signal modulating method, a signal modulating apparatus, a signal demodulating method and a signal demodulating apparatus which are used for recording or reproducing digital signals, such as, digital speech signals, digital video signals and data, in a recording medium, and for example, to the signal modulating method, the signal modulating apparatus, the signal demodulating method and the signal demodulating apparatus which may be adapted for a mastering device for a read-only optical disc or a recording/reproducing device for a re-writable optical disc.

When recording digital signals, such as digital speech signals, digital video signals or data, error correction code data is first appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by channel coding into the code suited to the characteristics of a recording/reproducing system.

An optical disc, such as, a compact disc (CD), is a recording medium having a wide field of application as a package medium for picture information or as a storage device for a computer. The optical disc system reproduces signals recorded on a reflective surface of the disc via a transparent substrate having a thickness of the order of 1.2 mm. On the optical disc, information such as digitized audio signals, video signals or digital data, is recorded. In this case, the error correction code data is appended to the digital signals, and the resulting data is routed to a modulating circuit where it is converted by so-called channel coding into code data suited to the characteristics of the recording/reproducing system.

The signal format of the above-mentioned compact disc (CD) system is summarized as follows:

The modulation system employed is 8-14 conversion or EFM.

With the EFM, an input 8-bit code, referred to hereinafter as a symbol, is converted into a 14 channel bit code, to which a frame synchronization signal of 24 channel bits and a subcode of 14 channel bits are appended and the neighboring codes are interconnected by merging bits of 3 channel bits. The resulting data is recorded by the NRZI modulation system.

FIG. 1 shows a frame structure of the CD system.

Referring to FIG. 1, 24 symbol data (music signals) and 8 symbol parity, entering a modulating circuit from a cross-interleave Reed-Solomon code (CIRC) encoder during a sync frame (6 sample value domains, six samples each of the L and R channels, with each sample being 16-bit data) are transformed into 14 channel bits and connected by merging bits of three channel bits to give 588 channel bits per frame. The resulting data is recorded by the NRZI system at a channel bit rate of 4.3218 Mbps.

The respective symbols entering the modulating circuit are transformed, with reference to a lookup table composed of a ROM, into a channel bit pattern in which the number of "0"s between "1" and "1" is not less than 2 and not more than 10. The channel bit pattern of a frame synchronization signal Sf is "100000000001000000000010" in binary expression. As for the merging bit pattern, one of "000", "001", "010" and "100" is selected. Each sub-coding frame is made up of 98 frames. As the subcode for the 0'th and first frames, the subcode sync signal S0 (="00100000000001") and S1 (="00000000010010") are appended (see FIG. 2).

FIG. 3 shows, for a typical sample value of input data, a channel bit pattern after EFM and a digital sum variation (DSV).

Each 16-bit sample is split into upper 8 bits and lower 8 bits each of which is entered to the modulation circuit via a CIRC encoder for 8-14 conversion to produce 14 channel-bit information bits. Not less than 2 and not more than 10 "0 "s are interposed between "1" and "1" of the information bits, as previously described. One of the merging bits "000", "001", "010" and "100" is selected. This rule is observed at all times at the connecting portions of the 14 information bits, so that EFM signals based on 17-channel bits are generated and outputted from the modulating circuit at 4.3218 Mbps. The number of channel bits is 27 in the case of the frame synchronization signal Sf.

Since not less than 2 and not more than 10 channel bits are interposed between an optional channel bit "1" and the next channel bit "1", the period during which the high level or the low level of the NRZI recording waveform continues, that is the recording wavelength, is necessarily not less than 3 T and not more than 11 T (see FIG. 3).

In this case, the shortest recording wavelength is 3 T and the longest recording wavelength is 11 T, with T being a period of a channel clock of 4.3218 MHz. This is referred to hereinafter as the 3 T.about.11 T rule of the EFM modulation regulation.

The digital sum value or variation (DSV) is now considered as an index of the dc balance of the NRZI recording waveform. The DSV is given as a time integral of the recording waveform. That is, the variant of the DSV when the high level of the recording waveform has continued for a unit time T is +1, while the variant of the DSV when the low level of the recording waveform has continued for a unit time T is -1.

The time change of DSV when the initial value of DSV at time t.sub.0 is assumed to be zero is given at the lower most portion of FIG. 3. The modulated signal during the time since t.sub.1 until t.sub.2 is not uniquely determined by the 17-channel bit pattern "01000001000001001", but depends on the modulated signals level at time t.sub.1, that is on the ultimate level of the modulated signal waveform during the time interval from time t.sub.0 until time t.sub.1 (referred to hereinafter as CWLL).

Thus the modulated signal waveform illustrated is that for the CWLL at time t.sub.0 being at a low level (CWLL="0"). The modulated signal waveform for CWLL="1" (high level) is inverted from the pattern for CWLL="0" so that the high and low levels are inverted to low and high levels, respectively.

Similarly, the DSV is also increased or decreased depending upon the CWLL, such that, if CWLL="0" at time t.sub.0, the DSV variant with the information pattern "01000100100010" (referred to hereinafter as 14 NWD), that is the DSV variant during the time period from t.sub.0 until t.sub.0 +14, is +2, as shown in FIG. 3. Conversely, if CWLL="1" at time t.sub.0, 14 NWD=-2. The DSV variant since time t.sub.0 +14 until t.sub.1 +14 is referred to as 17 NWD.

The merging bits, inserted since time t.sub.0 +14 until time t.sub.1, is now explained. Of the four margin bits "000", "001", "010" and "100", "001" or "100" cannot be inserted under the above-mentioned 3 T.about.11 T rule, such that only "010" or "000" can be inserted. That is, if the number of "0"s at the trailing end of the previous information bit pattern, outputted before the merging bit, is B, and the number of "0"s at the leading end of the subsequently outputted current information bit pattern is A, since B=1 and A=1, the leading and trailing ends of the merging bit must be "0" and "0", such that the merging bit pattern that can be inserted becomes "0X0", where X is arbitrary (don't care).

In the lower most portion of FIG. 3, there is shown the DSV with the bits "010" inserted as merging bits, by a solid line, while there is shown the DSV with the bits "000" inserted as merging bits, by a broken line.

In general, the merging bits to be inserted at a connecting point need to be selected so that the 3 T.about.11 T rule of the modulation regulation will be met. Similarly, such merging bits are prohibited which, when inserted, will produce a repetition by two times of a 11 T pattern which is the same as the 11 T frame synchronization pattern.

Of the merging bits satisfying the above requirements, such merging bits are selected as optimum merging bits which, when inserted, will produce the smallest absolute value of the cumulative DSV from the merging bit until the end of the next information bit pattern connected to the prevailing cumulative DSV.

In the example of FIG. 3, the DSV at time t.sub.1 +14 when the merging bits "010" are inserted is +3, while the DSV at the same time point when the merging bits "000" are inserted is -1, so that the merging bits "000" are selected.

The merging bits, found by the above-described algorithm, satisfy the 3 T.about.11 T rule of the modulation regulation at the connecting portion between two 14-bit data, while prohibiting generation of an erroneous frame sync signal and approaching the cumulative DSV of the EFM signal to a value as close to zero as possible.

Meanwhile, with the conventional EFM system, since the shortest run-length is limited to two, two merging bits suffice if for the purpose of coping with run-length limitations. If the number of the merging bits can be reduced to two, the data recording density may be increased by a factor of 17/16 without altering the physical size such as the recording wavelength.

However, there are only three sorts of the 2-bit merging bits. In addition, it is a frequent occurrence that only one of the three sorts of the merging bits can be inserted because of limitations such as those imposed by run-length. Thus, with the conventional DSV control system, there exist a large number of domains in which it is impossible to control the DSV. Consequently, low-frequency components of the modulated signals cannot be sufficiently suppressed to affect servo stability or the data error rate on data demodulation.

In view of the foregoing, it is a principal object of the present invention to provide a signal modulating method, a signal modulating apparatus, a signal demodulating method and a signal demodulating apparatus whereby the input M bits, such as an input 8-bit code string, is directly transformed into N-channel bits, such as 16 channel bits, without employing the above-mentioned merging bits at the time of signal modulation, thereby reducing ill effects on the DSV control and also enabling sufficient suppression of the low-frequency components.

According to the present invention, there is provided a signal modulating method for converting an M-bit based data string into an N-bit based code string, where M and N are integers having a relation of M<N, and for connecting an N-bit code to a next N-bit code, the method including: a first step of receiving the M-bit based data string as an input signal value; a second step of converting the M-bit data into the N-bit code in accordance with a conversion table; and a third step of outputting the N-bit based code string as a modulation result. The conversion table is constituted by first and second sub-tables including plural code groups, respectively. The plural code groups include different codes for the same input. The second sub-table is a table which is partly duplexed with the first sub-table and is produced by allocating different codes to data of first input data to second input data of the first sub-table. The first and second sub-tables are so designed that code sets of the duplexed portions take variants of digital sum variations which are opposite in sign. Codes are allocated to all the code groups in the duplexed portions of the first and second sub-tables with respect to input data sequentially from a code having a maximum absolute value of variant of the digital sum variation.

According to the present invention, there is also provided a signal modulating apparatus for converting an M-bit based data string into an N-bit based code string, where M and N are integers having a relation of M<N, and for connecting an N-bit code to a next. N-bit code, the apparatus including: receiving means for receiving the M-bit based data string as an input signal value; conversion means for converting the M-bit data into the N-bit code in accordance with a conversion table; and output means for outputting the N-bit based code string as a modulation result. The conversion table is constituted by first and second sub-tables including plural code groups, respectively. The plural code groups include different codes for the same input. The second sub-table is a table which is partly duplexed with the first sub-table and is produced by allocating different codes to data of first input data to second input data of the first sub-table. The first and second sub-tables are so designed that code sets of the duplexed portions take variants of digital sum variations which are opposite in sign. Codes are allocated to all unit tables in the duplexed portions of the first and second sub-tables with respect to input data sequentially from a code having the maximum absolute value of variant of the digital sum variation.

According to the present invention, there is also provided a signal demodulating method for inversely converting an N-bit based code string to generate an M-bit based data string, where M and N are integers having a relation of M<N, the method including: a first step of receiving an N-bit based input code string; a second step of inversely converting the N-bit input code into M-bit data in accordance with an inverse conversion table; and a third step of outputting an M-bit based data string as a demodulation result. The inverse conversion table is constituted by first and second sub-tables including plural code groups, respectively. The plural code groups have the same output data for different input codes. The second sub-table is a table which is partly duplexed with the first sub-table and is produced by allocating different input codes to data from first output data to second output data of the first sub-table. The first and second sub-tables are so designed that code sets in the duplexed portions take variants of digital sum variations which are opposite in sign. To all the code groups in the duplexed portions of the first and second sub-tables, output data is allocated sequentially from a code having the maximum absolute value of variant of the digital sum variation.

According to the present invention, there is also provided a signal demodulating apparatus for inversely converting an N-bit based code string to generate an M-bit based data string, where M and N are integers having a relation of M<N, the apparatus including: receiving means for receiving an N-bit based input code string; inverse conversion means for inversely converting the N-bit input code into M-bit data in accordance with an inverse conversion table; and output means for outputting an M-bit based data string as a demodulation result. The inverse conversion table is constituted by first and second sub-tables including plural code groups, respectively. The plural code groups have the same output data for different input codes. The second sub-table is a table which is partly duplexed with the first sub-table and is produced by allocating different input codes to data from first output data to second output data of the first sub-table. The first and second sub-tables are so designed that code sets in the duplexed portions take variants of digital sum variations which are opposite in sign. To all the code groups in the duplexed portions of the first and second sub-tables, output data is allocated sequentially from a code having the maximum absolute value of variant of the digital sum variation.

According to the present invention, there is also provided a signal modulating method for converting an M-bit based data string with reference to a predetermined conversion table into an N-bit based code string, where M and N are integers having a relation of M<N, and for connecting an N-bit code to a next N-bit code. The conversion table is produced by: a first step of selecting codes meeting predetermined modulation rules from all possible patterns of N-bit based codes; a second step of classifying the selected codes into plural code groups in accordance with plural different code conditions; a third step of calculating variants of digital sum variations of the codes of the plural code groups; a fourth step of arraying the codes sequentially from a code having a greater variant of digital sum variation of the plural code groups; a fifth step of allocating the arrayed codes to the M-bit data from the code having a greater variant of digital sum variation of the code groups to generate a first sub-table; and a sixth step of allocating codes other than the codes included in the first sub-table of the codes meeting the predetermined modulation rules, to first data to second data of all data, from a code having a greater absolute value of variant of the digital sum variation, to generate a second sub-table having a portion duplexed with the first sub-table.

With this invention, since in the duplexed portions of the conversion tables, the corresponding code sets have variants of digital sum variations (DSV) which are opposite in sign and close to each other in absolute value, DSV control can be achieved by selecting one of the duplexed portions without using a margin bit used in conventional modulation. In addition, since the conversion table in which codes having greater absolute values of variants of the digital sum values are allocated sequentially to the duplexed portion is used, low frequency components of the modulated signals are sufficiently suppressed.

FIG. 1 shows a frame construction of a conventional modulated output signal.

FIG. 2 shows a sub-coding frame structure of a conventional modulated output signal.

FIG. 3 shows conventional sample values and the EFM modulated waveform.

FIGS. 4a-4g shows an example of a conversion table employed in an embodiment of the present invention.

FIG. 5 is a flow chart showing an example of an algorithm constituting the conversion table.

FIG. 6 shows an example of a unit table with the state value being 1.

FIG. 7 shows an example of a unit table with the state value being 2.

FIG. 8 shows an example of a unit table with the state value being 3.

FIG. 9 shows an example of a unit table with the state value being 4.

FIG. 10 is a flow chart showing an example of an algorithm of the signal modulating method embodying the present invention.

FIG. 11 is a flow chart showing an illustrative construction of a signal modulating apparatus embodying the present invention.

FIG. 12 is a graph showing how low-frequency components in the modulated signal may be decreased in the embodiment of the present invention as contrasted to the conventional system.

FIG. 13 is a flow chart showing an example of the algorithm of the signal modulating method as an embodiment of the present invention.

FIG. 14 is a block diagram showing an illustrative construction of a signal demodulating apparatus embodying the present invention.

Applicants hereby incorporate by reference the entire disclosure of the parent application Ser. No. 08/612,952 filed Mar. 8, 1996, now U.S. Pat. No. 5,818,367. Preferred embodiments of the signal modulating method, the signal modulating apparatus, the signal demodulating method and the signal demodulating apparatus will now be described with reference to the drawings.

The signal modulating method and the signal modulating apparatus according to the present invention are effected on the assumption of converting an input M-bit based data string into an N-bit based code string, M and N being integers in a relation of M<N, and connecting the N-bit code to the next N-bit code. The conversion table for converting the M-bit based data string into the above-mentioned N-bit based code string is partially duplexed. The duplexed portions are configured so that the variants of the digital sum variation (digital sum value) of the codes of each of two mutually associated code sets are opposite in sign and close to each other in the absolute value.

FIG. 4 shows an example of the conversion table.

The conversion table is made up of a plurality of, e.g., four different sorts of unit tables T.sub.1, T.sub.2, T.sub.3 and T.sub.4, each unit table having a duplexed portion, as shown in FIG. 4. That is, if a table of sets of codes (channel bit patterns) for the totality of input signal values for a unit table is denoted as Ta, part of it is duplexed to form a table Tb. With the illustrative example of FIG. 4, 88 codes with input signal values of from 0 to 87 are duplexed. In the present specification, the table Ta and the table Tb are termed a front side table and a back side table, respectively.

Thus, with the illustrative example of FIG. 4, the conversion table is constituted by four sorts of tables T.sub.1a, T.sub.2a, T.sub.3a, T.sub.4a for 256 16-bit codes or 256 16-channel bit patterns, associated with 8-bit input signal values of from 0 to 255, constituting the front side table, and four tables T.sub.1b, T.sub.2b, T.sub.3b, T.sub.4b, which are duplexed for 88 16-channel bit patterns of the tables T.sub.1a, T.sub.2a, T.sub.3a, T.sub.4a having the input signal values of from 0 to 87, constituting the back side table. In the present embodiment, the duplexed portions of the conversion table, that is the 16-bit codes for the input signal values of from 0 to 87 of the tables T.sub.1a, T.sub.2a, T.sub.3a, T.sub.4a and the 16-bit codes for the input signal values of from 0 to 87 of the tables T.sub.1b, T.sub.2b, T.sub.3b, T.sub.4b, are configured so that the variants of the digital sum value or variation of the associated code sets are opposite in polarity and close in magnitude to each other.

An embodiment of the signal modulating method employing the conversion table of FIG. 4 is explained.

With the present embodiment, shown in FIG. 4, the input 8-bit signal (data) is converted to a 16-bit code. In the conventional EFM system, the input 8-bit signal is converted into a 14-bit information bit pattern which is connected to a neighboring 14-information bit pattern via 3-bit merging bits. In the present system, the 8-bit input signal is directly converted into a 16-bit code without employing the merging bits. The present modulation system is referred to hereinafter as a 8-16 modulation system. The 8-16 modulation also satisfies the condition for EFM that the number of "0"s between "1" and "1" should be not less than 2 and not more than 10, that is the 3 T.about.11 T rule.

In the EFM, only one table is provided for converting the input 8-bit signal into a 14-bit code. With the 8-16 modulation system, plural sorts of tables are provided for converting the input 8-bit signal into a 16-bit code. In the embodiment shown in FIG. 4, four sorts of unit tables T.sub.1, T.sub.2, T.sub.3 and T.sub.4 are employed.

The "state values" employed in the classification of the unit tables is explained.

The state values play the part of indices for judging which of the conversion tables is to be employed when converting the input 8-bit signal (data) into the 16-bit code. Thus the kinds of the state values is equal to that of the different sorts of the unit tables of the conversion table. That is, in the present embodiment, there are four kinds of state values [1] to [4] in association with the four sorts of the unit tables T.sub.1, T.sub.2, T.sub.3 and T.sub.4.

The state values undergo transition each time a 8-bit symbol is converted into a 16-bit code. If the 16-bit code ends with "1" or "10", the state value undergoes transition to [1]. If the 16-bit code ends with not less than 2 and not more than 5 consecutive "0"s, the state value undergoes transition to [2] or [3]. If the 16-bit code ends with not less than 6 and not more than 9 consecutive "0"s, the state value undergoes transition to [4]. When a code undergoing transition to the state value "2" and a code undergoing to the state value "3" can be handled as perfectly different codes, whether the state value is [2] or [3] may be arbitrarily determined in producing the table.

The conversion table for converting the input 8-bit signal into the 16-bit code has the following characteristics.

The unit table T.sub.1 employed when the state value is [1] is made up of 16-bit codes beginning with at least two "0"s in order to meet the condition that the number of "0"s between "1" and "1" should be not less than 2 and not more than 10 (3 T.about.11 T rule). The reason is that the 16-bit code modulated before transition of the state value to [1] ends with "1" or "10".

For the same reason, the unit tables T.sub.2 or T.sub.3, employed for the state values of [2] or [3], respectively, are made up of 16-bit codes beginning with 0 to 5 consecutive "0"s. It is noted that the unit table T.sub.2 employed for the state value equal to [2] is made up of codes having both the first bit and the 13th bit (that is, the fourth bit from LSB) equal to "0", with the MSB being the first bit, while the unit table T.sub.3 employed for the state value equal to [3] is made up of codes having one or both of the first bit and the 13th bit (the fourth bit from LSB) equal to "1", with the MSB again being the first bit.

The unit table T.sub.4 employed when the state value is [4] is made up of 16-bit codes beginning with "1" or with "01".

There exist 16-bit codes which can be employed in common for the two different state values. For example, a 16-bit code beginning with three consecutive "0"s and having the first and the 13th bits equal to "0" may be employed both with the state value equal to [1] and with the state value equal to [2]. In order to prohibit possible confusion during decoding, the table needs to be configured so that the codes of different state values are associated with the same input 8-bit signal value (data).

On the other hand, the 16-bit code of the type in which the state value subsequently undergoes transition to [2] or [3] can be associated with two totally different sorts of the input 8-bit signals. Although the 16-bit code cannot be uniquely decoded by themselves, they can be correctly decoded by necessarily setting the next occurring state value to [2] or [3]. This method will be explained subsequently.

There is provided another table for indicating for respective codes of the unit tables, to which of [1] to [4] the next state values transfer when the input 8-bit signals are converted to the codes. If the 16-bit codes end with not less than 2 and not more than 5 consecutive "0"s, it is not possible to determine whether the state values next transfer to [2] or [3] by the code features themselves. However, the next state values can be uniquely determined by having reference to this table. Meanwhile, the state value is necessarily [1] following the synchronization pattern.

In the example of FIG. 4, the next state value is indicated by S for constituting the table consisting of the state values S indicating the transition direction.

Using the above tables, a modulator modulates 8-bit input symbols into 16-bit codes. The current state values are stored in the internal memory and the table to be referred to is identified from the state values. The 8-bit input signals are converted by the table by way of effecting the modulation. Simultaneously, the next state values are found from the table and held on memory so that the table to be referred to during the next conversion will be identified. The practical hardware configuration will be explained subsequently.

The digital sum variation or digital sum value (DSV) is controlled in the following manner.

It is checked for each state value how many 16-bit codes there exist which satisfy the run-length limitations (3 T.about.11 T rule) and can be used satisfactorily. For inhibiting occurrence of two repetitive patterns of 11 T which are the same as the frame synchronization pattern, such 16-bit code in which ten "0"s are arrayed and followed by "1" followed in turn by five "0"s are pre-eliminated. The reason is that, if the code is connected to a 16-bit code pattern beginning with five consecutive "0"s, the two repetitive patterns of 11 T are produced. If, after conversion to a 16-bit code, the state value undergoes transition to [2] or [3], the code may be used in two ways, so that these codes are counted twice.

The results of calculations indicate that 344 16-bit codes can be used with the state value of [1], 345 16-bit codes that can be used with the state value of [2], 344 16-bit codes can be used with the state value of [3] and 411 16-bit codes can be used with the state value of [4]. Since the input signal is a 8-bit signal, 256 codes suffice, so that there are at least 88 superfluous codes for the respective state values. These 88 superfluous codes are used for DSV control purposes. That is, using these superfluous codes, a table with the number of 88 entries is separately provided as a back side table. This back side table is provided in the present embodiment for the input 8-bit signals of from "0" to "87".

For achieving efficient DSV control with the present DSV control system, the front side and back side tables are constituted under the following principle.

There exist 16-bit codes that can employ two different state values in common as described above. Since the table needs to be formulated so that the same input 8-bit signal values (data) are associated with these codes at all times, the table formulating methods in this case are complicated because of these limitations. Since it is intended herein to indicate the method of formulating the table with a view to efficient DSV control, the following description is made on the assumption that the respective state values are taken independently and the 16-bit codes that can be used for the respective state values may be freely allocated to respective values of the input 8-bit signals.

The flow chart of FIG. 5 is intended for illustrating the method for formulating the above-mentioned conversion table, more specifically, the method for formulating an optional one of the four sorts of the unit tables of the conversion table.

Referring to FIG. 5, the totality of patterns of the 16-bit codes are found at step S101. At the next step S102, the bit patterns or codes which will satisfy the condition of the run-length limitation (3 T.about.11 T) are selected. At the next step S103, the codes are classified into codes which will follow the above-mentioned state-value-based conditions. The number of the 16-bit codes that may be employed for these state values is 344 to 411, as previously explained. For example, the number of the 16-bit codes that can be employed for the state value of [1] is 344.

At the next step S104, the amount of variation of the DSV for the level directly previous to each code (=CWLL) being low is calculated for each code for each of the state values. Since the code length is 16 bits, and the amount of variation of the DSV per code is -10 at the minimum and +10 at the maximum. If the state value is [1], as an example, the amount of DSV variation is -10 at the minimum and +6 at the maximum.

At the next step S105, the 344 16-bit codes having the state value equal to [1] are sequentially arrayed beginning from the code having the larger DSV variant on the positive side up to the code having the larger DSV variant on the negative side, by way of effecting the sorting.

At the next step S106, 88 16-bit codes are selected in order of decreasing amount of DSV variation on the positive side and sequentially allocated to "0" to 87" of the 8-bit input signal in the front-side table T.sub.1a in FIG. 6 for the state value of [1]. The larger the absolute value of the DSV variation of the selected 88 16-bit code, the smaller is the value of the input 8-bit signal to which the 16-bit code is allocated. On the other hand, 88 16-bit codes are selected in order of decreasing amount of DSV variation on the negative side and sequentially allocated to "0" to 87" of the 8-bit input signals in the back-side table T.sub.1b in FIG. 6. The larger the absolute value of the DSV variation of the selected 88 16-bit codes, the smaller is the value of the input 8-bit signal to which the 16-bit code is allocated. Finally, 168 16-bit codes are selected in order of small absolute value of the DSV variation and allocated to "88 to 255" of the 8-bit input signal in the front-side table T.sub.1a in FIG. 6.

If the state value is [1], the number of the 16-bit codes that can be employed is 344, so that the totality of codes that can be employed may be selected at this stage, as shown in FIG. 6.

FIGS. 7, 8 and 9 show examples of allocation of input signal values in the unit tables of the conversion table which are employed for the state values of [2], [3] and [4], respectively.

In FIGS. 6 to 9, the sequence of the 16-bit signals having the same amount of DSV variation is changed from that in the example of FIG. 4 during sorting. However, any of these tables may be employed without any inconvenience.

If the front side and back side tables Ta, Tb are formulated under the above-described principle, one of two 16-bit codes with opposite signs and with the larger absolute value of the DSV variant may be selected for the input 8-bit signal having a value between "0" and "87", thus enabling efficient DSV control. If the input 8-bit signal has a value between "88" and "255", the 16-bit codes are uniquely set such that DSV control cannot be performed. However, since these 16-bit codes are of the smaller absolute value of the DSV variant, it becomes possible to maintain the smaller absolute value of the cumulative DSV at all times.

The back side table Tb with 88 entries, defined as described above, has the same characteristics as those of the front side table Ta with 256 entries, except that the number of entries is small.

The DSV control is performed using both the front side table Ta and the back side table Tb. If the input 8-bit signal has a value between "0" and "87", which of the front side table Ta or the back side table Tb should be employed at the time of conversion of the input 8-bit signal into the 16-bit codes can be selected adaptively. Thus, with the present embodiment, the cumulative DSV is calculated at all times, the cumulative DSV in case the conversion is performed using the front side table Ta and the cumulative DSV in case the conversion is performed using the back side table Tb are calculated and that one of the tables which will reduce the absolute value of the cumulative DSV closer to zero is selected for effecting the conversion.

Referring to FIG. 10, the algorithm of the signal modulating system of the present embodiment employing the above-described conversion table is explained.

When a 8-bit signal (data) is entered at step S1, the current state value is acquired at step S2. It is then checked at step S3 whether or not the 8-bit input signal is not more than 87.

If the result of judgement at the step S3 is YES, that is if the input signal value is found to be 87 or less, the program transfers to step S4 in order to refer to the front side table Ta responsive to the current state value to acquire a 16-bit code corresponding to the input signal value and to calculate a cumulative DSV value xa. At the next step S5, the back side table Tb responsive to the current state value is referred to in order to acquire a 16-bit code corresponding to the input signal value and to calculate a cumulative DSV value xb. At the next step S6, the relative magnitudes of the cumulative DSV values xa and xb, that is whether or not .vertline.xa.vertline..ltoreq..vertline.xb.vertline., are judged.

If the result of judgement at the step S3 is NO, that is if the input signal is found to be larger than 87, the program transfers to step S7 in order to refer to the front side table Ta responsive to the current state value to acquire a 16-bit code corresponding to the input signal value, before the program transfers to step S10. If the result of decision at step S6 is YES, that is if .vertline.xa.vertline..ltoreq..vertline.xb.vertline., the front side table Ta is referred to in order to acquire a 16-bit code before the program proceeds to step S10. If the result of decision at step S6 is NO, that is if the absolute value of the cumulative DSV value xb of the back side table Tb is found to be smaller, the back side table Tb is referred to in order to acquire a 16-bit code before the program proceeds to step S10.

At step S10, the cumulative DSV is calculated and updated. At step S11, the table for the next state value, that is the table collectively showing the next state values S of FIG. 4, is referred to in order to update the state value. At the next step S12, the acquired 16-bit code is outputted.

FIG. 11 shows, in a block circuit diagram, a typical construction of a signal modulating apparatus for realization of a signal modulating system embodying the present invention.

Referring to FIG. 11, a 8-bit input signal is entered to a comparator circuit 10 and an address generating circuit 21.

The comparator 10 compares the input 8-bit signal to a value "88". If the value of the 8-bit input is smaller than "88", the above-mentioned DSV control becomes feasible. Thus the comparator 10 instructs the selectors 11 and 12 to enter the DSV control mode.

If instructed by the comparator 10 to enter the DSV control mode, the selector 11 transmits the 8-bit input signal to address generators 14 and 17. If the 8-bit input signal is not less than "88", an instruction is issued from the comparator 10 to the effect that DSV control is not feasible and is not carried out. Thus the input 8-bit signal is not transmitted to the address generators.

A state value storage memory 13 is a memory for storing the current state value of from [1] to [4].

A cumulative DSV storage memory 25 is a memory for storing the current value of the cumulative DSV.

A conversion table ROM 23 for the 16-bit codes is a table ROM for storing 16-bit codes to which the 8-bit input signal values are to be converted. There are the four unit tables T.sub.1, T.sub.2, T.sub.3 and T.sub.4 associated with the respective state values. In addition, the 16-bit codes are duplexed as far as the input signal values of "0" to "87" are concerned, such that there exist the codes included in the front side table Ta and those included in the back side table Tb. Thus there are eight sorts of tables T.sub.1a to T.sub.4b. Using these tables T.sub.1a to T.sub.4b, it becomes possible to receive an address which is determined from three parameters, that is the 8-bit input signal, state value and a value indicating which of the front side table or the back side table is to be used, and to find the associated 16-bit code.

A next state value decision table ROM 27 is a table ROM for storing the next state value which prevails after conversion of the 8-bit input signal value to a 16-bit code. There are four tables for the respective state values, while the tables are duplexed as far as the input signal values of "0" to "87" are concerned, such that there is the back side table in addition to the front side table. That is, next state value decision tables T.sub.1a-s, T.sub.1b-s, T.sub.2a-s, T.sub.2b-s, T.sub.3a-s, T.sub.3b-s, T.sub.4a-s and T.sub.4b-s in association with the code tables T.sub.1a, T.sub.1b, T.sub.2a, T.sub.2b, T.sub.3a, T.sub.3b, T.sub.4a and T.sub.4b, respectively. These tables T.sub.1a-s to T.sub.4b-s receive addresses determined from the three parameters, namely the 8-bit input signal values, the current state values and the value indicating which of the front side table or the back side table is to be employed, and finds out the associated next state value.

The address generating circuit 14 acquires the 8-bit input signal and the current state value supplied from the state value storage memory 13 in order to generate an address for producing from the 16-bit code table ROM 23 an address for acquiring the 16-bit code in case of employing a table Ta (hereinafter referred to as the first table) to transmit the address to a read-out circuit 15.

The read-out circuit 15 receives the address signal from the address generating circuit 14 and, using the address signal, acquires a 16-bit code from the 16-bit code table ROM 23. This code is transmitted to a cumulative DSV calculating circuit 16.

The cumulative DSV calculating circuit 16 calculates, from the 16-bit code received from the read-out circuit 15 and from the current cumulative DSV value received from the cumulative DSV storage memory 25 the value of the cumulative DSV resulting from employing the 16-bit code and transmits the calculated cumulative DSV value to a comparator circuit 20.

The address generating circuit 17 receives the 8-bit input signal and the current state value from the state value storage memory 13. The address generating circuit 17 also generates an address resulting from employing the second table from the 16-bit code table ROM 23 and routes the address to a read-out circuit 18.

The read-out circuit 18 receives the address signal from the address generating circuit 17 and, using the address signal, produces a 16-bit code from the 16-bit code table ROM 23. This code is routed to a cumulative DSV calculating circuit 19.

The cumulative DSV calculating circuit 19 calculates, from the 16-bit code received from the read-out circuit 18 and the value of the current DSV received from the cumulative DSV storage memory 25, the value of the cumulative DSV resulting from employing the 16-bit code, and transmits the calculated value to a comparator circuit 20.

The comparator 20 acquires, from the cumulative DSV calculating circuit 16 and the cumulative DSV calculating circuit 19, the value of the cumulative DSV in case of effecting the conversion using the first table and the value of the cumulative DSV in case of effecting the conversion using the second table and compares the corresponding absolute values to each other. Which of the tables gives the smaller absolute value of the cumulative DSV is determined and a signal indicating which table is to be employed is transmitted to the selector 12.

If instructed by the comparator 10 to enter the DSV control mode, the selector 12 routes a signal indicating which of the first and second tables is to be employed to the address generator 21. If instructed by the comparator 10 not to effect the DSV control, the selector 12 issues a signal to the address generator 21 for instructing the address generator 21 to use the first table in any case.

Using the value of the 8-bit input signal, the current state value received from the state value storing memory 13 and the signal from the selector 12 indicating as to which of the first or second tables is to be employed, the address generator 21 generates an address for acquiring the 16-bit code from the 16-bit code table ROM 23 and an address for acquiring the next state value from the next state value decision table ROM, and transmits the addresses to read-out circuit 22 and 26.

The read-out circuit 22 receives an address signal from the address generator 21 and, using the address signal, acquires the 16-bit code from the 16-bit code table ROM 23. This code is the 16-bit code output which is issued from the present modulator. The read-out circuit 22 also transmits the 16-bit code to a cumulative DSV calculating circuit 24.

The cumulative DSV calculating circuit 24 calculates, for the 16-bit code received from the read-out circuit 22 and the cumulative DSV received from the cumulative DSV storage memory 25, the value of the cumulative DSV which will prevail after using the 16-bit code, and updates the contents of the cumulative DSV storage memory 25 with the calculated value.

The read-out circuit 26 receives the address signal from the address generating circuit 21 and, using the address signal, acquires the next state value from the next state value decision table ROM 27. The read-out circuit 26 outputs the next state value to the state value storage memory 13 for updating its storage contents.

In FIG. 12, a curve A shows low-frequency components, as found by Fourier transform, of a recording waveform produced on modulating input-8-bit sample signals using the above-described signal modulating method and apparatus of the present invention.

On the other hand, a curve B in FIG. 12 shows low-frequency components of a recording waveform produced on modulating the same sample signals using a conventional EFM system and Fourier transforming the generated recording waveform, while a curve C in FIG. 12 shows low-frequency components of a recording waveform produced on modulating the same sample signals using a system corresponding to the conventional EFM system having two merging bits and Fourier transforming the generated recording waveform.

It is seen from the curves A, B and C of FIG. 12 that, with the present embodiment, the low-frequency components may be lowered to a level substantially equal to that achieved with the conventional EFM system, despite the fact that the modulation efficiency is equivalent to that of the conventional EFM system with the two merging bits, that is equal to 17/16 times that of the conventional EFM system.

The method of receiving the signal modulated with the modulating system of the present invention and demodulating the received signals to original 8-bit signal will now be explained.

With the conventional EFM system in which the 14-bit information bits are associated with the 8-bit input signal in a full one-to-one relationship, back conversion from the 14-bit information bits to the 8-bit signals can be achieved without any inconvenience.

With the embodiment of the present invention, there are occasions wherein the same 16-bit signals are allocated to different 8-bit input signals, so that the demodulator cannot effect the back conversion on simply receiving the 16-bit codes. Thus, if the demodulator of the present embodiment cannot effect back conversion on reception of a 16-bit code, it receives another succeeding symbol, that is another succeeding 16-bit code, in order to effect back conversion based upon the two symbols. The algorithm of the demodulating system of the present embodiment is shown in FIG. 13.

The sum of the demodulation algorithm shown in FIG. 13 is now explained.

The 16-bit code which can be allocated in common to two totally different values of the input 8-bit signals is necessarily restricted to the code in which the state value is changed next time to [2] or [3], as previously explained. In addition, if the state value to which one of such 16-bit codes transfers next is [2], the state value to which the other of the 16-bit codes transfers next is necessarily [3]. The table employed for the state value of [2] is made up of codes each of which has the first bit and the 13th bit equal to 0, with the MSB being the first bit, while the table employed for the state value of [3] is made up of codes each of which has one or both of the first bit and the 13th bit equal to 1, with the MSB being the first bit.

From these conditions, if the state value of the 16-bit code about to be back-converted transfers to [2], the succeeding 16-bit code has both the first bit and the 13th bit equal to 0, whereas, if the state value of the 16-bit code about to be back-converted transfers to [3], the succeeding 16-bit code has one or both the first bit and the 13th bit equal to 1. Thus, if the demodulator on reception of a 16-bit code is unable to effect the back-conversion, it receives another succeeding symbol (16-bit code) at step S25 of FIG. 13 to check the first and the 13th bits at step S26. Thus it is checked at step S27 if both of these bits are "0". If the result of judgment at step S27 is YES, that is if both of the bits are "0", the 16-bit code about to be back-converted is the code the state value of which transfers next to [2]. If the result of judgment at step S27 is NO, that is if one or both of the bits are "1", the 16-bit code about to be back-converted is the code the state value of which transfers next to [3]. This enables back-conversion to be effected uniquely.

Taking an illustrative example, this operation is explained by referring to the conversion table of FIG. 4.

In the case of the front side table T.sub.1a of the unit table T.sub.1 of the conversion table of FIG. 4, with the state value equal to 1, the 16-bit codes for 8-bit input signals "5" and "6" are both "0010000000100100". Thus the demodulator on reception of the code "0010000000100100" cannot effect the back-conversion. In such case, the demodulator reads another succeeding symbol. If the succeeding code thus read is "0010000000001001", for example, this code is a code which has been converted for the state value [3], because the 13th bit of the code is "1". If the current code is the same code, herein "0010000000100100", the state value next transfers to [2] or to [3] if the input signal value is "5" or "6", respectively, the demodulator can effect correct decoding, that is it can judge the input signal to be such signal the state value of which transfers next time to [3], that is "6".

In the flow chart of FIG. 13, the 16-bit code is entered at step S21. Reference is had to the back-conversion table at step S22. It is judged at step S23 whether decoding can be achieved uniquely. If so, the program may naturally proceed to step S24 to output the decoded 8-bit signal.

FIG. 14 shows, in a block diagram, an illustrative construction of a signal demodulator embodying the present invention.

In FIG. 14, a 16-bit input code is routed to a 1-symbol delay circuit 31 and an AND gate 34.

The 1-symbol delay circuit 321 delay the input 16-bit code by one symbol. The 16-bit code, thus delayed by one symbol, is routed to a decoding table ROM 32 having a first table for decoding ITa therein and to a decoding table ROM 33 having a second table for decoding ITb therein.

The decoding first table ROM 32, having the first table for decoding ITa therein, receives the 16-bit code to effect back-conversion to output a 8-bit signal. If the code is the 16-bit code of the type which by itself does not permit back-conversion uniquely, the demodulator after outputting the 16-bit code outputs a 8-bit signal the state value of which transfers to [2]. The 8-bit output signal value is routed to a judgement circuit 35.

Similarly to the decoding first table ROM 32, the decoding second table ROM 33, having the second table for decoding ITb therein, receives the 16-bit code and effects back-conversion to output a 8-bit signal. If the 16-bit input code is such code as permits monistical back-conversion, it outputs nothing or outputs special data. If the 16-bit code is such a code which by itself does not permit monistical back-conversion, the modulator after outputting the code outputs a 8-bit signal value the state value of which transfers to [3]. The 8-bit signal, thus outputted by the modulator, is routed to the judgement circuit 35.

The AND circuit 34 takes AND of the input 16-bit code and a 16-bit code "1000 0000 0000 1000" from a comparison value generating circuit 36, which in hexadecimal notation is "8008", in order to check the first and 13th bits of the input 16-bit code, and outputs "0" and "1" if the bits of the 16-bit AND outputs are all "0" and otherwise, respectively. Since "8008" is such a code in which only the first bit and the 13th bit are "1" and the remaining bits are "0", with the MSB being the first bit, the output of the AND gate 134 is "0" or "1" if both the first bit and the 13th bit are "0" or if one or both of the first bit and the 13th bits are "1", respectively.

The judgement circuit 35 receives the signal from the AND circuit 34 and the 8-bit signal values supplied from the decoding first table ROM 32 and the decoding second table ROM 33. First, if no 8-bit signal is routed or special data is routed from the decoding second table ROM 33, it indicates that the 16-bit input code has been decoded uniquely to the 8-bit signal, so that the judgement circuit 35 directly outputs the 8-bit signal value routed from the decoding first table ROM 32 as an output signal. If the 8-bit signal value is supplied from the decoding second table ROM 33, it indicates that the input 16-bit code has not been able to be decoded uniquely to the 8-bit signal value. Since the data fed from the decoding first table ROM 32 and the decoding second table ROM 33 have been passed through the on-symbol delay circuit 31, these signals are codes pre-read by one symbol. Thus, if the 16-bit code entering the AND gate 34 is the code converted for the state value of [2], that is if the output signal of the AND gate 34 is "0", the judgement circuit 35 outputs the 8-bit signal, received from the decoding first table ROM 32, as an output signal. On the other hand, if the 16-bit code entering the AND gate 34 is the code converted for the state value of [3], that is if the output signal of the AND gate 34 is "1", the judgement circuit 35 outputs the 8-bit signal, received from the decoding second table ROM 33, as an output signal.

The above-described embodiment of the present invention is preferably applied above all to modulation or demodulation in recording digital speech, video or data on a high-density optical disc. The following is a typical signal format in the high-density optical disc:

The present invention is not limited to the above-described embodiments. For example, the number of bits N of the input signal or the number of channel bits M of the converted output signal is not limited to N=8 or M=16, but may be set to desired arbitrary values.

With the present invention, as described above, since the duplexed portions of the conversion table are designed so that the codes of each of two associated code sets are such codes in which the DSV variants are opposite in sign and approximate to each other in absolute value, the low-frequency components of the modulated signal can be suppressed satisfactorily.

Also, with the present invention, the conversion table is constituted by the first and second sub-tables including plural code groups, and the code group to be used in the next conversion is switched by a code immediately before, so that each N-bit code can be connected without using margin bits.

In addition, with the present invention, the conversion table is constituted by two kinds of sub-tables giving opposite effects of positive and negative effects to the cumulative DSV, and modulation is carried out with the two sub-tables switched adaptively, so that low frequency components of the modulated signals may be restricted sufficiently.

In contrast to the 8-14 conversion, that is, EFM, customarily employed in Compact Discs, 8-bit input signals can be converted into 16 channel bit codes without employing merging bits. That is, in contrast to the conventional method in which a 8 bit pattern is converted into a 14-bit information bit pattern and three merging bits, thus totalling at 17 bits, the data recording density may be raised by a factor of 17/16, while the low-frequency components are suppressed.

For raising the recording density, it may be contemplated to convert the 8-bit symbol into 14 information bits plus two merging bits, thus totalling at 16 bits. In contrast to this method, the low-frequency components of the modulated signals can be suppressed sufficiently because two sorts of conversion tables affording inverse operations, that is positive and negative operations, on the cumulative DSV, are provided, and modulation is carried out whilst these two sorts of tables are changed over appropriately.

In addition, the signals modulated in accordance with the present system may be decoded by pre-reading an additional symbol and performing decoding the signal in conjunction with the additional symbol.