Method of Forming Recessed Container Cells by Wet Etching Conductive Layer and Dissimilar Layer Formed Over Conductive Layer

1. Field of the Invention

The present invention relates generally to semiconductor processing and, more particularly, to a recessed structure and a method of forming the same.

2. Description of the Related Art

Microprocessor-controlled integrated circuits are used in a wide variety of applications. Such applications include personal computers, vehicle control systems, telephone networks, and a host of consumer products. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of a software program. This software program is typically stored in a memory device coupled to the microprocessor. Not only does the microprocessor access the memory device to retrieve the program instructions, it also typically stores and retrieves data created during execution of the program in the memory device.

There are a wide variety of different memory devices available for use in microprocessor-based systems. The type of memory device chosen for a specific function within a microprocessor-based system depends largely upon what features of the memory are best suited to perform the particularly function. Most microprocessor-based systems include a dynamic random access memory (DRAM). DRAMs are volatile memories that must be continually powered in order to retain the contents. However, DRAMs are quite advantageous in that they tend to provide greater storage capability and programming cycles than non-volatile memories, such as read only memories.

A typical DRAM includes a memory array in which memory cells are arranged in rows and columns. Conductive lines, called word lines, connect the memory cells in a given row together, while perpendicular conductive lines, called digit lines, connect memory cells in a given column together. Each DRAM memory cell typically includes an access device, such as a transistor, and a storage device, such as a capacitor. Information is stored in each DRAM memory cell as the presence or absence of a charge on the storage capacitor. In response to the appropriate voltages on a selected word line and digit line, the access transistor couples the storage capacitor to the digit line so that a sense amplifier can determine whether the storage capacitor contains a charge, commonly called a logical one, or no charge, commonly called a logical zero.

To fabricate as many memory cells as possible on a single chip, the size of each memory cell should be minimized. However, the minimization of the size of a storage capacitor in a DRAM memory cell is typically limited by the amount of charge that the storage capacitor is able to retain. In fact, one of the primary concerns in DRAM fabrication is the desire to pack memory cells densely while maintaining the required capacitance levels of the storage capacitors. Simply put, it is essential that the plates of the storage capacitors be large enough to retain a charge adequate to allow the sense amplifiers to determine whether the storage capacitor is storing a logical one or a logical zero.

For years after the initial development of the basic DRAM memory cell, the storage capacitors were formed as two dimensional, or planar, capacitors. In other words, the storage capacitors were formed by two flat layers of conductive material, such as polysilicon or metal, separated by a flat dielectric layer. As the density of the memory cells increased and the size of the memory cells decreased, the size of the planar plates of the storage capacitors was clearly a limiting factor hindering further size reductions.

To reduce the size of DRAM memory cells further, and to provide storage capacitors with adequate capacitance, three dimensional capacitors were developed. One common three dimensional capacitor is referred to as a container capacitor. A container capacitor is fabricated by forming a container in a dielectric or insulative substrate. A conductive material, such as polysilicon, is deposited onto the substrate so that it lines the surface of the container. Similarly, a dielectric layer is deposited over the substrate so that it lines the polysilicon layer within the container. Finally, a second layer of conductive material, such as polysilicon, is deposited over the substrate so that it lines the dielectric layer within the container. Clearly, a container capacitor's plates have a substantially greater area than a planar capacitor that occupies the same amount of die area.

Although container capacitors improved upon planar capacitors, they are not without their problems. During the fabrication of the first polysilicon layer of a container capacitor, it is not uncommon that residual polysilicon may remain on the substrate around the edge of the container. These polysilicon residues, sometimes called floaters, are conductive and, thus, can cause short circuits, typically between adjacent container capacitors in the memory array.

The present invention is directed to one or more of the problems set forth above.

In accordance with one aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a layer of conductive material within the container form and over the upper surface of the substrate; (c) disposing a layer of dissimilar material over the layer of conductive material; (d) removing the layer of dissimilar material and the layer of conductive material from at least a portion of the upper surface of the substrate; and (e) wet etching a portion of the layer of conductive material remaining in the container form to recess the layer of conductive material below the upper surface of the container form.

In accordance with another aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a layer of conductive material within the container form and over the upper surface of the substrate; (c) disposing a layer of dissimilar material over the layer of conductive material; (d) removing the layer of dissimilar material and the layer of conductive material from the upper surface of the substrate by chemical mechanical planarization; and (e) wet etching a portion of the layer of conductive material remaining in the container form to recess the layer of conductive material below the upper surface of the container.

In accordance with still another aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a layer of conductive material within the container form and over the upper surface of the substrate; (c) disposing a layer of photoresist over the layer of conductive material; (d) removing the layer of photoresist and the layer of conductive material from the upper surface of the substrate using chemical mechanical planarization; and (e) wet etching a portion of the layer of conductive material remaining in the container form to recess the layer of conductive material below the upper surface of the container form.

In accordance with yet another aspect of the present invention, there is provided a method of forming a recessed microelectronic structure. The method comprising the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a layer of polysilicon within the container form and over the upper surface of the substrate; (c) disposing a layer of photoresist over the layer of polysilicon; (d) removing the layer of photoresist and the layer of polysilicon from the upper surface of the substrate using chemical mechanical planarization; and (e) wet etching a portion of the layer of polysilicon remaining in the container form to recess the layer of polysilicon below the upper surface of the container form.

In accordance with a further aspect of the present invention, there is provided a method of forming a capacitor in a microelectronic circuit. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a first layer of conductive material within the container form and over the upper surface of the substrate; (c) disposing a layer of photoresist over the first layer of conductive material; (d) removing the layer of photoresist and the first layer of conductive material from the upper surface of the substrate using chemical mechanical planarization; (e) wet etching a portion of the first layer of conductive material remaining in the container to recess the first layer of conductive material below the upper surface of the container form; (f) removing the layer of photoresist remaining in the container form; (g) disposing a layer of dielectric material over the recessed first layer of conductive material and over the upper surface of the substrate; and (h) disposing a second layer of conductive material over the layer of dielectric material.

In accordance with an even further aspect of the present invention, there is provided a method of forming a capacitor in a microelectronic circuit. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a first layer of conductive material within the container form and over the upper surface of the substrate; (c) disposing a layer of photoresist over the first layer of conductive material; (d) removing at least a portion of the layer of photoresist and at least a portion of the first layer of conductive material from the upper surface of the substrate to expose at least a portion of the upper surface of the substrate adjacent the container form; (e) wet etching a portion of the first layer of conductive material remaining in the container form to recess the first layer of conductive material below the upper surface of the container form; (f) removing the layer of photoresist remaining in the container form; (g) disposing a layer of dielectric material over the recessed first layer of conductive material and over the upper surface of the substrate; and (h) disposing a second layer of conductive material over the layer of dielectric material.

In accordance with a still further aspect of the present invention, there is provided a method of forming a capacitor in a microelectronic circuit. The method includes the steps of: (a) forming a container form in a substrate, the substrate having an upper surface; (b) disposing a first layer of polysilicon within the container form and over the upper surface of the substrate; (c) disposing a layer of photoresist over the first layer of polysilicon; (d) removing the layer of photoresist and the first layer of polysilicon from the upper surface of the substrate using chemical mechanical planarization; (e) wet etching a portion of the first layer of polysilicon remaining in the container form to recess the first layer of polysilicon below the upper surface of the container form; (f) removing the layer of photoresist remaining in the container form; (g) disposing a layer of dielectric material over the recessed first layer of polysilicon and over the upper surface of the substrate; and (h) disposing a second layer of polysilicon over the layer of dielectric material.

The foregoing and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 illustrates a semiconductor memory;

FIG. 2 illustrates a portion of a memory array of FIG. 1;

FIG. 3 illustrates an electric schematic diagram of an exemplary memory cell in the array of FIG. 2;

FIG. 4 illustrates a cross-sectional view of a container capacitor in accordance with the present invention;

FIG. 5 illustrates a substrate having a container form formed therein;

FIG. 6 illustrates a layer of polysilicon and photoresist formed over the substrate and container form of FIG. 5;

FIG. 7 illustrates the structure of FIG. 6 after a chemical-mechanical planarization process; and

FIG. 8 illustrates the structure of FIG. 7 after an etching process and subsequent resist removal.

Specific embodiments of memory elements and methods of making such memory elements are described below as they might be implemented for use in semiconductor memory circuits. In the interest of clarity, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation (as in any semiconductor engineering project), numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of semiconductor design and fabrication for those of ordinary skill having the benefit of this disclosure. Furthermore, the fabrication of a single device is described with the understanding that many similar devices may be fabricated simultaneously.

Turning now to the drawings, and referring initially to FIG. 1, a memory device is illustrated and generally designated by a reference numeral 10. The memory device 10 is an integrated circuit memory that is advantageously formed on a semiconductor substrate 12. The memory device 10 includes a memory matrix or array 14 that includes a plurality of memory cells for storing data, as described below. The memory matrix 14 is coupled to periphery circuitry 16 by the plurality of control lines 18. The periphery circuitry 16 may include circuitry for addressing the memory cells contained within the memory matrix 14, along with circuitry for storing data in and retrieving data from the memory cells. The periphery circuitry 16 may also include other circuitry used for controlling or otherwise ensuring the proper functioning of the memory device 10.

A more detailed description of the memory matrix 14 is illustrated in FIG. 2. As can be seen, the memory matrix 14 includes a plurality of memory cells 20 that are arranged in generally perpendicular rows and columns. The memory cells 20 in each row are coupled together by a respective word line 22, and the memory cells 20 in each column are coupled together by a respective digit line 24. Specifically, each memory cell 20 includes a word line node 26 that is coupled to a respective word line 22, and each memory cell 20 includes a digit line node 28 that is coupled to a respective digit line 24. The conductive word lines 22 and digit lines 24 are collectively referred to as address lines. These address lines may be electrically coupled to the periphery circuitry 16 so that each of the memory cells 20 can be accessed for storage and retrieval of information.

FIG. 3 illustrates an exemplary memory cell 20 that may be used in the memory matrix 14. The memory cell 20 includes a memory element 32 that is coupled to an access device 30. In this embodiment, the memory element 32 is illustrated as a storage capacitor, and the access device 30 is illustrated as a MOSFET transistor. The base of the transistor 30 is coupled to the word line 22 to form the word line node 26, and the source of the transistor 30 is coupled to the bit line 24 to form the bit line node 28. One plate 38 of the capacitor 32 is coupled to the drain of the transistor 30, and the other plate 42 of the capacitor 32 is coupled to V.sub.cc, which is usually circuit ground.

The general operation of the memory device 10 as illustrated in FIGS. 1-3 is well known in the art, so such operation will not be described herein. However, the structure and fabrication of the storage capacitor 32 is unique. As illustrated in FIG. 4, a storage capacitor 32 is formed in a substrate 50. The substrate 50 is typically an exposed surface of an in-process wafer. In the disclosed embodiment, the substrate 50 surrounding the storage capacitor 32 may be comprised of a generally dielectric material, such as silicon oxide or boron phosphorous silicon glass (BPSG). It should be understood that a suitable access device 30 may be placed laterally or vertically with respect to the storage capacitor 32 and that such connections are not illustrated here.

As illustrated in FIG. 4, the storage capacitor 32 is formed in a container form 52. The storage capacitor 32 includes a first layer or layers of conductive material 54 and a second layer or layers of conductive material 56 which form the lower and upper plates of the capacitor 32. The first conductive layer 54 is separated from the second conductive layer 56 by a layer of dielectric material 58, which is disposed therebetween. As mentioned in reference to FIG. 3, one of the plates of the storage capacitor 32 will be coupled to V.sub.cc (not necessarily directly) while the opposite plate will be coupled to the access device 30.

The fabrication of the storage capacitor 32, as illustrated in FIG. 4, will now be described in reference to FIGS. 5-8. As illustrated in FIG. 5, the container form 52 is formed in the substrate 50. The container form 52 may be formed by any suitable method, such as by using standard photolithographic and etching methods. Once the container form 52 has been formed, a layer of conductive material 60, which will become the first layer of conductive material 54, is deposited on the substrate 50 and in the container form 52, as illustrated in FIG. 6. The conductive material 60 may be any suitable conductive material, such as polysilicon or metal. Suitable metals may include, for example, ruthenium and/or platinum. Also, as alluded to previously, the layer of conductive material 60 may actually be formed as a multi-layer coating of conductive materials, such as a first layer of smooth polysilicon and a second layer of roughened or hemispherically-grained polysilicon. Advantageously, the conductive layer 60 is a blanket polysilicon deposition that coats the sides and bottoms of the container form 52 with polysilicon.

Once the conductive layer 60 has been deposited, a layer of photoresist 62 is deposited over the conductive layer 60. The layer of photoresist 62 may be spun onto the conductive layer 60 and then baked to remove the solvent. It should be noticed that due to differential volume shrinkage, the thickness of the photoresist layer 62 over the container form 52 is typically less than the thickness of the photoresist layer 62 over areas that do not have containers. It should further be noted that the layer 62 need not be photosensitive. Indeed, an organic compound or resin having suitable properties may also be utilized.

To remove the layer of photoresist 62 and the conductive layer 60 of polysilicon from the top surface 64 of the substrate 50, while leaving the photoresist and polysilicon in the container form 52, a chemical-mechanical planarization (CMP) process is performed. Accordingly, it should also be noted that one property of the type of material used to form the layer 62 that should be considered is the material's integrity through the chosen CMP and etching processes. Advantageously, the top surface 64 of the substrate 50 acts as a CMP stop to determine when the top surface 64 of the substrate 50 is clear of the conductive material 60 and the photoresist 62. Instead of using the top surface 64 of the substrate 50 as a CMP stop, a timed CMP process may also be suitable. The CMP process produces the structure illustrated in FIG. 7. In addition, prior to this CMP process, any conductive material that may have been deposited on the backside of the substrate 12 may be removed by a suitable wet etch to prevent this conductive material from being dislodged during subsequent processing steps and being redeposited in undesirable locations.

After the CMP process, a suitable wet isotropic etchant is then used to remove any remaining conductive material 60 from the top surface 64 of the substrate 50 and, also, to recess the polysilicon within the container form 52. Certain specific examples of this etching process are discussed below. The use of a chemical etchant, as opposed to a plasma etch, is advantageous because it removes undesirable conductive material from the edges and backside of the substrate as well. The amount that the conductive material within the container form 52 is recessed should be carefully controlled because capacitance will be lost as the plate 54 becomes smaller. Advantageously, the amount that the conductive material within the container form 52 is recessed may be controlled by the amount of time the etchant is used using known etch rates and/or by controlling the selectivity that the etchant exhibits between the photoresist and the conductive material. The recessed first conductive layer 54 within the container form 52 reduces the chances of residual conductive material remaining between containers, and, thus, reduces the chances of short circuits caused by such floaters.

This etching process may be performed using various etching chemistries. As a first example, if polysilicon is used as the conductive material 60, the etching process may begin with a dilute HF etchant to decap the polysilicon, followed by a dilute tetramethylammoniumhydroxide (TMAH) etchant to etch the polysilicon relative to the photoresist. As another example, the decap step may be performed to minimize oxide erosion by using as an etchant TMAH buffered with dilute HF. As still another example, the etching of the polysilicon may be controlled to maximize the selectivity between the photoresist and the polysilicon using a TMAH etchant having a concentration in the range of 1% to 3.2% at a temperature in the range of 22 to 35 degrees Celsius and, advantageously, a concentration of 2.25% at a temperature of 30 degrees Celsius. It should be noted that other etchants, such as NH.sub.4 OH, tetraethylammoniumhydroxide (TEAH), KOH, or an NH.sub.4 OH/H.sub.2 O.sub.2 mix, may also be suitable to use instead of TMAH. It should also be noted that a decap etch is not used when a metal is used as the conductive material 60 and that HCI, or other suitable etchants, may be used to perform the recessing step.

Once the first conductive layer 54 has been recessed within the container form 52, the remaining photoresist 62 is then removed from the container to produce the structure illustrated in FIG. 8. Subsequently, as illustrated in FIG. 4, the layer of dielectric 58 and the second conductive layer 56 is deposited over the substrate 50 and into the container form 52 to cover the lower plate 54.

While the invention may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.