Sample and Hold Circuit and Method With Common Mode Differential Signal Feedback for Converting Single-Ended Signals to Differential Signals

1. Field of the Invention

The present invention relates to sample and hold (S/H) circuits and their corresponding techniques for sampling analog signals and holding the sampled values, and in particular, to such circuits and techniques for sampling single-ended signals and holding such sampled signals as differential signals.

2. Description of the Related Art

Fully differential circuit architectures are widely used for many applications such as switched capacitor filters and analog-to-digital (A/D) converters. Important benefits of such architectures include increased noise immunity and power supply rejection, as well as automatic compensation for second order non-linearities such as capacitor voltage coefficients. However, "real world" applications involve signals which are more often single-ended. Hence, a single-ended-to-differential signal converter is usually used as an input stage.

Referring to FIG. 1, a typical conventional single-ended-to-differential signal converter used as the input stage for a S/H circuit in an A/D converter using complementary metal oxide semiconductor (CMOS) technology uses switched capacitor input and output circuits controlled by non-overlapping clock signals .phi.1 and .phi.2 to control MOS switches S1-S7 and S8-S10, respectively. During the sample phase of operation, i.e., during assertion of clock signal .phi.1, switches S1-S7 are closed and the input signal VINp-VINn is sampled on input capacitors C1 and C2. The input terminal corresponding to the "negative" input signal phase VINn is connected to the reference potential of the actual single-ended input signal VINp, which is usually circuit ground potential. This sample clock phase .phi.1 is also used to bias the inputs INp, INn of the operational amplifier (op-amp) A1 to a common mode input voltage VCOMin through switches S3, S4 and S5, as well as to set the common mode output voltage (additional circuitry not shown). Switches S6 and S7 are used during the sample phase to pre-charge output feedback capacitors C3 and C4 to a known voltage. If the input voltage is unipolar, the pre-charged values are set by two different reference voltages, VREFp, VREFn which introduce offset voltages and the inputs INp, INn of the op-amp A1 which are equal to half of the full input voltage scale.

During the hold phase of operation, i.e., during assertion of clock signal phase .phi.2, switches S8-S10 are closed. This causes the electrical charges accumulated by the input capacitors C1, C2 to be redistributed between them and the output feedback capacitors C3, C4, thereby maintaining a quasi-null differential voltage at the inputs INp, INn of the op-amp A1.

Referring to FIG. 1A, the phase relationships among the clock signals .phi.1, .phi.1', .phi.1", .phi.2 are shown. Clock phases .phi.1' and .phi.1" are successively delayed, overlapping versions of clock signal phase .phi.1, and are all non-overlapping with respect to clock signal phase .phi.2.

Referring to FIG. 2, a typical conventional design for the op-amp A1 has a cascode architecture, as shown. For a given level of power dissipation, this architecture has a large transconductance which is necessary for fast settling in high speed circuits. Also, because of non-dominant poles at very high frequencies, the op-amp A1 does not require separate compensation capacitors which consume circuit (i.e., silicon) area and increase power dissipation. However, such a telescopic circuit configuration has disadvantages in that the output voltage range is reduced and the input common mode voltage has a small range. If this results in an input common mode voltage which is too small, the biasing transistor M7 is pushed into its linear operating region and the bias current is thereby reduced. If the input common mode voltage is too large, the input gain transistors enter their linear operating regions which results in a reduced transconductance and output impedance, thereby degrading the open loop circuit gain. Further, optimization of the output linear operating range, as established by the bias voltages for the cascode devices M3-M6, reduces the acceptable input common mode voltage range.

Another problem with the circuit of FIG. 1 is the variation of the input common mode voltage during the hold phase of operation. Ideally, redistribution of the charges accumulated by sampling capacitors C1 and C2 when switch S8 is closed and nodes INp and INn have virtually the same potential (i.e., the input common mode) would mean that the common node AB settles to a voltage potential which is equal to the arithmetic average of the input sample voltages VINp, VINn, thereby leaving the input common mode voltage of the op-amp A1 unchanged.

Referring to FIGS. 3A and 3B, the equations which describe this charge balancing can be written using the equivalent circuits for the sample phase of operation (FIG. 3A) and the hold phase of operation (FIG. 3B) as follows:

where:

Q.sub.AB =total charge stored in nodes A and B during sample

Qin.sub.p & Qin.sub.n =charges stored in nodes In.sub.p and In.sub.n, respectively, during sample

Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4 & Q.sub.5 =charge injection from MOS switches S1, S2, S3, S4 and S5, respectively, at turn-off (end of the sample phase)

Q.sub.8 =charge absorbed from node AB by switch S.sub.8 at turn-on (beginning of the hold phase)

Vcom.sub.in =common mode input voltage during sample phase

Vcom.sub.in '=common mode input voltage during hold phase

V.sub.AB =node AB voltage during hold phase

Vref.sub.p & Vref.sub.n ="positive" and "negative" reference voltages, respectively, centered on the output common mode

Cd.sub.1 '& Cd.sub.2 '=voltage dependent junction capacitances associated with switches S1 and S2, respectively, during the sample phase

Cd.sub.1 "& Cd.sub.2 "=voltage dependent junction capacitances associated with switches S1 and S2, respectively, during the hold phase

Solving Equations (1)-(6) with the additional condition of

imposed by the output common mode feedback yields the input common mode voltage during the hold phase of operation as follows: ##EQU1##

High speed circuits require very large sampling switches (switches S1-S5 in the circuit of FIG. 1) in order to reduced the RC time constant of the sampling circuit and reduce the signal drop across the input dependent switch resistance. Such large switches when implemented in MOS technology have large associated capacitances Cd which are on the same order of magnitude as the sampling and hold capacitors C1-C4, and have large channel charges. Simulations have demonstrated an input common mode voltage variation of 300 millivolts or more for sampling capacitors C1, C2 of two picofarads and NMOS sampling switches S1, S2 with width and length dimensions of 400 microns and 0.8 microns, respectively. Such a voltage variation is unacceptable for most designs and will lead to a collapse of the op-amp input pair.

The circuit non-linearities are dominated by the second harmonic which is not cancelled as it would be in fully differential architectures. The signal-dependent charge injection Q1 into the common node AB by sampling switch S1 is attenuated by the symmetric arrangement of the capacitors C1-C4 only to the degree by which the input capacitors C1, C2 and the output capacitors C3, C4 are matched to one another. A first order error in the differential output voltage can be computed using equations (1)-(7) above, and has a signal-dependent term of the following form: ##EQU2## where: .DELTA.V.sub.out =first-order error in differential output voltage V.sub.out

.DELTA.V.sub.com =signal dependent variation of input common mode voltage V.sub.com

.epsilon..sub.2 =relative mismatch between capacitors C.sub.1 and C.sub.2

.epsilon..sub.4 =relative mismatch between capacitors C.sub.3 and C.sub.4

Other error terms in the differential output signal can be compensated by various calibration and/or correction techniques, but the signal-dependent term, as set forth above in Equation (13), primarily determines the degree of non-linear distortion.

Accordingly, it would be desirable to have a sample and hold circuit architecture for converting single-ended signals to differential signals while avoiding the above-discussed problems.

An apparatus and method in accordance with the present invention provides a common mode feedback technique for sample and hold circuits which convert single-ended signals to differential signals. An error amplifier is used in a separate feedback loop to establish and maintain the input common mode voltage during the hold phase of operation. Such a technique balances charge injection from large switches in high speed circuits and reduces non-linear distortion due to signal-dependent charge injection and the non-linear (i.e., voltage-dependent) junction capacitance of the input switches. Such a technique improves the linear range of the sample and hold circuit and reduces distortions due to signal-dependent charge injection and non-linear charge redistribution.

In accordance with one embodiment of the present invention, a sample and hold (S/H) circuit with common mode differential signal feedback for converting a single-ended signal to a differential signal includes an input switched capacitor circuit and a feedback circuit. The input switched capacitor circuit is configured to receive a plurality of sample and hold control signals, an input reference signal and a feedback reference signal and in accordance therewith receive and sample a single-ended input signal and in accordance therewith provide a differential input signal. The feedback circuit, coupled to the input switched capacitor circuit, is configured to receive the hold control signal, the input reference signal and the differential input signal and in accordance therewith provide the feedback reference signal.

In accordance with another embodiment of the present invention, a sample and hold (S/H) circuit with common mode differential signal feedback for converting a single-ended signal to a differential signal includes a sampling circuit and a feedback circuit. The sampling circuit is configured to receive a plurality of control signals and in accordance therewith: receive and sample a single-ended input signal during a sample phase and receive a variable feedback voltage during a hold phase and in accordance therewith provide a sampled signal; and convert the sampled signal to an intermediate differential signal in accordance with the variable feedback voltage during the hold phase, wherein the intermediate differential signal includes a common mode input voltage. The feedback circuit, coupled to the sampling circuit, is configured to monitor the common mode input voltage and a common mode reference voltage and in accordance therewith provide the variable feedback voltage, wherein the variable feedback voltage is adjusted to cause the common mode input voltage to remain substantially constant in relation to the common mode reference voltage.

In accordance with still another embodiment of the present invention, a sample and hold (S/H) method of converting a single-ended signal to a differential signal while maintaining a substantially constant common mode voltage includes the steps of: receiving a plurality of sample and hold control signals, an input reference signal and a feedback reference signal and in accordance therewith receiving and sampling a single-ended input signal and in accordance therewith generating a differential input signal; and receiving the hold control signal, the input reference signal and the differential input signal and in accordance therewith generating the feedback reference signal.

In accordance with yet another embodiment of the present invention, a sample and hold (S/H) method of converting a single-ended signal to a differential signal while maintaining a substantially constant common mode voltage includes the steps of: receiving and sampling a single-ended input signal during a sample phase to generate a sampled signal; receiving a variable feedback voltage during a hold phase; converting the sampled signal to an intermediate differential signal in accordance with the variable feedback voltage during the hold phase, wherein the intermediate differential signal includes a common mode input voltage; and monitoring the common mode input voltage and a common mode reference voltage and in accordance therewith adjusting the variable feedback voltage, wherein the adjusting of the variable feedback voltage causes the common mode input voltage to remain substantially constant in relation to the common mode reference voltage.

These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.

FIG. 1 is a schematic diagram of a conventional sample and hold circuit for converting single-ended signals to differential signals.

FIG. 1A is a signal timing diagram for the clock signal phases used in the circuits of FIGS. 1, 3A, 4, 6, and 7.

FIG. 2 is a schematic diagram of a conventional operational amplifier design for use in the circuit of FIG. 1.

FIGS. 3A and 3B are the equivalent circuits for the sample and hold phases of operation, respectively, for the circuit of FIG. 1.

FIG. 4 is a schematic diagram of a sample and hold circuit in accordance with one embodiment of the present invention.

FIG. 5 is a schematic diagram of the error amplifier in the circuit of FIG. 4.

FIG. 6 is a schematic diagram of the equivalent circuit for the input portion of the circuit of FIG. 4 during the sample phase of operation.

FIG. 7 is a schematic diagram of a sample and hold circuit in accordance with another embodiment of the present invention.

Referring to FIG. 4, a sample and hold circuit in accordance with one embodiment of the present invention includes a feedback loop formed by a three-input error amplifier A2 and two switch circuits S8', S8" connected to the sample and hold circuit of FIG. 1. The error amplifier A2 monitors the input nodes INp, INn of the op-amp A1 and compares their voltages to the common mode voltage VCOMin. The output of the error amplifier A2 is connected to the common node AB during the hold phase of operation (i.e., during assertion of clock signal phase .phi.2) through switches S8, S8' and S8". This feedback loop maintains the input common mode voltage at the input terminals INp, INn of the op-amp A1 at the common mode voltage reference VCOMin during the hold phase of operation.

This technique provides two major advantages. First, the input common mode voltage at the input terminals INp, INn of the op-amp A1 is guaranteed to be substantially maintained at the common mode voltage reference VCOMin, thereby ensuring that the main op-amp A1 does not collapse due to large charge injection at its input nodes INp, INn and non-linear charge redistribution in the junction capacitances CD1, CD2. Additionally, by setting the input common mode voltage to a known value, in this case the reference voltage VCOMin, the output linear range of the op-amp A1 can be optimized. The second advantage is that by driving the common node AB during the hold phase of operation, the effects of the signal-dependent charge injection Q1 and the non-linear charge redistribution in the junction capacitances Cd1, Cd2 are cancelled. Since the input common mode voltage is established by this secondary feedback loop, all signal-dependent errors in the differential output signal are significantly reduced.

Referring to FIG. 5, the feedback amplifier A2 can be implemented as shown. The inputs INp, INn, VCOMin are connected to matched NMOS M1-M3 and PMOS M6-M8 transistors in common source configurations. If both signal inputs INp, INn are lower in voltage than the reference VCOMin, the drain current of transistor M3 increases and, due to the operation of the current mirror formed by transistors M4 and M5, the output terminal D is driven to a high potential. Complementary operations are performed by corresponding input devices M6-M8 and current mirror devices M9 and M10. Hence, if both inputs INp, INn are higher in potential than the reference VCOMin, then the drain current of transistor M8 increases and the output terminal D is pulled low by the operation of the current mirror formed by transistors M9 and M10. If one of the two inputs INp, INn is above and one is below the reference VCOMin, the error amplifier A2 is inactive, i.e., terminal D remains at its present potential. One example of this last condition is where the input common mode voltage is correct but a large differential voltage appears at the inputs INp, INn during the slewing of the op-amp A1 at the beginning of a hold phase of operation.

The error amplifier A2 does not have critical settling requirements and can be implemented with relatively small devices and low power dissipation. Any non-settling error at the common node AB will be further attenuated by the matching of the sampling C1, C2 and feedback C3, C4 capacitors. However, the error amplifier A2 should be powerful enough to bring the input common mode voltage very close to the reference VCOMin as quickly as possible so as to allow maximum settling time for the op-amp A1.

Referring to FIG. 6, the charging and discharging currents of the sampling capacitors C1, C2 flow through switches S3-S5 into the node for the reference voltage VCOMin. Hence, any signal-dependent variations in the reference voltage VCOMin will generate further signal-dependent differential charge injection (from switches S3-S5) into the input nodes INp, INn, as well as a large non-linear distortion in the overall operation of the sample and hold circuit. However, providing a low impedance buffer for the reference voltage VCOMin is undesirable due to the necessary circuit area and power dissipation.

Referring to FIG. 7, a sample and hold circuit in accordance with another embodiment of the present invention addresses this problem by the introduction of additional switches S11, S12, S13, S14, connected substantially as shown. During the sample phase of operation, switches S11 and S12 are closed and the input signal is sampled on capacitors C1 and C2. In this case, the return path for the signal is circuit ground rather than the common mode reference VCOMin line. This avoids the need for a buffer circuit for the reference voltage VCOMin. During the hold mode of operation, switches S11 and S12 are open and switches S13 and S14 are closed. The error amplifier A2 is then used to set the correct common mode voltage at the inputs INp, INn of the op-amp A1.

This ground sampling technique requires the use of the input common mode error amplifier A2. The common mode voltage during the sampling phase at nodes E and F is circuit ground potential, while during the hold phase of operation the common mode voltage at nodes E and F becomes equal to the common mode reference voltage VCOMin. Hence, with the use of the error amplifier A2, this ground sampling technique has the same advantages as that of FIG. 4, as discussed above.

Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodiments, it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.