Method of Making a Dielectric for an Integrated Circuit

This invention relates to methods of integrated circuit fabrication.

As integrated circuit geometries shrink, those concerned with the design of such circuits are forced to use increasingly thinner gate dielectrics. For example, it is anticipated, that 0.25 micron (and below) MOSFET technologies will require a gate dielectric with a thickness of 4 nanometers or less. Such thin dielectrics exhibit comparatively high defect densities, lower breakdown and wearout behavior. Furthermore, such thin dielectrics do not present an adequate barrier to boron penetration from overlying boron doped polysilicon into the substrate. In addition, MOSFETs fabricated with such thin dielectrics frequently exhibit high leakage current at low voltage and lower interface resistance to current stress.

Those concerned with the development of integrated circuit technology have consistently sought better dielectrics and methods for their fabrication.

Illustratively, the present invention includes:

forming a dielectric upon a substrate by;

forming a first dielectric layer in the presence of nitrogen;

forming a second layer in the absence of all but trace amounts of nitrogen; and

forming a third layer in the presence of nitrogen.

FIGS. 1, 2, and 3 are partial cross-sectional views of an integrated circuit showing an illustrative embodiment of the present invention; and

FIG. 4 is a graph depicting silicon-nitrogen bond concentration as a function of dielectric thickness in an illustrative embodiment of the present invention; and

FIG. 5 is a graph depicting processing temperatures as a function of time according to an illustrative embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a substrate which may typically, silicon, doped silicon, epitaxial silicon, etc. After field oxide formation, (not shown) a thin layer of silicon dioxide 13 is grown in N.sub.2 O, NO or NO.sub.2. The thickness is, illustratively, 0.5-2 nanometers. Illustratively, the process for forming layer 13 may include growth in oxygen or steam for a period of approximately 1-30 minutes at a temperature of 650.degree. C.-1000.degree. C., ideally at 850.degree. C.

Turning to FIG. 2, the structure of FIG. 1 is then subjected to an oxygen or steam ambient to grow another 0.5-3 nanometers. There is no significant amount of nitrogen present in the reaction chamber for the second growth phase. The second growth phase produces a second layer of dielectric denoted by reference numeral 15. The growth process which forms dielectric 15 also pushes previously-formed nitrogen incorporated dielectric 13 upwards. Previously-formed dielectric 13 is denoted by reference numeral 131 in FIG. 2.

Turning to FIG. 3, an annealing step is performed in N.sub.2 O, NO or NO.sub.2. The annealing step forms a dielectric 17 having a thickness between 0.5 and 2 nanometers. The process of forming dielectric 17 pushes the previously-formed layers upward. Previously-formed layer 15 is denoted in FIG. 3 as layer 115 and previously-formed layer 13 is denoted in FIG. 3 as layer 1311.

Layers 1311, 115, and 17, taken together form gate dielectric 19. Subsequent processing may, for example, include the deposition of a conductive material, such as polysilicon over dielectric 19, the subsequent patterning of the conductive material, such as polysilicon, formation of source and drain, and deposition in patterning of alternating layers of interlevel dielectric and conductive runners.

The total thickness of composite gate dielectric 19 and the relative thicknesses of dielectric sublayers may be adjusted by varying the oxidation time, temperature, and gas partial pressure for individual components, 1311, 115, and 17.

This process may be easily integrated into modern integrated circuit manufacturing processes very cheaply because it does not increase the number of manufacturing steps. The process is illustrated in FIG. 5.

In FIG. 5, reference numeral 100 represents the furnace ideal temperature which may be illustratively, approximately 700.degree. C. Reference numeral 101 represents the oxidation processing temperature which may be illustratively 650.degree. C.-1000.degree. C., preferably 850.degree. C. Reference numeral 102 represents a temperature ramp of approximately 5.degree. C. per minute.+-.1.degree. C. per minute. Reference numeral 103 represents the oxidation process, utilizing nitrogen which forms layer 13. Reference numeral 104 represents the oxidation process without the presence of nitrogen which forms layer 15. Reference numeral 105 represents the oxidation process in the presence of nitrogen which forms layer 17. Reference numeral 106 represents furnace ramp down, illustratively at approximately 3.degree. C..+-.1.degree. C. per minute.

In layer 17, many silicon-hydrogen bonds which were typically found in dielectrics formed by other processes are absent as silicon-nitrogen bonds replaces them. Instead, layer 17 exhibits a relatively high density of silicon-nitrogen bonds which are typically stronger than silicon-hydrogen bonds and Si--O bonds, thereby producing a more reliable dielectric-crystalline silicon interface. The presence of nitrogen in layer 1311 provides a barrier against oxygen diffusion. This barrier tends to slow the oxidation rate of layer 17, thereby providing better uniformity for layers 115 and 17. Such uniformity is particularly important and increasingly difficult to achieve with thinner dielectrics and larger (8" and 12") diameter wafers. In addition, the presence of nitrogen in layer 1311 and layer 17 tends to block boron diffusion from overlying boron doped polysilicon layers. Furthermore, the presence of nitrogen in layer 113 makes layer 113 more resistant to the plasma etching process which is used to define the subsequently formed polysilicon layer. Such resistance is important because the thickness of the composite 19 is very low and is easily etched through. Presence of nitrogen in the bottom sublayer 17 near the silicon-dielectric interface improves breakdown, wearout and the resistance to current stress of the composite 3-layer dielectric (19).

FIG. 4 is a graph depicting silicon-nitrogen bond concentration as a function of the individual layers depicted in FIG. 3. It will be noticed that silicon-nitrogen bond concentration is high in layers 1311 and 17, while very low in layer 115.