Integrated Circuit Fault Testing System Based on Power Spectrum Analysis of Power Supply Current

The present invention relates to systems for detecting troubles in CMOS integrated circuits and, more particularly, to methods and systems for detecting troubles in CMOS integrated circuits on the basis of power supply current information.

Such CMOS integrated circuit trouble detection methods and systems have heretofore been used for quickly checking the normal operation of CMOS integrated circuits.

In a CMOS integrated circuit, only a very slight leak current flows as the supply current except for transient currents in transistor switching operations. This character of the CMOS integrated circuit can be utilized to detect troubles therein. A trouble is detected on the basis of a large current, which is not the transistor switching current or the leak current.

FIG. 11 shows a prior art example of the trouble detection system. In this case, a supply voltage is supplied from a power supply 5' to a CMOS integrated circuit 4' under test to check for a trouble in the circuit from the magnitude of the supply current, which is measured in an ammeter 6'.

FIG. 12 shows another prior art example of the trouble detection system. In this case, a tester 1 applies a test pattern from a test pattern storage unit 3 to a CMOS integrated circuit 4 under test, and the supply current at this time is detected in a current detection unit 6. A checking unit 7 checks for a trouble in the circuit 4 from the result of the detection or observation.

FIG. 13 shows a method of current measurement carried out in an IC checking system for checking electric characteristics of ICs (integrated circuits) proposed in Japanese Laid-Open Patent Publication No. 2-302677. In this method, current is measured in a timed relation to a generated test pattern. Specifically, for accurate current measurement a test pattern 102 which is outputted from a test pattern generator, is utilized to generate a gate signal for controlling the measurement of the supply current 101 in synchronism to the test pattern.

In the CMOS integrated circuit trouble detection system as shown in FIG. 11, which is based on the current measurement, the supply current in the CMOS integrated circuit is measured in the inoperative state thereof. Therefore, it is not always possible to measure a supply current in the case of a trouble.

The case of FIG. 12 is the real-time measurement of the supply current by operating the CMOS integrated circuit using the tester. However, it takes a time to detect current. That is, the real-time supply current measurement substantially cannot be made depending on the CMOS integrated circuit under test; it cannot be made with, for instance, high frequency operation devices or the like.

The prior art method of current measurement is applied to a system of determining AC characteristics of the supply current in a CMOS integrated circuit in the operative state thereof. In the system, the CMOS integrated circuit is tested by applying test patterns thereto and measuring the supply current therein for each applied test pattern. The accurate measurement of the supply current, however, requires a high speed current measuring system, and it is difficult in a short period of time.

FIG. 14 illustrates conceivable measurement of a quiescent current 105 caused as the supply current which is not a transistor switching current in a CMOS integrated circuit. In this case, however, it is necessary to separate the quiescent current from the supply current 106 as the transistor switching current, but it is difficult to do so.

The present invention was made in view of the above problems, and it has an object of providing a method and a system for detecting troubles in a CMOS integrated circuit by making a short-time check for a quiescent current other than any transistor switching current, which is caused by the application of each test pattern to the CMOS integrated circuit.

According to one aspect of the present invention, there is provided a system of detecting troubles in CMOS integrated circuits by observing any quiescent current other than transistor switching current in a supply current caused in a CMOS integrated circuit when made operative by test pattern application comprising: means for repeatedly applying a test pattern to the CMOS integrated circuit under test; current detection means for detecting the supply current supplied to the CMOS integrated circuit; and means for deriving a power spectrum of the supply current detected by the current detection means; the CMOS integrated circuit under test being checked for a trouble based on the magnitude power in the supply current power spectrum for a predetermined frequency band.

According to another aspect of the present invention, there is provided a system of detecting troubles in CMOS integrated circuits by observing any quiescent current other than transistor switching current in a supply current caused in a CMOS integrated circuit when made operative by test pattern application, comprising: a tester for applying the test pattern to the CMOS integrated circuit under test; a test pattern storing means in which data of the test pattern is stored; a program storing means in which a program for controlling the driving of the tester is stored; a power supply unit for supplying power to the CMOS integrated circuit under test; a current detection unit for detecting the supply current supplied from the power supply unit to the CMOS integrated circuit under test; an amplifier for amplifying the detection signal from the current detection unit; a power spectrum analyzing means for deriving power of the amplified detection signal for each frequency band; and a checking means for detecting the magnitude of the power of the amplified detection signal after filtering for each frequency band and checking the CMOS integrated circuit for a trouble based on the magnitude of the detected power in a predetermined frequency band.

Other objects and features will be clarified from the following description with reference to attached drawings.

FIG. 1 is a block diagram showing a system according to a first embodiment of the present invention;

FIG. 2 is a flow chart illustrating an inspection routine according to the present invention;

FIGS. 3(A)-3(C) are drawings representing relations between for the repetitive test pattern application and the supply current of CMOS integrated circuit for explaining a principle of the present invention;

FIG. 4 is a block showing a different embodiment of the present invention;

FIG. 5 is drawings representing relations between for the repetitive test pattern application and the supply current of CMOS integrated circuit;

FIG. 6 is a block diagram showing a further embodiment of the present invention;

FIG. 7 shows the current detection unit 6a using a current detection resistor R;

FIG. 8 is a block diagram showing a yet further embodiment of the present invention;

FIG. 9 is a block diagram showing a yet another embodiment of the present invention;

FIG. 10 shows a yet another embodiment of the present invention;

FIG. 11 shows a prior art example of the trouble detection system;

FIG. 12 shows another prior art example of the trouble detection system;

FIG. 13 shows a method of current measurement carried out in an IC checking system for checking electric characteristics of ICs; and

FIG. 14 illustrates conceivable measurement of a quiescent current 105 caused as the supply current which is not a transistor switching current in a CMOS integrated circuit.

FIG. 3(A) illustrates repetitive application of a test pattern 200 (applied signal 204) to a CMOS integrated circuit under test. The test pattern 200 consists of N sub-patterns, and its application requires NT seconds (T being its cycle period corresponding to the test cycle).

When the CMOS integrated circuit is operated by applying the applied signal 204 thereto, a normal supply current 201 is caused to flow through it, as shown in FIG. 3(B), when it is normal. This normal supply current is constituted by the sole transistor switching current, and the quiescent current level is ignorable.

When the CMOS integrated circuit under test has a trouble (for instance, a short-circuit), an abnormal supply current 202 is caused as shown in FIG. 3(C). This abnormal supply current 202 is an abnormal quiescent current 203 as VDD supply current quiescent Iddq in specific sub-patterns.

When the test pattern 200 is repeatedly applied to the CMOS integrated circuit under test in a cycle period of (T+T.sub.0) (T.sub.0 being a time required for the system set-up, etc.), it is seen that the normal supply current 201 has a large peak at a frequency of 1/T ›Hz!, while the abnormal supply current 202 has peaks at 1/T and 1/(NT+T.sub.0) ›Hz!. That is, the two currents are different as to whether they have a peak at 1/( NT+T.sub.0) ›Hz!.

It is thus possible to detect a quiescent current caused only in specific sub-patterns and thus determine a trouble in the CMOS integrated circuit under test by detecting the peak at 1/(NT+T.sub.0) ›Hz!.

This function can be realized without need of any high operation speed measuring instrument but with only a simple filtering mechanism.

The signal at 1/(NT+T.sub.0) ›Hz! may be dealt with in the case of a device which is high in the operation speed (i.e., short in T) as well. Since N is usually several thousands to several hundreds of thousands, the frequency of 1/(NT+T.sub.0) ›Hz! is not high and permits measurement without use of any special system.

Preferred embodiments will be described hereinunder with reference to the drawings. FIG. 1 is a block diagram showing a system according to a first embodiment of the present invention.

Referring to FIG. 1, a CMOS integrated circuit 4 under test is electrically connected to a tester 1. A program storage unit 2 and a test pattern storage unit 3 are connected to the tester 1. A program for controlling the driving of the tester 1 (hereinafter referred to as "test program") is stored in the program storage unit 2, and test pattern data for testing the CMOS integrated circuit 4 under test is stored in the pattern storage unit 3. A power supply unit 5 is connected through a current detection unit 6 to the CMOS integrated circuit 4 for supplying power thereto. The tester 1 applies a test pattern, which is stored in the pattern storage unit 3, from a pin electronic card driver (not shown) to a corresponding terminal (or input pin) of the CMOS integrated circuit 4 with a test cycle, a repetition period and a signal waveform format as set by the program stored in the program storage unit 2 and under control of the program stored in the program storage unit 2. The power supply unit 5 may be as program controlled power supply unit which is provided in the tester 1.

The current detection unit 6 detects the supply current supplied from the power supply unit 5, and its detection signal is coupled through an amplifier 7 and a power spectrum analyzing unit 8 to a checking unit 9. The amplifier 7 amplifies the detection signal, and the power spectrum analyzing unit 8 determines the power of the amplified detection signal from the amplifier 7 for each frequency band. The checking unit 9 observes the determined signal power and checks for a trouble in the CMOS integrated circuit 4 under test on the basis of the magnitude of the observed signal power.

A method of inspection using the system according to a first embodiment of the present invention will now be described. FIG. 2 is a flow chart illustrating an inspection routine according to the present invention. First, the test pattern is repeatedly applied from the tester to the CMOS integrated circuit under test (step 301). The cycle period of the sub-patterns of the test pattern is T seconds, and with N sub-patterns the repetition period of the test pattern is (NT+T.sub.0).

The detection or observed signal is then generated through detection of the supply current flowing in the CMOS integrated circuit under test (step 302). Power spectrum data of the supply current is then generated through filtering of the detection signal (step 303). A power spectrum at 1/(NT+T.sub.0) ›Hz! is then obtained from the power spectrum data, and the CMOS integrated circuit under test is checked for any trouble from the magnitude of the power spectrum thus obtained (step 304).

The operation of the system according to the first embodiment of the present invention shown in FIG. 1 will now be described. As described above, the program for driving the tester 1 is stored in the program storage unit 2, and the program pattern for testing the CMOS integrated circuit 4 under test is stored in the pattern storage unit 3. The tester 1 tests the CMOS integrated circuit 4 in accordance with the program and using the test pattern stored in the test pattern storage unit 3.

It is programmed that the test pattern is applied repeatedly to the CMOS integrated circuit 4. The test pattern, which consists of N sub-patterns each having a cycle period (or test period) of T seconds, requires NT seconds for its single application.

The test pattern is repeatedly applied to the CMOS integrated circuit 4 under test for every (NT+T.sub.0) seconds. The CMOS integrated circuit 4 is supplied with the power from the power supply unit 5, and the supply current is monitored by the current detection unit 6. The amplifier 7 amplifies the signal from the current detection unit 6, and the power spectrum analyzing unit 8 determines the power of the power spectrum for each frequency band. The checking unit 9 detects the magnitude of each frequency band power, and when the detected magnitude exceeds a reference value, it determines that a trouble is present in the CMOS integrated circuit.

Where the test pattern consists of N sub-patterns each with a cycle period of T seconds and its repetition period of the application to the CMOS integrated circuit 4 is (NT+T.sub.0) seconds, the checking unit 9 detects the magnitude of power in the neighborhood of 1/(NT+T.sub.0) ›Hz!.

FIG. 4 is a block showing a different embodiment of the present invention. In this embodiment, the time interval T.sub.0 between adjacent test pattern periods NT is set to 0 seconds, as shown in FIG. 5. That is, a test pattern 200 consisting of N sub-patterns each with a cycle period of T seconds is repeatedly applied to the CMOS integral circuit 4 under test in a cycle period of NT seconds. The filter (i.e., power spectrum analyzing unit 8) selectively passes only a particular band, for instance the neighborhood of 1/NT ›Hz! in the detection signal from the current detection unit 6. Since the test pattern is repeatedly and continuously applied to the CMOS integrated circuit 4 under test in the repetition cycle period of NT seconds, the supply current power spectrum contains no power spectrum due to T.sub.0, and it is thus possible to permit more accurate inspection of the CMOS integrated circuit 4.

FIG. 6 is a block diagram showing a further embodiment of the present invention. In this embodiment, the current detection unit 6a uses a current detection resistor R as shown in FIG. 7. By using the current detection resistor R it is possible to easily convert the current signal to the voltage signal.

FIG. 8 is a block diagram showing a yet further embodiment of the present invention. In this embodiment, a filter 10 is used in lieu of the power spectrum analyzing unit 8 shown in FIG. 1. The filter 10 can pass a particular frequency part (signal) of the supply current data. The checking unit 9 checks for a trouble in the CMOS integrated circuit under test by detecting the power magnitude of the detection signal as the supply current data passed through the filter 10. With the filter 10 it is possible to detect the power magnitude of the supply current in a specific frequency band with a simple construction.

FIG. 9 is a block diagram showing a yet another embodiment of the present invention. In this embodiment, a band-pass filter 10a is used in place of the filter 10 in the preceding embodiment. Where the test pattern consists of N sub-patterns each with a cycle period of T seconds and is repeatedly applied to the CMOS integrated circuit 4 under test in a repetition cycle period of (NT+T.sub.0) seconds, the band-pass filter 10a passes only the neighborhood of 1/(NT+T.sub.0) ›Hz!. When an abnormal quiescent pattern is caused in specific sub-patterns due to a trouble in the CMOS integrated circuit 4 under test, the supply current power spectrum has a peak at 1/(NT+T.sub.0) ›Hz!, and this peak can be readily separated by the band-pass filter 10a.

FIG. 10 shows a yet another embodiment of the present invention. This embodiment uses a low-pass filter 10b in lieu of the filter 10 noted above. Where the test pattern consists of N sub-patterns each with a cycle period of T seconds and is repeatedly applied to the CMOS integrated circuit 4 in a repetition cycle period of (NT+T.sub.0) seconds, the low-pass filter 10b passes only a band below the neighborhood of 1/(NT+T.sub.0) ›Hz!. When an abnormal quiescent current is caused in specific sub-patterns due to a trouble in the CMOS integrated circuit 4 under test, the supply current power spectrum has a peak at 1/(NT+T.sub.0) ›Hz!, while no meaningful peak is present below 1/(NT+T.sub.0) ›Hz!. The low-pass filter 10b thus can readily separate the peak, while the system construction can be simplified.

As has been described in the foregoing, the system for detecting CMOS integrated circuit troubles according to the present invention can discriminate a quiescent signal, which is caused in a CMOS integrated circuit under test due to a trouble therein when a test pattern is applied thereto and is usually difficult to directly observe it, from the transistor switching current, that is, can check for such a quiescent current, through the supply current power spectrum analysis, because such quiescent current is caused in specific sub-patterns of the test pattern in every repetition application cycle thereof.

In addition, according to the present invention even in a test of a high operation speed device the discrimination of the quiescent current from the transistor switching current, can be very readily obtained by taking the length of the test pattern into considerations, and can be realized with a simple construction.

Changes in construction will occur to those skilled in the art and various apparently different modifications and embodiments may be made without departing from the scope of the present invention. The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting.