Data Communication Circuit for Controlling Data Communication Between Redundant Power Supplies and Peripheral Devices

The present invention relates to data busses, and more particularly, but not by way of limitation, to a data communication bus architecture wherein at least a portion of the data communication bus can be isolated to permit uninterrupted data communication between devices connected to the isolated portion of the data communication bus.

The I.sup.2 C (inter-integrated circuit) bus is a bi-directional two wire bus that provides low speed direct data communication between I.sup.2 C compatible devices on a circuit board. One advantage of the I.sup.2 C bus is that it eliminates many interfacing difficulties associated with other types of data buses. Generally, I.sup.2 C buses utilize a master/slave configuration, such that the master devices can communicate to all the other devices, while the slave devices generally respond to the data received over the I.sup.2 C bus. Some I.sup.2 C bus configurations also allow for a multi-master configuration and utilize collision detection and arbitration to prevent data corruption. Generally, the number of peripheral devices that can be connected to the I.sup.2 C bus is limited by the capacitance value of the bus.

The early versions of the I.sup.2 C bus did not have any set specifications for manufacturers to follow when designing I/O buffers to interface therewith. In fact, in many of the early versions of the I.sup.2 C bus, if a device connected to the I.sup.2 C bus did not have any power applied to the device, the configuration of I/O pins on the device would shunt the bus to ground. This would disable the I.sup.2 C bus preventing communication between all of the devices connected thereto. For example, many devices used electrostatic discharge (ESD) diodes on the I/O pins to protect the device from electrostatic discharge when powered down. In these devices, when power is lost to the device, the ESD diodes will load the bus and pull it to ground because the diodes are there to shunt static discharges to ground. This in turn, disables the I.sup.2 C bus and prevents any data communication between the other peripheral devices on the bus. Among other things, this creates a problem when bus communication is needed between two or more devices when most of the devices on the I.sup.2 C data bus are powered down. Such is the case, for example, when a system has redundant power supplies that use I.sup.2 C to coordinate operation. During the start-up of a system with redundant power supplies, the redundant power supplies must communicate therebetween to establish the proper operating parameters of the power supplies. If the I.sup.2 C data bus is disabled, communication over the bus can not occur, thereby preventing the power supplies from operating properly.

Therefore, it is highly desirable to have a device or bus architecture that permits data communication between at least two devices, when power has been disabled from at least one of the remaining peripheral devices connected to the data bus.

The present invention overcomes the above identified problems as well as other shortcomings and deficiencies of existing technologies by providing a data communication bus architecture wherein at least a portion of the data communication bus can be isolated to permit uninterrupted data communication over the bus between devices connected to the isolated portion of the data communication bus.

The present invention further provides a computer system utilizing redundant power supplies and an I.sup.2 C data bus architecture, with the redundant power supplies and multiple peripheral devices connected to the I.sup.2 C data bus. The I.sup.2 C data bus is configured so that the power supplies can be connected to the I.sup.2 C bus and isolated from the peripheral devices during power-up of the computer system so that the power supplies can communicate over the I.sup.2 C bus, and further the power supplies can be connected to the other peripheral devices over the I.sup.2 C data bus when the computer system is powered up.

A more complete understanding of the present invention may be had by reference to the following Detailed Description and appended claims when taken in conjunction with the accompanying Drawings wherein:

FIG. 1 is a schematic block diagram of a computer system utilizing the present invention; and

FIG. 2 is a schematic diagram of an exemplary embodiment of a circuit in accordance with the principles of the present invention.

With reference to FIG. 1, there is shown a schematic block diagram of an exemplary embodiment of a computer system 110 illustrating the utilization of the present invention. The purpose of this block diagrams is to illustrate, among other things, the features of the present invention and the basic principles of operation thereof. This block diagram is not necessarily intended to schematically represent particular modules of circuitry or control paths.

As depicted, computer system 110 includes a computer 112, power supplies 114 and 116, an inter-integrated circuit (I.sup.2 C) bus 118, peripheral devices 120, 122 and 124, a MOSFET switching device 126, termination 128, a +5 volt auxiliary supply 130, a +5 volt input 132, and a resistive device 134. Power supplies 114 and 116, along with peripheral devices 120, 122 and 124 are each connected to and communicate over I.sup.2 C bus 118, with power supplies 114 and 116 separated from devices 120, 122 and 124 by MOSFET 126. MOSFET 126 is further connected to resistive element 134 and power input 132 and is used to isolate power supplies 114 and 116 on the I.sup.2 C bus 118 from devices 120, 122 and 124 when in the open state. Although good results have been achieved using a MOSFET switching device, it is contemplated to be within the scope of this invention that other types of switching mechanisms could be utilized, such as a relay or the like.

Still referring to FIG. 1, as illustrated in this exemplary embodiment, power supplies 114 and 116 are configured as redundant power supplies for computer system 110, and supply power to devices 120, 122, and 124, and input 132. In operation, power supplies 114 and 116 communicate together over I.sup.2 C bus 118. One of power supplies 114 and 116 will operate in the master mode, with the other operating in the slave mode. This permits the power supply operating in the master mode to communicate with the power supply operating in the slave mode such that the proper output can be set, with both power supplies sharing the load to the system in a selected manner. After the power-up of computer system 110 and during the operation thereof, the power supply operating in the master mode monitors the operating voltages within the computer system for needed power output adjustment and communicates through the I.sup.2 C bus to adjust the slave mode power supply to maintain acceptable voltage levels within selected limits.

Still referring to FIG. 1, the general operation of computer system 110 will now be described. Power input 130 is connected to a +5 volt auxiliary power, which is supplied by power supply 114 or power supply 116 and is always present for the proper termination of I.sup.2 C bus 118. Power supplies 114 and 116 generally supply power to the computer system 110, including devices 120, 122 and 124, but are separated therefrom by MOSFET switching device 126. MOSFET switching device 126, when in the "open" state, disconnects power supplies 114 and 116 from devices 120, 122 and 124, but still permits the power supplies to communicate over the isolated portion of the I.sup.2 C data bus. When either of power supplies 114 and 116 are powered up, power input 132 will receive power therefrom, "closing" MOSFET switching device 126. When MOSFET switching device 126 is closed, the I.sup.2 C data bus 118 is connected between power supplies 114 and 116 and peripheral devices 120, 122 and 124 and is transparent thereto providing a continuous connection. As described above, when MOSFET switching device 126 is open, such as during power-up, the I.sup.2 C data bus 118 is disconnected between power supplies 114 and 116 and peripheral devices 120, 122 and 124. However, power supplies 114 and 116 can still communicate over I.sup.2 C bus 118.

Referring now to FIG. 2, there is shown a more detailed schematic of portion 210 of the computer system 110 shown in FIG. 1. As depicted, a switching device 212 is connected to power input 214, resister 216 and transistor 218. Elements 220, 222, 224 and 226 represent the I.sup.2 C bus, with clock line PS.sub.-- SCL 220 and data line PS.sub.-- SDA 222 for connection to the power supplies 114 and 116, and clock line DEVICE.sub.-- SCL 224 and data line DEVICE.sub.-- SDA 226 for connection to peripheral devices 120, 122 and 124. Lines 220 and 222 are selectively connected to lines 224 and 226 with switching device 212. Power input 228 is connected to resisters 230 and 232 and transistor 218. Switching device 212 includes output enable pins labeled lOE.sub.--, 2OE.sub.--, 3OE.sub.--, and 4OE.sub.--, and are for receiving the signals to connect or disconnect switching device 212.

Still referring to FIG. 2, and as further depicted, power input 214 is connected to the +5 volt auxiliary supply and power input 228 is connected to receive power from either power supply 114 or 116, as described hereinabove. The voltage applied at input 228, through the open divider network (resistors 230 and 232) controls transistor 218, such that transistor 218 turns on and off at selected voltage levels, which enables or disables switching device 212. The parameters of resistors 230 and 232 determine the voltage level for enabling and disabling switching device 212.

In general operation, when power supplies 114 and 116 are being powered-up, and the voltage at input 228 is below a selected level, switching device 212 is opened or disabled such that I.sup.2 C lines 220 and 222 are disconnected from I.sup.2 C lines 224 and 226, permitting communication only between power supplies 114 and 116 over I.sup.2 C bus 118. When the voltage at input 228 reaches the selected level, switching device 212 is closed or enabled, connecting I.sup.2 C lines 220 and 224 with I.sup.2 C lines 224 and 226 respectively. As described hereinabove, when switching device 212 is closed and the lines of I.sup.2 C data bus 118 are connected, switching device 212 is transparent during the operation of I.sup.2 C data bus 118.

Those skilled in the art can realize that the teachings of the present invention as described hereinabove provide a data communication bus architecture wherein at least a portion of the data communication bus can be isolated to permit uninterrupted data communication between devices connected to the isolated portion of the data communication bus.

It can be further appreciated that the present invention provides an I.sup.2 C data bus architecture with redundant power supplies and multiple devices connected to the I.sup.2 C data bus. The power supplies are connected to the I.sup.2 C bus such that a switch can isolate the power supplies from the other devices during power-up so that the power supplies can communicate over the I.sup.2 C bus.

Although a preferred embodiment of the present invention has been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiment disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.