Method for Forming a Diffusion Region in a Semiconductor Device

This invention relates specifically to the formation of diffusion regions in semiconductor devices.

As circuitry density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One recent technique finding greater application in achieving reduced transistor size is to form field effect transistors with thin films, which are commonly referred to as "thin film transistor" (TFT) technology.

With thin film transistors, a substantially constant thickness film of material (typically polysilicon) is first provided. A central channel region of the thin film is masked while opposing adjacent source/drain regions are doped with appropriate P or N type conductivity enhancing impurities. A gate insulator and gate is provided either above or below the thin film channel region, thus providing a field effect transistor having active and channel regions formed entirely within a thin film as opposed to a bulk substrate. In the manufacturing of thin film transistors, field implants are provided beneath field oxide regions and are normally of the same conductivity type as the bulk/well type of the substrate for providing greater dopant concentration between the thin film transistors. This provides greater electrical isolation between adjacent transistors. Such higher dopant and implant regions are designed to be positioned immediately beneath the isolation field oxide regions. In the construction of these thin field transistors, such implants are normally immediately provided after field oxide formation and sacrificial oxide growth. However, conventional thermal processing of the semiconductor device subsequent to the formation of the implant regions has the effect of facilitating the diffusion of the field implant region downwardly and laterally inward. The lateral inward diffusion is undesirable as it adversely impacts the concentration of other types of materials which form the source and drain regions for the field effect transistors. The resulting lateral diffusion further results in dopant diffusion into active channel regions therefore affecting the body effects (of narrow width devices), threshold voltage instability, and higher junction leakage.

The formation of buried contact diffusion regions for use with thin film transistors have problems similar to that discussed above, that is, with buried contacts, the out diffusion of ions into the field oxide region degrades its isolation characteristics. In particular, the prior art practice, particularly in the fabrication of SRAM devices normally provides such buried contact regions into the bulk substrate prior to the provision of the thin film transistor layer. As will be recognized, subsequent thermal processing of the semiconductor wafer has the effect of diffusing the buried contact region downwardly and laterally inwardly thereby producing deleterious results. Still further, bulk well formation is normally provided after the deposit of a gate oxide and conductive gate layer. Subsequent thermal processing of the semiconductor device also results in the diffusion of the bulk well.

It would be desirable to improve upon the methods of forming diffusion type regions and bulk wells for devices such as thin film transistors, SRAMS, DRAMS, resistors in SRAMS, and similar assemblies. Such is the subject matter of the present invention.

FIG. 1 is a view of a semiconductor wafer fragment taken at one processing step in accordance with the present invention.

FIG. 2 is a view of the FIG. 1 wafer fragment shown at a processing step subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 2 wafer fragment shown at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that shown in FIG. 3.

FIG. 5 is a view of the FIG. 4 wafer fragment shown at a processing step subsequent to that shown by FIG. 4.

FIG. 6 is a view of the FIG. 5 wafer fragment shown at a processing step subsequent to that shown by FIG. 5.

FIG. 7 is a view of the FIG. 6 wafer fragment shown at a processing step subsequent to that shown by FIG. 6.

FIG. 8 is a view of a semiconductor wafer fragment, of a second form of the invention, taken at one processing step in accordance with the present invention.

FIG. 9 is a view of the FIG. 8 wafer fragment shown at a processing step subsequent to that shown by FIG. 8.

FIG. 10 is a view of the FIG. 9 wafer fragment shown at a processing step subsequent to that shown by FIG. 9.

FIG. 11 is a view of the FIG. 10 wafer fragment shown at a processing step subsequent to that shown by FIG. 10.

FIG. 12 is a view of the FIG. 11 wafer fragment shown at a processing step subsequent to that shown by FIG. 11.

FIG. 13 is a view of the FIG. 12 wafer fragment shown at a processing step subsequent to that shown by FIG. 12.

FIG. 14 is a view of the FIG. 13 wafer fragment shown at a processing step subsequent to that shown by FIG. 13.

FIG. 15 is a view of a semiconductor wafer fragment of a third alternative form of the invention taken at one processing step in accordance with the present invention.

FIG. 16 is a view of the FIG. 15 wafer fragment shown at a processing step subsequent to that shown in FIG. 15.

FIG. 17 is a view of the FIG. 16 wafer fragment shown at a processing step subsequent to that shown by FIG. 16.

FIG. 18 is a view of the FIG. 17 wafer fragment shown at a processing step subsequent to that shown by FIG. 17.

FIG. 19 is a view of the FIG. 18 wafer fragment shown at a processing step subsequent to that shown by FIG. 18.

FIG. 20 is a view of FIG. 17 wafer taken at a processing step subsequent to that shown in FIG. 17.

FIG. 21 is a view of the FIG. 20 wafer at a processing step subsequent to that shown in FIG. 20.

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).

Referring now to FIGS. 1 through 7, and initially to FIG. 1, there illustrated is a semiconductor wafer fragment in process and which is indicated generally by reference to numeral 10. In the context of this document, the term "semiconductor wafer fragment" or semiconductive substrate is defined to mean any construction comprising semiconductive material, including, but not limited to bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including but not limited to, the semiconductive substrates described above. This wafer fragment may be one portion of a static random access memory (SRAM cell or other electronic component). Such is provided in a bulk semiconductor substrate 11. The wafer fragment 10 is provided with field oxide regions 12. These field oxide regions are formed by conventional means. An active area 14 is defined adjacent the field oxide region 12.

Referring now to FIG. 2, a gate dielectric layer 16 is formed atop the bulk substrate 11 and in covering relation relative to the field oxide region 12, and the active area 14. This gate dielectric layer 16 preferably is silicon dioxide which is formed to a thickness of approximately 300 Angstroms.

Referring now to FIG. 3, a thin film transistor layer 18 is formed atop the gate dielectric layer 16 to a given thickness. The thin film transistor layer 18 would be subsequently patterned and doped with an impurity to provide source and drain regions 19a and 19b respectively.

Referring now to FIG. 4, a masking layer 20 is formed atop the thin film transistor layer and patterned in a given fashion, as shown. Thereafter, an ion discharge 22 is provided through the unmasked regions and through the thin film transistor layer 18 and underlying gate dielectric layer 16 to form a buried contact region 24 therebeneath. This first masking layer is then removed

Referring now to FIG. 5, a second masking layer 26 is formed and which provides a masked area, and an unmasked area, which is substantially aligned with the buried contact region 24.

As shown in FIG. 6, the method further includes etching the thin film transistor layer 18 and underlying gate dielectric layer 16 to expose the buried contact region 24 therebeneath.

Referring now to FIG. 7, a second electrically conductive layer 28 is formed atop the thin film transistor layer 18. This second electrically conductive layer 28 electrically couples the thin film transistor layer 18 and the buried contact diffusion region 24.

A second aspect of the present invention relates to the formation of a field implant region, and which facilitates the electrical isolation of a field effect transistor from adjoining electrical devices.

Referring now to FIG. 8, a semiconductor wafer 40 in process is shown. The semiconductor wafer is formed in a bulk substrate 41. As seen in FIG. 8, field oxide regions 42 are formed in a conventional fashion in the bulk substrate 41. The field oxide regions 42 define an active area region 44 adjacent thereto.

Referring now to FIG. 9, a gate dielectric layer 46 is formed atop the exposed active area 44 and adjacent field oxide regions 42. The gate dielectric layer is similar to that discussed previously.

Referring now to FIG. 10, a conductive gate layer 48 is formed atop the gate dielectric layer and adjacent field oxide regions 42.

Referring now to FIG. 11, a masking layer 50, comprising photoresist, is formed over the active area 44 while leaving the adjacent field oxide regions 42 unmasked.

As seen in FIG. 12 after the formation of the masking layer 50 ion implanting 52 is conducted. The ion implanting 52 comprises forming a dopant impurity through the conductive gate layer 48 and field oxide regions 42 and into the underlying substrate 41 to form a field implant region 54. The field implant region 54 facilitates the electrical isolation of one electrical device from an adjoining electrical device.

Referring now to FIG. 13, the masking layer 50 is shown removed.

As shown in FIG. 14, the method further comprises patterning and etching the conductive gate layer 48 to form a transistor gate within the active area region 44. Electrically conductive source and drain regions are provided operatively adjacent the gate 48.

A third aspect of the invention is best seen by reference to FIGS. 15 through 19, respectively.

Referring now to FIG. 15, the semiconductor wafer in process is shown generally by the numeral 70. The wafer is formed in a bulk substrate 71 in a traditional fashion. As further shown in FIG. 15, field oxide regions 72 are formed, and an active area region 74 is formed adjacent thereto.

Referring now to FIG. 16, a gate dielectric layer 76 is formed atop the semiconductor substrate 70, the gate dielectric layer 76 is similar to that discussed earlier in this application.

Referring now to FIG. 17, the semiconductor wafer 70 is shown in a step subsequent to that shown in FIG. 16, and wherein a conductive gate layer 78 is formed atop the gate dielectric layer 76.

Referring now to FIG. 18, conditions are provided effective to pattern and etch the conductive gate layer 78, as illustrated.

Referring now to FIG. 19, and subsequent to the patterning and etching of the gate layer 78, an ion discharge 80 is provided to ion implant through the field oxide region 72, gate dielectric layer 76, and conductive gate layer 78 to form a background dopant well 80.

Referring now to FIG. 20, the semiconductor wafer 70 is shown at a step subsequent to that shown in FIG. 17. In particular, in FIG. 20, after forming the conductive gate layer 78 an ion discharge 80 is provided to implant through the field oxide region 72, gate dielectric layer 76 and conductive gate layer 78 to form the background dopant well 82 as shown.

Referring now to FIG. 21, the gate dielectric layer 78 is shown in a step subsequent to FIG. 20 where it is patterned, and etched, as illustrated.

The method of the present invention is believed to be readily apparent and is briefly summarized at this point.

In accordance with one aspect of the present invention a semiconductor processing method for forming a diffusion region includes:

providing a semiconductor substrate 10;

forming a first layer of material 18 over the semiconductor substrate 10 which is electrically conductive, or subsequently rendered electrically conductive; and

after forming the first layer, ion implanting 22 a conductivity modifying impurity through the first layer 18 and into the semiconductive substrate 10 to form a diffusion region 24 therein.

In accordance with another aspect of the invention, a method for forming a field effect transistor includes:

providing a substrate 40;

providing a field oxide region 42 and active area region 44 on the substrate 10;

forming a gate dielectric layer 46 atop the substrate 10 and within the active area region 44; and

after forming the gate dielectric layer, ion implanting a dopant impurity 52 through the field oxide region 42 and into the underlying substrate to form a field implant 54 beneath the field oxide region 42 for facilitating electrical isolation of the field effect transistor from adjacent electrical devices.

Still another aspect of the present invention relates to a method for forming a field effect transistor which includes:

providing a substrate 40;

forming a field oxide region 42 on the substrate 40 and defining an exposed active area 44 adjacent thereto;

forming a gate dielectric layer 46 atop the exposed active area 44;

forming a conductive gate layer 48 over the gate dielectric layer 46 and adjacent field oxide region 42;

forming a masking layer 50 over the active area 44 while leaving the field oxide region 42 unmasked;

after forming the conductive gate layer 48, and with the masking layer 50 in place, ion implanting a dopant impurity 52 through the conductive gate layer 48 and field oxide region 42 and into the underlying substrate 40 to form a field implant 54 beneath the field oxide region 42 for facilitating electrical isolation of the field effect transistor from adjoining electrical devices;

patterning and etching the gate layer 48 to form a transistor gate within the active area region 44; and

forming electrically conductive source and drain regions operatively adjacent the gate.

Still another aspect of the present invention relates to a method for forming a thin film transistor which includes:

providing a substrate 10;

forming a thin film transistor layer 18 atop the substrate 10; and

after forming the thin film transistor layer 18, ion implanting 22 a dopant impurity through the thin film transistor layer 18 and into the underlying substrate t o provide a buried contact diffusion region 24 beneath the thin film transistor layer 18.

Still a further aspect of the present invention relates to a semiconductor processing method for forming a background dopant well 80 relative to a semiconductor material substrate 70, and which includes:

providing a semiconductor substrate 70;

22 forming a field oxide region 72 on the semiconductor substrate 70;

forming a gate dielectric layer 76 atop the semiconductor substrate 70;

forming a conductive gate layer 78 atop the gate dielectric layer 76; and

after the step of forming the conductive gate layer, ion implanting 80 through the field oxide region 72, gate dielectric layer 76 and conductive gate layer 78 to form a background dopant well 80.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown a nd described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the Doctrine of Equivalents.