Method for Testing a Memory Chip, Divided Into Cell Arrays, During Ongoing Operation of a Computer While Maintaining Real-Time Conditions

1. A method for testing a memory chip, divided into cell arrays, during ongoing operation of a computer while maintaining real-time conditions, the memory chip being divided into row areas and column areas in accordance with a matrix, each of said areas having at least one cell array and a storage cell row determining an individual row of a row area and a storage cell column determining an individual column of a column area, comprising the steps of: a) selecting a first row area; b) copying, if a content of the first row area is allocated to an application program, said content into another free, second row area and modifying addressing of the application program for the second row area; c) carrying out a Franklin test for each cell array of the first row area; d) selecting two cell arrays from the row area; e) carrying out a Nair test on any storage cell row of the two selected cell arrays; f) reporting steps d) to e) with another pair of cell arrays until all possible combinations of two cell arrays have been run through; g) carrying out a Nair test on any storage cell column, restricted to the selected, first row area; h) carrying out steps b) to g) for all row areas of the memory chip; i) selecting a pair of row areas; j) copying, if at least one of the row areas is allocated to an application program, a content of the at least one row area into at least one free row area and modifying addressing of the application program for each copied-over row area; k) selecting in each case any one storage cell column from the two selected row areas; l) carrying out a Nair test on the two selected storage cell columns; m) carrying out steps j) to l) with a different pair of row areas until all possible combinations of two row areas have been run through.

2. The method according to claim 1, wherein no interrupts are permitted during execution of the Nair test.

3. The method according to claim 1, wherein a plurality of memory chips of an entire memory are tested simultaneously by parallel testing, in which common data is written into all the memory chips and wherein the common data is read out of all the memory chips.

4. The method according to claim 1, wherein for classifying faults in computer systems, which have EDC mechanisms, in which occurrence of a fault is determined by interrogating an EDC controller, and wherein a fault is classified, assuming the fault can be reproduced, by distinction between stuck-at faults, if a storage cell has a different value than a value directly written into the storage cell, connection faults, if steps e) to g) or l) to m) discover a fault, and pattern-sensitive faults, if step c) discovers a fault.

5. A method for testing a memory chip, divided into cell arrays, during ongoing operation of a computer while maintaining real-time conditions, the memory chip being divided into row areas and column areas in accordance with a matrix, each of said areas having at least one cell array and a storage cell row determining an individual row of a row area and a storage cell column determining an individual column of a column area, comprising the steps of: a) selecting a first row area; b) copying, if a content of the first row area is allocated to an application program, said content into another free, second row area and modifying addressing of the application program for the second row area; c) carrying out a Franklin test for each cell array of the first row area; d) selecting two cell arrays from the row area; e) carrying out a Nair test on any storage cell row of the two selected cell arrays; f) reporting steps d) to e) with another pair of cell arrays until all possible combinations of two cell arrays have been run through; g) carrying out a Nair test, without interruption, on any storage cell column, restricted to the selected, first row area; h) carrying out steps b) to g) for all row areas of the memory chip; i) selecting a pair of row areas; j) copying, if at least one of the row areas is allocated to an application program, a content of the at least one row area into at least one free row area and modifying addressing of the application program for each copied-over row area; k) selecting in each case any one storage cell column from the two selected row areas; l) carrying out a Nair test on the two selected storage cell columns; m) carrying out steps j) to l) with a different pair of row areas until all possible combinations of two row areas have been run through.

6. The method according to claim 5, wherein a plurality of memory chips of an entire memory are tested simultaneously by parallel testing, in which common data is written into all the memory chips and wherein the common data is read out of all the memory chips.

7. The method according to claim 5, wherein for classifying faults in computer systems, which have EDC mechanisms, in which occurrence of a fault is determined by interrogating an EDC controller, and wherein a fault is classified, assuming the fault can be reproduced, by distinction between stuck-at faults, if a storage cell has a different value than a value directly written into the storage cell, connection faults, if steps e) to g) or l) to m) discover a fault, and pattern-sensitive faults, if step c) discovers a fault.

8. A method for testing a memory chip, divided into cell arrays, during ongoing operation of a computer while maintaining real-time conditions, the memory chip being divided into row areas and column areas in accordance with a matrix, each of said areas having at least one cell array and a storage cell row determining an individual row of a row area and a storage cell column determining an individual column of a column area, comprising the steps of: a) selecting a first row area; b) copying, if a content of the first row area is allocated to an application program, said content into another free, second row area and modifying addressing of the application program for the second row area; c) carrying out a Franklin test for each cell array of the first row area; d) selecting two cell arrays from the row area; e) carrying out a Nair test on any storage cell row of the two selected cell arrays; f) reporting steps d) to e) with another pair of cell arrays until all possible combinations of two cell arrays have been run through; g) carrying out a Nair test on any storage cell column, restricted to the selected, first row area; h) carrying out steps b) to g) for all row areas of the memory chip; i) selecting a pair of row areas; j) copying, if at least one of the row areas is allocated to an application program, a content of the at least one row area into at least one free row area and modifying addressing of the application program for each copied-over row area; k) selecting in each case any one storage cell column from the two selected row areas; l) carrying out a Nair test on the two selected storage cell columns; m) carrying out steps j) to l) with a different pair of row areas until all possible combinations of two row areas have been run through; classifying a fault, assuming the fault can be reproduced, by distinction between stuck-at faults, if a storage cell has a different value than a value directly written into the storage cell, connection faults, if steps e) to g) or l) to m) discover a fault, and pattern-sensitive faults, if step c) discovers a fault.

9. The method according to claim 8, wherein no interrupts are permitted during execution of the Nair test.

10. The method according to claim 8, wherein a plurality of memory chips of an entire memory are tested simultaneously by parallel testing, in which common data is written into all the memory chips and wherein the common data is read out of all the memory chips.