Gamma Correction Circuit Using Analog Multiplier

The present invention relates to a gamma correction circuit using an analog multiplier, and more particularly, to a gamma correction circuit for overcoming electro-optic nonlinearity associated with liquid crystal material to maintain a linear output while driving a liquid crystal display panel.

Recently, improved LCD picture quality has been required to take advantage of advanced video signal input/output technology and a variety of new video media. Suitable liquid crystal materials for these applications exhibit a gray scale over a range of applied voltages. That is, for a given liquid crystal material, transmittance increases generally with increasing voltage. The relationship between applied voltage and transmittance, however, is not linear. For example, as shown in FIG. 1, which is a typical electrooptic characteristic of an LCD, transmittance as a function of applied voltage is not linear around V.sub.10 and V.sub.90. The curve shown in FIG. 1 is commonly referred to as the "gamma", and circuitry used to compensate for these nonlinearities is known as "gamma correction" circuitry.

Gamma correction circuits linearly correct the transmissivity characteristic of a liquid crystal over predetermined nonlinear portion of the characteristic. Typically the gamma correction circuit increases the amplification rate over the nonlinear portions in a chrominance demodulation circuit.

Conventional gamma correction circuits, however, are limited to correcting in either a digital or analog mode. They are also very complicated to make and they frequently generate an unstable video signal output.

FIG. 2 is a block diagram of an LCD driver having the conventional gamma correction circuit, which controls the amplification rate of the nonlinear portions in the chrominance demodulation block when a video signal is applied to an LCD pixel. The video signal, having a controlled amplification rate, is supplied to a gamma compensator circuit 20, which, in turn, feeds a gamma compensated value to the Y-driver 22 of the LCD array 24. A controller outputs horizontal and vertical sync signals to the X and Y drivers, 22 and 28, respectively. The X and Y drivers then supply appropriate signals to drive the LCD array 24.

FIG. 3 is a block diagram illustrating a conventional digital gamma correction circuit in greater detail. As shown in FIG. 3, the gamma correction circuit receives a video signal and sets a proper gamma value for correction. FIG. 4 is a graph showing the input/output characteristic of the conventional digital gamma correction circuit. The conventional gamma correction techniques will now be discussed with reference to FIGS. 3 and 4.

As seen in FIG. 3, A/D converter 30 receives an analog input video signal and converts it into a digital signal. This digital signal is detected in a data detector 31. A gamma setting circuit 32 establishes a gamma value for the detected signal by retrieving a predetermined gamma value from a ROM look-up table (not shown). The output of gamma setting circuit 32 is then supplied to an adder 33, which sums the signal output from A/D converter 30 and the signal output from gamma setting circuit 32. The summed result is output to a D/A converter 34, which converts the digital signal output from adder 33 into analog, and feeds the converted signal to a TFT pixel. Through this process, gamma correction is performed.

In FIG. 4, correction for an arbitrary point P is carried out as follows. When a data input voltage D.sub.VP at point P is output without gamma correction, the corresponding transmissivity of the input voltage becomes L.sub.P ". This causes the transmissivity to be nonlinear over the entire range of input data voltages. However, when input data voltage D.sub.VP ' at point P' is applied to the pixel, the transmissivity becomes L.sub.P, which is at a linear portion of the transmissivity characteristic curve.

Accordingly, the gamma set value becomes D.sub.VP -D.sub.VP ' because value D.sub.VP ' must be input instead of value D.sub.VP. The gamma set value varies with respect to the respective input data voltages of the nonlinear portions. The section from point A to point B in the graph shown in FIG. 4 has a linear transmissivity, requiring no gamma correction. Thus, when input data voltage D.sub.VQ ' at point Q' is applied to the pixel, transmissivity becomes L.sub.Q " and the characteristic becomes linear. If, however, the input voltage is Q, the output voltage is D.sub.VQ ' which is at a nonlinear portion of the transmissivity characteristic curve.

As discussed above, the digital gamma correction circuit performs D/A or A/D conversion with respect to the analog data signal. In converting the analog data into digital or the digital data into analog, round-off errors occur and data is frequently not expressed accurately. As a result, the number of gray scales or gradations which can be gamma corrected is limited.

FIG. 5 is a block diagram of a conventional analog gamma correction circuit, which forms a gamma-corrected output using several differential amplifiers. FIG. 6 is a graph showing the input/output characteristic of this gamma correction circuit. The conventional analog gamma correction will now be explained below with reference to FIGS. 5 and 6.

As seen in FIG. 5, three reference voltages V.sub.RL, V.sub.RM and V.sub.RH are applied to the respective differential amplifiers 505, 515 and 525, each of which having different gains and operating within different voltage ranges. Because the output current of each respective differential amplifier is I.sub.out =GM(Vin-Vout), current i.sub.out flowing through a load resistor R.sub.L becomes i.sub.1 +i.sub.2 +i.sub.3, which is controlled according to the input voltage range. An input/output characteristic of the gamma correction circuit is thus obtained, as shown in FIG. 6. The conventional analog gamma correction circuit shown in FIG. 5, however, uses more than three differential amplifiers, and is thus complicated.

As mentioned above, the digital gamma correction circuit causes round-off error in converting the analog data into digital or converting digital data into analog, thereby limiting the number of gradations for gamma correction. Further, the analog gamma correction circuit uses more than three differential amplifiers, and is therefore a very complicated circuit. Neither the conventional analog nor digital circuits can provide suitable gamma correction of the input signal.

Therefore, it is an object of the present invention to provide a gamma correction circuit using a conventional analog multiplier for performing gamma correction with respect to an input data signal.

To accomplish the object of the present invention, there is provided a gamma correction circuit for making linear the nonlinearity electrooptic characteristics of a liquid crystal display, the circuit comprising: a comparator for receiving an input data voltage and comparing it with three reference voltages, to thereby output an input data comparison signal; a first analog switch for receiving the input data comparison signal, which is the output signal of the comparator, and selecting and outputting a weight voltage corresponding to the signal; a second analog switch for receiving the input data comparison signal, which is the output signal of the comparator, and selecting and outputting a correction voltage corresponding to the signal; and an analog multiplier for receiving the input data voltage, the weight voltage of the first analog switch, and the correction voltage which is the output of the second analog switch, and outputting a final voltage.

FIG. 1 is a graph showing the electrooptic characteristic of a liquid crystal display (LCD);

FIG. 2 is a block diagram of an LCD driver having a conventional gamma correction circuit;

FIG. 3 is a block diagram of a conventional digital gamma correction circuit;

FIG. 4 is a graph of a gamma correction characteristic for a conventional digital gamma correction circuit;

FIG. 5 is a block diagram of a conventional analog gamma correction circuit;

FIG. 6 is a graph showing the input/output characteristic of a conventional gamma correction circuit;

FIG. 7 is a block diagram of one embodiment of a gamma correction circuit using an analog multiplier in accordance with the present invention;

FIGS. 8A and 8B are circuit diagrams illustrating an analog switch in the analog multiplier in accordance with the present invention;

FIG. 9 is a circuit diagram of an MOS Gilbert cell used in the analog multiplier of the gamma correction circuit in accordance with the present invention;

FIG. 10 illustrates a comparator circuit of the present invention;

FIG. 11 is a graph showing input voltage vs. output voltage at node N1 of the circuit shown in FIG. 10;

FIG. 12 is a graph showing the input/output characteristic of the gamma correction circuit in accordance with the present invention; and

FIG. 13 is a graph showing input voltage vs. output voltage at node N2 of the circuit shown in FIG. 10.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the attached drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

As shown in FIG. 7, a gamma correction circuit in accordance with a preferred embodiment with the present invention includes an analog multiplier having a comparator 70, first analog switch 71, second analog switch 72, and analog multiplier 73.

Comparator 70 receives two reference voltages V1 and V2 and a data input voltage Vin. A comparison is then made to determine whether the input voltage falls within a first range less than a first threshold voltage determined by a first reference voltage V1, a second range between the first threshold voltage and a second threshold voltage determined by reference voltage V2, or a third range above the second threshold voltage. An input data comparison signal Scom is then output in accordance with the range in which the input data voltage falls. Namely, three output lines are connected to comparator 70 and one of these lines goes high in accordance with the range in which the data input voltage Vin falls.

It should be noted, however, that although two reference voltages have been described above, any appropriate number may be used in accordance with the input data voltage and panel characteristics.

The three output lines from comparator 70 are supplied to first and second analog switches 71 and 72, respectively. As will be discussed in greater detail below, the first analog switch 71 selects one of weight voltages V.sub.B1, V.sub.B2, and V.sub.B3 and outputs it as weight voltage V.sub.B in response to one of the three output lines going high. In addition, second analog switch 72 selects a corresponding correction voltage V.sub.c among V.sub.c1, V.sub.c2 and V.sub.c3 in response to the one output line going high.

Input data voltage Vin, weight voltage V.sub.B and correction voltage V.sub.c are then supplied to analog multiplier 73, which adds V.sub.c to Vin, and multiplies the sum by the weight voltage V.sub.B. The resulting product is output as a gamma corrected voltage. Alternatively, V.sub.c can be subtracted from Vin by adding a negative value of V.sub.c to Vin.

FIGS. 8A and 8B are circuit diagrams illustrating in greater detail the structure of first and second analog switches 71 and 72, respectively. As seen in FIG. 8A, first analog switch 71 comprises first, second and third transistors Q1, Q2 and Q3, the sources of which being coupled to weight voltages V.sub.BL, V.sub.BM, and V.sub.BH, respectively. The gates of transistors Q1-Q3 respectively receive one of the three output lines from comparator 70. Accordingly, when one of the output lines from comparator 70 goes high, one of transistors Q1-Q3 is rendered conductive to supply a corresponding one of weight voltages V.sub.BL, V.sub.BM and V.sub.BH as the output weight voltage V.sub.B.

As seen in FIG. 8B, second analog switch 72 comprises fourth, fifth and sixth transistors Q4, Q5 and Q6, having correction voltages V.sub.C1, V.sub.C2, and V.sub.C3 applied, respectively to the sources thereof. The gates of these transistors receive reference voltages V.sub.C1, V.sub.C2 and V.sub.C3, and the drain potentials are coupled to generate output drain correction voltage V.sub.C in response to a logic high on one of the output lines from comparator 70.

As seen in FIG. 9, analog multiplier 73 includes an MOS Gilbert Cell 100 (as disclosed in "IEEE Journal of Solid-State Circuits, vol. Sc-20, No. 6, December 1985 pp. 1158-1168) and an adder 200. As noted above, analog multiplier 73 adds correction voltage V.sub.c from second analog switch 72 to input data voltage Vin to generate a sum, which is then multiplied by the weight voltage V.sub.B output from the first analog switch 71.

As illustrated in detail in FIG. 9, Vin is supplied across input nodes N5 and N6. N6 is coupled to the gates of n-channel MOS transistors M3 and M6, and N5 is connected to adder 200, which adds the potential at node N5 to .+-.V.sub.c and supplies the sum to the gates of n-channel MOS transistors M4 and M5. The drains of transistors M3 and M5 are connected to power supply VCC through resistor RL.sub.1 and the drains of resistors M4 and M6 are connected to power supply VCC through resistor RL.sub.2. Currents I.sub.7 and I.sub.8 flow through resistors RL.sub.1 and RL.sub.2, respectively, and a final output voltage is generated across nodes P1 and P2.

The final output voltage between nodes P1 and P2 corresponding to the product of Vi (see FIG. 9) and Vb can be expressed in accordance with the following formula:

where Vi (Vin.+-.V.sub.c) is the first input, Vb (the weight voltage) is the second input, and K1=R1.times.(2 Ka Kb).sup.1/2, Ka and Kb are constants determined by the gate length and gate width of the MOS transistors.

A detailed explanation of comparator 70 will now be made with reference to FIG. 10. As noted above, comparator 70 receives two reference voltages V1 and V2, and outputs an input data comparison signal Scom on one of three output lines. Comparator 70 includes: first and second comparator sections 81 and 82, respectively; inverters INV1 and INV2; and AND gates AND1 and AND2.

The first comparison circuit 81 includes p-channel MOS transistor M10 having its drain connected to the drain of n-channel MOS transistor M11 through node N1. As further shown in FIG. 10, the sources of transistors M10 and M11 are connected to power supply V.sub.cc and ground, respectively, and the gates of transistors M10 and M11 receive input data signal Vin and reference voltage V1, respectively.

The second comparison circuit 82 includes p-channel transistor M12 and n-channel transistor M13, the sources of which are connected to power supply V.sub.cc and ground, respectively. The gates of transistors M12 and M13 respectively receive input data signal Vin and reference voltage V2, and the drains of these transistors are connected to each other through node N2.

AND gate AND1 receives signals appearing at nodes N1 and N2, and, in response thereto, generates a first data comparison signal VS1 on one of the output lines of comparator 70. AND gate AND2 receives the signal appearing at node N2 and the signal appearing at node N1 inverted by inverter INV1. In response to these input signals, AND2 outputs a second data comparison signal VS2 on a second one of the output lines of comparator 70. Further, inverter INV2 inverts the signal appearing at node 2 to generate a third data comparison signal VS3 on a third one of the output lines of comparator 70.

The operation of comparison circuit 11 will now be described with reference to FIG. 11 illustrating the voltage at node N1, VN1, as a function the input data signal Vin. VN1 is maintained at a relatively high level provided that Vin is below threshold voltage VT1. Once Vin exceeds VT1, however, the voltage on node N1, VN1, drops sharply. VT1 is a function of the gate lengths and widths of transistors M10 and M11, as well as the value of reference voltage V1.

A plot of the voltage at node N2 of the second comparison section 82, VN2, as a function of Vin, is shown in FIG. 13. This plot is similar to that shown in FIG. 11. However, the threshold voltage, VT2, at which VN2 drops is preferably greater than threshold voltage VT1. VT2 depends on the gate lengths and widths of transistors M12 and M13, as well as the value of reference voltage V2.

The operation of comparison circuit 70 will now be described. If the input data voltage is lower than threshold voltages VT1 and VT2, nodes N1 and N2 are maintained at a relatively high potential. Accordingly, the output of AND gate AND1, VS1, is also high, while the output of AND gate AND2, VS2, is low because the output of INV1 is low. Further, INV2 inverts the relatively high voltage signal present on node N2 to render VS3 low. Thus, only one of the three output lines of comparator 70 is high. In this case, the output line carrying signal VS1 is rendered high.

If the input data voltage signal vin is increased so that it is higher than VT1, but lower than VT2, node N1 is rendered low while node N2 remains at a high voltage. Thus, the output of AND gate AND1, VS1 is low. However, VS2 goes high because both inputs of AND gate AND2 are also high, but VS3 remains low because inverter INV2 continues to invert the relatively high voltage present on node N2.

Further, if input data signal Vin is increased even further so that it is higher than both VT1 and VT2, then nodes N1 and N2 are both rendered low, and the outputs of AND gates AND1 and AND2, i.e., VS1 and VS2, are also both rendered low. However, the output line of comparator 70 carrying VS3 (i.e., the output of inverter INV2) is rendered high.

In summary, comparator 70 receives input data voltage 70 and compares it with threshold voltages VT1 and VT2 to selectively render one of signals VS1, VS2 or VS3 high on a corresponding one of three output line s of comparator 70.

As noted above, first analog switch 71 receives three reference voltages, as shown in FIG. 8A, so that a weight voltage corresponding to the input data comparison signal output from comparator 70 is determined. If the range of the input data voltage is less than threshold voltages VT1, VS1 is rendered high and transistor Q1 is turned on so that weight voltage V.sub.BL is output. If the range of the input data voltage is between threshold voltages VT1 and VT2, VS2 is rendered high and transistor Q2 is turned on so that weight voltage becomes V.sub.BM is output. Further, if the range of the input data voltage is above threshold voltage VT2, VS3 is set high and transistor Q3 is turned on such that weight voltage V.sub.BH is output.

After receiving the input data comparison signal Scom (including signals VS1, VS2 and VS3), first analog switch 71 selects weight voltages V.sub.BL, V.sub.BM and V.sub.BH, in accordance with the ranges of the input data voltage, and then feeds them to the analog multiplier 73.

References for determining weight voltage V.sub.B can be expressed by the following equation (1).

Second analog switch 72 receives three reference voltages V.sub.C1 -V.sub.C3, as shown in FIG. 8B, so that a correction voltage according to the input data comparison signal output from comparator 70 is selected and output. If the range of the input data voltage is less than VT1, VS1 is set high and transistor Q4 is turned on so that correction voltage V.sub.C1 is output. If the range of the input data voltage is between VT1 and VT2, VS2 is raised to a high level and transistor Q5 is turned on so that correction voltage V.sub.C2 is output. Likewise, if the range of the input data voltage is above VT2, VS3 is set high and transistor Q6 is turned on such that correction voltage becomes V.sub.C3 is output.

Thus, in response to receiving the input data comparison signal, second analog switch 72 selects one of correction voltages V.sub.C1, V.sub.C2 and V.sub.C3, in accordance with which range input data voltage Vin fall. The selected correction voltage is then also fed to analog multiplier 73.

References for determining correction voltage V.sub.C can be expressed by the following equation (2).

As indicated above, the MOS Gilbert cell 100 shown in FIG. 9 receives the selected weight and corrected voltages and outputs a gamma corrected voltage, Vout across nodes P1 and P2 in response thereto.

The operation of Gilbert cell 100 will now be discussed with reference to equation (3) below:

where Vi is the first input determined by adding or subtracting the correction voltage Vc to the input data voltage Vin, V.sub.B is the weight voltage or the second input to Gilbert cell 100, and k1=RL* (2KaKb).sup.1/2 (Ka and Kb are constants determined by the gate lengths and width of the MOS transistors of the Gilbert cell, and RL is the resistance of one of load resistors RL.sub.1 or RL.sub.2.)

In the event that the correction voltage V.sub.c is subtracted from V.sub.in : ##EQU1## That is, analog multiplier 73 subtracts correction voltage V.sub.c from the input voltage V.sub.in, and then multiplies the difference by the weight voltage V.sub.B. The resulting product is then output as the final gamma corrected voltage.

FIG. 12 is a graph illustrating the output characteristics of analog multiplier 73. Portions of the graph labeled A1-A3 will be described in detail below.

If Vin is less than VT1, then V.sub.B =V.sub.BL and V.sub.c =V.sub.c1. Accordingly: ##EQU2## such that analog multiplier 73 operates in region A1 of the graph shown in FIG. 12.

If Vin is greater than VT1 but less than VT2, then V.sub.B =V.sub.BM and V.sub.c =V.sub.c2. Accordingly: ##EQU3## such that analog multiplier 73 operates in region A2 of the graph shown in FIG. 12.

If Vin is greater than VT2, then V.sub.B =V.sub.BH and V.sub.c =V.sub.c3. Accordingly: ##EQU4## such that analog multiplier 73 operates in region A3 of the graph shown in FIG. 12.

In summary, in the gamma correction circuit including an analog multiplier, comparator, first and second analog switches 71 and 72, when data voltage Vin is input, the comparator compares the input voltage to determine whether the input voltage falls within one of three voltage ranges. The first voltage range constitutes those voltage less than a first threshold voltage corresponding to a first reference voltage; the second range constitutes those voltages greater than the first threshold voltage but less than a second threshold voltage corresponding to a second reference voltage; and the third voltage range constitutes those voltages greater than the second threshold voltage. Depending on which range the input data signal falls, one of three output lines is set to a high level and supplied to first and second analog switches. In response to the high output line, analog switch 71 selects a weight voltage corresponding to the value of the input data voltage and supplies the result to the analog multiplier. Second analog switch 72 selects a correction voltage corresponding to the value of the input data voltage and also supplies the result to the analog multiplier. The analog multiplier preferably subtracts the selected correction voltage V.sub.c from the input data voltage and then multiplies the difference by the selected weight voltage V.sub.B. The resulting product is the final gamma-corrected output voltage.

Unlike the conventional gamma correction circuit, the present invention applies the weight voltage and correction voltage to the analog multiplier, obtaining output voltages appropriate for various ranges of input voltages. Therefore, nonlinearities due to the electrooptic characteristic of the liquid crystal display can be made linear. In addition, the present invention eliminates D/A and A/D conversion circuitry required in the conventional digital gamma correction circuit, enabling gamma correction to be performed for a wide range of gradations. Furthermore, the present invention does not require differential amplifiers, thereby simplifying the design of the gamma correction circuit.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.