Method for Simultaneously Fabricating Salicide and Self-Aligned Barrier

1. Field of the Invention

The present invention relates to a method of fabricating salicide and self-aligned barrier simultaneously. The fabricating of thin film Ti silicide is difficult and the surface is rough in the prior art whereas the present invention provides a method to overcome these problems. Because Si and Al intermix with each other, `spike` is thus formed penetrating source/drain region. In order to form the barrier layer to prevent the mixture, the prior art ether deposits TiN or utilize Ti nitridation. The former can hardly control the thickness of TiN in contact hole while the later must utilize another RTP to generate TiN, both may decrease the yield. The present invention utilize RTP only once and TiN is deposited all over Ti film so the thickness of TiN is easily controlled and the yield would not be decreased.

2. Description of the Prior Art

The conventional contact structure using a self-aligned silicide is described as following sequences of processes:

1. After the source and drain regions have been implanted to form the source/drain junctions, the poly-Si sidewall spacers 110 are formed (FIG. 1a).The spacer is made of SiO.sub.2. Note that side wall oxidation structures along the gate (known as oxide spacers 110) are used to prevent the gate and source/drain areas from being electrically connected. Following the silicide formation, a selective etch removes the unreacted metal without attacking the silicide.

2. The metal used to form the silicide is deposited all over the topography to form a film 120 of metal which can be Ti, Co or Ni . . . etc. (FIG. 1b)

3. The wafer 125 is heated by rapid thermal process (RTP), which causes the silicide reaction to occur wherever the metal film is in contact with the silicon. The configuration mentioned above is shown as 130a in FIG. 1c. The metal remains unreacted everywhere else and is shown as 130b in FIG. 1c.

4. The unreacted metal is selectly removed through the use of an etchant that dose not attack the silicide, the silicon substrate, or the SiO.sub.2. As a result, each exposed source and drain region is now completely covered by silicide, but there is no film elsewhere (FIG. 1d).

5. A dielectric layer is deposited onto the silicide, and contact holes are opened in it down to the silicide layer.

6. Deposit a layer of titanium all over the topography by DC magnetron sputtering followed by a process of RTP in the chamber that containing N.sub.2 or NH.sub.3. A diffusion barrier layer--TiN is thus formed over the silicide and is shown as TiN layer 160 in FIG. 1e and dielectric layer mentioned in the previous step is shown as dielectric layer 150 in FIG. 1e.

The implement of TiN layer can utilize the other method: Sputtering deposit TiN into contact hole 155 shown in FIG. 1g to form the TiN layer 165. The advantage is the spare of RTP, whereas, especially when the contact size is small, it is hard to control the thickness of TiN layer 165 in the contact hole by sputtering deposition.

7. Having deposited W-plug into the contact holes over the TiN layer, metal-Al is deposited over W-plug and the TiN layer. By etching the unwanted part of aluminum, the unwanted TiN layer is removed too. Thus the Al layer is made in contact with the suicide through W-plug and the Al conducting line is shown as 170 in FIG. 1f.

The configuration mentioned above is called salicide, wherever TiSi.sub.2 and CoSi.sub.2 are attractive for the salicide application because it exhibits low resistivity, and because it can reduce native-oxide layers (making it the only known refractory metal that can reliably form a silicide on both polycrystalline and single-crystal silicon through a thermal reaction). Therefore TiSi.sub.2 and COSi.sub.2 are widely used in the salicide application nowadays. Furthermore, devices fabricated with titanium silicide on the gate electrode are more resistant to high-field-induced hot-electron degradation than are conventional poly-Si gate devices. It is conjectured that the TiSi.sub.2 and COSi.sub.2 are effective getteres for the hydrogen atoms introduced during the hydrogen annealing. Less hydrogen is thus incorporated into the gate oxide, and this improves the hot-electron reliability.

On the other hand, to prevent the widely used silicide material-Ti from intermixing with interconnect metal-Al, diffusion barrier layer-TiN is deposited between these two kinds of metal. The TiN layer can be formed by sputtering from a TiN target in an inert or by the procedure of rapid thermal process (RTP) of Ti in an nitrogen ambient. The procedure is sophisticated, especially, and it is hard to control the thickness of the diffusion barrier layer owing to the contact size. Besides, in some application utilizing high aspect ratio contact process (e.g. the process of DRAM . . . etc.), it is hard to form enough thickness of diffusion barrier layer-TiN, so that the difficulty of the successive processes is raised. Furthermore, in the conventional process forming thinner Ti film and narrower gate-source/drain region, it is difficult to form Ti silicide and the resistivity of the Ti silicide is hard to reduce. In addition, the surface of silicide is rough and the dielectric layer over silicide is thus rough too. In wiring processes, it is desirable that the dielectric layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surface. Also, rough surface topography results in poor step coverage by subsequently deposited layers, discontinuity of layers across steps, and void formation between topographic features. Poor step coverage by deposited layers and void formation between topographic features result in degraded process yield and poorer reliability of integrated circuits. In addition, RTP is used twice in the prior art, because the thermal control is still not perfect, the yield maybe decreases.

A method for simultaneously fabricating salicide and self-aligned barrier layer is disclosed in the present invention. The metal stack Ti--TiN--Ti is formed all over the topography of the wafer and reacts with silicon atoms to generate another silicide stack TiSi.sub.2 --TiN--TiSi.sub.2. Thus the salicide and self-aligned barrier layer TiN is formed simultaneously. Furthermore the process generating TiSi.sub.2 --TiN--TiSi.sub.2 utilizes RTP only once so the throughput can be raised. Since the passive barrier layer TiN is formed by sputtering deposition over the Ti film instead of in the contact hole, it is easy to control the thickness of TiN layer. In addition, the top-layered TiSi.sub.2 acts as a sacrificial barrier layer and is combined with the passive barrier layer TiN to act as diffusion barrier layer. The barrier layer of the present invention is stronger than that of the prior art. Further, the processes that forming the metal stack can be performed in the same site so that the process is less sophisticated.

The above features of the present invention will be more clearly understood from consideration of the following descriptions in connection with accompanying drawings in which:

FIG. 1a-FIG. 1f show the sequence of processes how the salicide and diffusion barrier layer is formed in the prior art. FIG. 1g shows the other method of forming diffusion barrier layer.

FIG. 1a is a cross-sectional view of a wafer that with the oxide spacers formed along the gate.

FIG. 1b is a cross-sectional view of a wafer that with titanium deposited all over the topography of the wafer.

FIG. 1c is a cross-sectional view of a wafer that with specific regions of titanium reacted with underlying silicon atoms contained layers to form TiSi.sub.2 layers.

FIG. 1d is a cross-sectional view of a wafer that with the unreacted titanium etched and the regions containing TiSi.sub.2 left.

FIG. 1e and FIG. 1g individually is a cross-sectional view of a wafer: that dielectric layer is deposited all over the topography with contact hole opened and diffusion barrier layer is formed all over the topography and into the contact hole respectively.

FIG. 1f is a cross-sectional view of a wafer that with Al conductor lines deposited over the deposited W-plug.

FIG. 2a-FIG. 2f shows the sequence of processes how the salicide and diffusion barrier layer is formed.

FIG. 2a is a cross-sectional view of a wafer that with the oxide spacers formed along the gate.

FIG. 2b shows the metal stack all over the topography of wafer. The metal stack is Ti--TiN--Ti.

FIG. 2c shows that the silicide is formed after RTP and some portions of TiTiN--Ti becorne TiSi.sub.2 --TiN--TiSi.sub.2.

FIG. 2d shows that the unreacted portions of Ti--TiN--Ti structure is etched by RCA clean whereas the TiSi.sub.2 TiN--TiSi.sub.2 structure is left.

FIG. 2e shows that the dielectric layer is deposited over the whole wafer and the contact holes are opened followed by W-plug is sputter deposited into those holes.

FIG. 2f shows that the Al conducting lines are deposited over the W plugs with the unwanted portions of Al etched.

According to the present invention, an improved method of simultaneously fabricating the self-aligned silicide and barrier layer is described. This technique finds particular application in the processing of silicon wafers for integrated circuit chips. Accordingly, the invention will be described for this particular application.

Referring now to the drawings, FIG. 2a shows a section through the silicon wafer 215 after the initial processing steps. The spacer 210 is formed along the gate electrode 212, which composed of poly-Si. The source/drain electrode 213 is composed of n-type silicon whereas the spacer 210 and field oxide 220 is composed of SiO.sub.2. Referring to FIG. 2b, using a sputtering method to deposit a Ti-film 230 (film 230 can be made of Ti, Co or Ni . . . etc., and Ti is employed in this preferred embodiment) over the topography of the wafer 225, followed by sputtering to deposit a TiN-film 240 over the Ti-film 230. Finally a Ti-film 250 is deposited by sputtering over the TiN-film 240. The thickness of the Ti-film 230 is about 200-500 angstroms. The thickness of the TiN-film 240 is about 300-1000 angstroms and the thickness of the Ti-film 250 is about 200-500 angstroms the metal stack 255 is thus formed all over the wafer 225 which containing the regions underlying Si and SiO.sub.2. Note that the film 240 is always TiN or TiW whatever film 230 and film 250 are.

Following the previous process, a RTP is performed by heating the wafer 225 at about 600.degree.-800.degree. C. for 20 seconds. The Si atoms in the gate electrode 212 and source/drain region 213 are driven into Ti-film 230 and reacted with Ti to produce TiSi.sub.2, thus the TiSi.sub.2 -film 260 is formed. Some of the previously mentioned Si atoms are driven through TiN-film 240 into Ti-film 250 and reacted with Ti to produce TiSi.sub.2, thus the TiSi.sub.2 -film 270 is formed. The metal stack on spacer 210 or field oxide 220 is remained unreacted while the other is TiSi.sub.2 --TiN--TiSi.sub.2. The cross-sectional view is shown in FIG. 2c.

The unwanted region Ti--TiN--Ti can be etched by RCA clean while metal stack 280 TiSi.sub.2 --TiN--TiSi.sub.2 is left as shown in FIG. 2d. It is clear that the self-aligned silicide (salicide) and self-aligned barrier layer are formed simultaneously and are contained in the metal stack 280 TiSi.sub.2 --TiN--TiSi.sub.2.

The RCA clean is performed by: preparing a fresh mixture of H.sub.2 O--NH.sub.4 OH--H.sub.2 O.sub.2 by 5:1:1 (in volume) and then heating the mixture to 75.degree.-80.degree. C. The wafer 285 is submarged completely into the mixture for 10-15 minutes, and is maintained at 80.degree. C.

Followed by the previous step, a chemical vapor deposition of doped SiO.sub.2 occurred. Referring to FIG. 2e, the dielectric layer is phosphosilicate glass (PSG) so the deposition of doped SiO.sub.2 utilizes a reaction of silane; oxygen; and phospine to form PSG films. The reactions are given by: ##STR1## The reaction can be formed by CVD or LPCVD and the temperature must maintained in the range 300.degree.-500.degree. C. Followed by the deposition of PSG layer, the contact hole is then opened by the following steps: 1) photoresist is spun on the previous mentioned wafer followed by the process of exposure . . . etc to form the pattern; 2) use the liquid mixtures of H.sub.2 O and HF at the ratio of 100:1 as an etchant to etch contact holes; 3): strip the pattern formed previously. Because the top-layered TiSi.sub.2 270 acts as an etching stop, the contact hole is thus formed easily. The configuration is shown in FIG. 2e. The resulting wafer is deposited on a thin film of aluminum and then is spun on the photoresist. In which the aluminum film is produced by the method of sputtering deposition. After a wafer has been coated with the photoresist and suitably soft-baked, it is ready to be exposed to some form of radiation in order to create a latent image in the photoresist, the pattern is thus formed. To form the aluminum conducting line, an etchant consists by the ratio HNO.sub.3 : CH.sub.3 COOH: H.sub.3 PO.sub.4 : H.sub.2 O=1:4:4:1 is applied to remove those portions of aluminum film without the photoresist on them. Been stripped of the pattern, the result is shown in FIG. 2f. Because the RTP is used only once in the present invention whereas it is used twice in the prior art, the yield of the prior art is lower than the present invention.

The top-layered TiSi.sub.2 270 acts as a sacrificial barrier layer because the Si atoms may diffuse into Al conducting line. While the Si atoms of bottom-layered TiSi.sub.2 is retarded by TiN film, the TiN is often called passive barrier layer. Passive barrier layer TiN and sacrificial barrier layer TiSi.sub.2 is called barrier layer, and the strength of this barrier layer is stronger than that in the prior art.

Although specific embodiments have been illustrated and described it will be obvious to those skilled in the art that various modification may be made without departing from the spirit which is intended to be limited solely by the appended claims.