US 5,923,970 AGrant
Method of Fabricating a Ferrolelectric Capacitor With a Graded Barrier Layer Structure
Issue Date:1999-07-13
•16 Claims
•4 Drawing Sheets
Abstract
A method of fabricating an integrated circuit capacitor in which a first conductive plate, a layer of ferroelectric material, and a second conductive plate are deposited and formed in sequence. Thereafter a diffusion barrier material and an insulative material are deposited either (1) as layers of the diffusion barrier material and the insulative material with tensile and compressive stresses in the respective layers offsetting one another, (2) as a layered dielectric stack with alternating layers of the diffusion barrier material and the insulative material, or (3) as a graded diffusion barrier material varying from a binary oxide of Ta, Nb, or Zr at the surface of the ferroelectric material to SiO.sub.2 at a distance above the surface of the ferroelectric material.
Metadata
Assignee
- Advanced Technology Materials, Inc.
Inventor
- Peter S. Kirlin
Application Information
Application Number:US 9747796
Filing Date:1997-11-20
Priority Date:1997-11-20
Art Unit:284
Classifications
IPC:
H01G 406
Field of Search:
438240;396
Patent Drawings (4 sheets)
Description
Background of the Invention
1. Field of the Invention
This invention relates to devices methods for fabricating integrated circuits and more particularly to a method for fabricating a ferroelectric capacitor in an integrated circuit (IC) device, as well as the ferroelectric capacitor structure and the IC device comprising same.
2. Description of the Related Art
Integrated circuit chips include a substrate of semiconductive material with component structures of electronic circuits, e.g., transistors and resistors, fabricated within the substrate structure. Additional electrical devices and precursor and/or component structures of the electronic circuits are fabricated over the top of the substrate. These additional devices and structures of circuits include conductive leads, capacitors, and parts of transistors. The devices fabricated above the substrate typically require many layers, of a variety of materials, e.g., conductors, semiconductors, insulators, and barriers.
Conductive layers in integrated circuit devices often are fabricated in aluminum (Al), copper (Cu) or tungsten (W). Each conductive layer is deposited over an underlying surface and typically is patterned and etched into a shape that is predetermined by designers to perform a desired function in the final circuit product. Typical integrated circuit devices require multiple layers of conductive materials. Undesirable electrical shorting between conductive layers is prevented by interposing one or more layers of insulative material between each conductive layer and the next conductive layer above and/or below it.
Fabrication of an integrated circuit capacitor requires the fabrication of two layers of conductive materials forming the conductive plates of the capacitor. Those two plates are separated by a layer of dielectric material. During recent years researchers and designers have been investigating the use of high dielectric constant materials for use as integrated circuit capacitor dielectrics. Some promising high dielectric constant materials include lead zirconium titanate (PbZrTiO.sub.3), sometimes hereinafter denoted "PZT," and strontium bismuth tantalum oxide (SrBi.sub.2 Ta.sub.2 O.sub.9), sometimes hereinafter denoted "SBT." Because of the hysteresis type voltage-current (VI) characteristics of these materials, they are known as ferroelectric materials.
During fabrication of integrated circuit devices including capacitors with a ferroelectric dielectric material, the ferroelectric material is deposited before the second, or upper, plate of the capacitor is deposited and formed. After the upper plate is formed, a layer of insulative material typically is deposited to insulate the upper plate from another layer of conductive material, generally referred to as a metal layer. The process of shaping the upper plate of the capacitor can expose a portion of the ferroelectric material before the insulative material is to be deposited.
A standard insulative material, long used in fabrication of integrated circuit devices, is silicon dioxide (SiO.sub.2). Because developers have lengthy experience working with silicon dioxide and appropriate equipment for depositing it, silicon dioxide is the insulative material of choice for the layer of intermetal insulator between the upper capacitor plate and the next overlying conductive layer. Silicon dioxide appears to be a very good choice as the intermetal layer material except that in combination with the ferroelectric material, it creates problems while it is being deposited or during subsequent processing steps. A primary problem is that silicon dioxide reacts directly with the exposed parts of PbZrTiO.sub.3 or SrBi.sub.2 Ta.sub.2 O.sub.9 while the silicon dioxide is being deposited or during the subsequent processing steps. This reaction degrades the electrical properties of the ferroelectric material. Chemical vapor deposition (CVD) is a process used for depositing the silicon dioxide. The CVD process uses either hydrogen or silicon hydride (SiH.sub.4), as a carrier gas. Both of these carrier gas species are reducing gases. These reducing gases can react directly with the ferromaterial to form water which in turn reacts with the ferroelectric material and degrades its electrical properties.
Additionally, the deposited layer of silicon dioxide has a residual compressive stress in its crystalline structure. This compressive stress is translated into the ferroelectric material and degrades the electrical properties of the ferroelectric material.
Developers are left with a dilemma of finding a different material than silicon dioxide for use as an intermetal insulator or of finding a new device structure and a new method for depositing silicon dioxide without degrading the desirable electrical characteristics of the ferroelectric material, used as a capacitor dielectric.
Summary of the Invention
The foregoing and other problems are resolved by a new device structure and a method of fabricating an integrated circuit capacitor. A first conductive plate is deposited and formed on a substrate. A layer of ferroelectric material is deposited and formed over the first conductive plate, and a second conductive plate is deposited and formed on the layer of ferroelectric material. A layer of a diffusion barrier material and a layer of an insulative material are deposited over the second conductive plate, wherein residual tensile stress in the crystalline structure of the diffusion barrier material offsets residual compressive stress in the crystalline structure of the insulative material.
Materials, such as PbZrTiO.sub.3 or SrBi.sub.2 Ta.sub.2 O.sub.9, may be used as the ferroelectric material.
Materials, such as TiO.sub.2, ZrO.sub.2, Ta.sub.2 O.sub.5, Nb.sub.2 O.sub.5, and Zr.sub.1-x Ti.sub.x O.sub.2, where x is a number in a range from zero to one, may be used as the diffusion barrier material.
Materials, such as SiO.sub.2, Si.sub.3 N.sub.4, spin-on-glass, SiF.sub.z O.sub.4-z, wherein z is a number that varies in a range from zero to four, or an organic dielectric, such as polyimide, and compatible combinations of the foregoing, may be used as the insulative material.
In an alternative method, the diffusion barrier material and the insulative material may be deposited as a layered dielectric stack with alternating layers of the diffusion barrier material and the insulative material. Residual tensile stresses in the layers of diffusion barrier material offset the residual compressive stresses in the layers of insulative material.
In another method of the present invention, a graded diffusion barrier material is deposited on the top capacitor plate and the exposed ferroelectric material. The graded diffusion barrier material may suitably comprise Ta.sub.5-y Si.sub.y O.sub.10 or Nb.sub.5-y Si.sub.y O.sub.10 with y being a number varying along the thickness of the barrier material, e.g., from zero at the second conductive plate to five at a desired distance from the second conductive plate. In still another method aspect of the invention, a graded diffusion barrier material of the formula Zr.sub.1-x Si.sub.x O.sub.2 is deposited on the ferroelectric material, wherein x is a number varying along the thickness of the diffusion barrier material, from zero at the second conductive plate to one at a desired distance from the second conductive plate.
Other aspects, features and embodiments of the invention will be more fully apparent from the ensuing disclosure and appended claims.
Brief Description of the Drawings
FIG. 1 is a cross-sectional view of a substrate with a layer of conductive material deposited thereupon.
FIG. 2 is a cross-sectional view of the part of FIG. 1 with the conductive material formed into a first capacitor plate.
FIG. 3 is a cross-sectional view of the part of FIG. 2 with a layer of ferroelectric material deposited over the first capacitor plate.
FIG. 4 is a cross-sectional view of the part of FIG. 3 after the ferroelectric material is formed into shape as the capacitor dielectric.
FIG. 5 is a cross-sectional view of the part of FIG. 4 with a second layer of conductive material deposited over the shaped ferroelectric material.
FIG. 6 is a cross-sectional view of the part of FIG. 5 after the second layer of conductive material is shaped into a second capacitor plate.
FIG. 7 is a cross-sectional view of the part of FIG. 6 with a layer of diffusion barrier material deposited over the second capacitor plate.
FIG. 8 is a cross-sectional view of the part of FIG. 7 with an intermetal level dielectric deposited over the diffusion barrier layer.
FIG. 9 is a cross-sectional view of the part of FIG. 6 with a first layer of diffusion barrier material deposited, as the first of a stack of layered dielectric materials, over the second capacitor plate.
FIG. 10 is a cross-sectional view of the part of FIG. 9 with a first layer of insulative material deposited, as a second of the stack of layered dielectric materials, over the second capacitor plate.
FIG. 11 is a cross-sectional view of the part of FIG. 10 with a second layer of diffusion material in the stack.
FIG. 12 is a cross-sectional view of the part of FIG. 11 with a second layer of insulative material in the stack.
FIG. 13 is a cross-sectional view of the part of FIG. 6 with a layer of graded diffusion barrier material deposited over the second capacitor plate.
FIGS. 14 and 15 are graphs showing the relationships between selected materials that may be utilized in the graded diffusion barrier layer of FIG. 13.
Detailed Description of the Invention, and Preferred Embodiments Thereof
Referring now to FIG. 1, there is shown a semiconductor substrate 50 that has a conductive layer of material 52 deposited thereupon. This layer of conductive material 52 may be any compatible conductor, such as a metal. Typical metallic conductors include aluminum (Al), copper (Cu) and tungsten (W). The metallic conductor may be suitably deposited by a chemical vapor deposition (CVD) process, using well-known apparatus and processing parameters. After the layer of conductive material 52 is deposited on the substrate 50, then the conductive material is formed into a desired shape of a capacitor plate by conventional techniques well-known in the art.
FIG. 2 shows the result of the steps of processing the device, as shown in FIG. 1, to form the first plate 54 of a capacitor that may be used as the storage capacitor in an integrated circuit memory device. In the process steps, a photoresist is deposited over the layer of conductive material 52 of FIG. 1. The photoresist is patterned, and the layer of conductive material 52 is etched away, by a suitable conventional etch technique, except for the shape of the capacitor plate 54. This capacitor plate 54 thus forms the first, or bottom, plate of the storage capacitor being fabricated.
As shown in FIG. 3, a layer of insulative material 56 is deposited over the first capacitor plate 54 and any exposed surfaces of the substrate 50. The insulative material 56 is selected to be a high dielectric material with ferroelectric characteristics. Examples of such ferroelectric materials include materials such as lead zirconium titanate (PbZrTiO.sub.3) and strontium bismuth tantalum oxide (SrBi.sub.2 Ta.sub.2 O.sub.9). Either of these ferroelectric materials can be deposited by a chemical vapor deposition process using known apparatus and processing parameters. After the insulative layer 56 is deposited, it is shaped to conform with the designer's desired capacitor dielectric shape.
Referring now to FIG. 4, there is shown the result of shaping the ferroelectric material 56 of FIG. 3 into the capacitor dielectric layer 58. This shaping is accomplished by depositing a photoresist material over the layer of ferroelectric material, patterning the photoresist, and etching away undesired ferroelectric material. The etching may be readily accomplished by use of a conventional dry etch process. As a result, the device being fabricated now includes the substrate 50, the first capacitor plate 54, and the capacitor dielectric 58 which is made of either PbZrTiO.sub.3 or SrBi.sub.2 Ta.sub.2 O.sub.9.
FIG. 5 shows the cross-section of the device following deposition of another layer of conductive material 59, which is deposited over the capacitor dielectric 58. Typically a metal, e.g., aluminum or tungsten, is used. For ease of fabrication, the choice of metal for this layer may be the same material as the metal selected for use in the first capacitor plate 54. The selected metal can be deposited by chemical vapor deposition (CVD) using known apparatus and processing parameters. After this conductive layer is deposited, it is shaped into a second capacitor plate.
Referring now to FIG. 6, there is shown the result of the device with the conductive layer 59 of FIG. 5 shaped into a second, or upper, capacitor plate 60 of the desired capacitor structure. The shaping occurs by depositing a photoresist material over the conductive layer 58 of FIG. 5, patterning the photoresist, and etching away undesired portions of the conductive layer 58. The etch removal of undesired portions of the conductive layer 58 may be effected with any suitable conventional etching process having utility for such purpose. Thus the second capacitor plate 60 is left on top of the capacitor dielectric layer 58. It is noted that the desired shape of the second capacitor plate 60 leaves end portions of the capacitor dielectric layer 58 exposed to deposition of a subsequent layer of material. Although such exposure of the dielectric material 58 may not occur in all capacitor designs, it does occur in some highly desirable capacitor designs. Selection of appropriate subsequent processing steps is important to avoid depositing an intermetal insulator, such as silicon dioxide (SiO.sub.2), which would degrade the electrical properties of the capacitor dielectric 58.
In accordance with the present invention, a new structural arrangement is used and a new step is employed in the fabrication process to prevent degradation of the capacitor dielectric 58 during subsequent processing. This step comprises the deposition of an oxygen diffusion barrier layer that prevents oxygen from diffusing from the capacitor dielectric 58 to the intermetal dielectric layer which is to be subsequently deposited. The barrier layer also prevents diffusion of hydrogen and water from the atmosphere of the deposition vessel (not shown) to the capacitor dielectric layer 58 during the fabrication process.
In FIG. 7, the device being fabricated is now shown with a layer of oxygen diffusion barrier material 62 deposited over the top of the second capacitor plate 60 and the exposed portions of the capacitor dielectric 58. Binary oxides, e.g., titanium oxide (TiO.sub.2), zirconium oxide (ZrO.sub.2), tantalum oxide (Ta.sub.2 O.sub.5), and niobium oxide (Nb.sub.2 O.sub.5) may be used to form the oxygen diffusion barrier layer 62. Deposition can be accomplished by physical vapor deposition (PVD), sputtering, or evaporation, at appropriate and readily determinable process conditions therefor.
The resulting layer of oxygen diffusion barrier material 62 provides a dense, hydrogen (H.sub.2) free and water (H.sub.2 O) free barrier for the device being fabricated.
This diffusion barrier 62 prevents reduction of the capacitor dielectric, or ferroelectric, layer 58. Degradation of the electrical characteristics of the ferroelectric material is thereby avoided.
Advantages of the PVD process for the formation of the diffusion barrier include the fact that the process can be adjusted to be dry, i.e. no water, and oxidizing. The diffusion barrier 62 can be deposited with a residual tensile stress in its crystalline structure.
The formation of the diffusion barrier with residual tensile stress may be achieved by techniques known in the art, such as described in G. H. Haertling, Ferroelectrics, 1987, Vol. 75, pp. 25-55 (III. Properties, 2. Mechanical Properties, 2.sup.nd paragraph), where in discussing the highly compliant nature of PLZT (Pb-La-Zr-Ti-O), Haertling mentions a device disclosed in turn in J. Maldonado and A. Meitzler, Proc. IEEE, 1971, Vol. 59, p. 368 in which "domain orientation was accomplished by mechanically flexing a PLZT plate bonded to a plexiglas substrate." Such mechanical flexure approach can be employed to provide the diffusion barrier 62 with an appropriate residual tensile stress to counteract the residual compressive stresses in the layer(s) of insulative material subsequently deposited over the barrier layer.
Alternatively, the diffusion barrier may be formed with phase changes during processing whereby residual tensile stresses are imparted to the product diffusion barrier film.
Additionally, differential temperature effects may be employed in the formation of the barrier layer to impart residual tensile stresses to the barrier layer film.
Referring now to FIG. 8, there is shown a cross-section of the integrated circuit device after deposition of a layer of intermetal dielectric 64. Because of the advantageous oxygen diffusion barrier layer 62, materials such as silicon dioxide (SiO.sub.2) which would otherwise be unsuitable, can be deposited as the intermetal dielectric layer, without causing undesirable degradation of the electrical characteristics of the capacitor dielectric layer 58. This layer of silicon dioxide, as an intermetal dielectric, can be deposited by a CVD step. Such a process advantageously provides desirable conformality, or smoothing of the resulting top surface in preparation for subsequent fabrication processing steps.
There are various other alternative materials which also can be used in the formation of the intermetal dielectric. Illustrative of such alternative materials are silicon nitride (Si.sub.3 N.sub.4), spin-on-glass, silicon fluoride (SiF.sub.y O.sub.4-y) where y is a number in a range from zero to four, or an organic dielectric, such as polyimide. Spin on dielectrics are inherently planarizing with respect to subsequent fabrication processing steps.
Inherent residual compressive stress in the intermetal dielectric layer 64 is offset either in part or wholly by the residual tensile stress in the crystalline structure of the oxygen diffusion barrier layer 62.
The present invention therefore provides a new device structure and a sequence of processing steps that resolve the dilemma concerning how to take advantage of the favorable qualities of a ferroelectric capacitor dielectric without degrading the electrical characteristics of that ferroelectric material when intermetal dielectric materials such as silicon dioxide are deposited adjacent to the ferroelectric material. There are alternative resolutions to that dilemma.
One alternative is to use a fabrication process of steps represented by FIGS. 1-6, as previously described. It is noted that the bottom and top capacitor plates 54 and 60 together with the capacitor dielectric layer 58 are all deposited and formed into a capacitor, as shown in FIG. 6. Portions of the capacitor dielectric 58 are exposed to material that will be subsequently deposited.
Referring now to FIG. 9, there is shown the result from the next processing step in an alternative processing sequence. A thin layer 66 of oxygen diffusion barrier material is deposited by chemical vapor deposition over the second capacitor plate 60 and the capacitor dielectric 58. This thin layer 66 of diffusion barrier material is the first layer of a multi-layered dielectric stack of diffusion barrier material and insulator. The diffusion barrier material can be selected from the previously mentioned group of diffusion barrier materials for the process of FIGS. 1-8.
FIG. 10 shows the result of the next processing step. A thin layer 68 of insulator material, such as silicon dioxide (SiO.sub.2), is deposited by physical vapor deposition over the thin layer 66 of diffusion barrier material. The thin layer of insulator may be formed of a material selected from the group of alternative insulator materials previously mentioned. This layer of insulator material forms the second layer of the stack of layers.
In FIG. 11 there is shown the result of the next step of the alternative processing sequence. Another thin layer 70 of the selected oxygen diffusion barrier material is deposited by chemical vapor deposition over the layer of insulator 68. This layer of diffusion barrier material forms the third layer of the stack of layers.
FIG. 12 shows the result of deposition by physical vapor deposition of another thin layer 72 of the selected insulator material over the thin layer 70 of diffusion barrier material. This layer of insulator forms the fourth layer of the stack of layers. Additional layers of barrier material and insulator can be used as desired.
Other previously mentioned alternative processing choices for depositing either the barrier layers or the insulator layers are also appropriate choices for the just described multi-layered dielectric stack of diffusion barrier material and insulator.
The alternate layers of diffusion barrier material and insulator have residual tensile stresses and compressive stresses, respectively. By careful design of thicknesses of the layers and the selected parameters for deposition, the tensile and compressive stresses in the respective alternating sequential layers can be made to cancel one another out, so that the net stress is zero or close to zero.
Although depositing the multi-layers of barrier material and insulator may appear to be time consuming and expensive, both processing time and expense can be limited by using a multi-station deposition tool, such as, for example, a Novellus Concept 1 or 2 reactor. In that reactor, the barrier layer material can be deposited in the first station of the reactor and the insulator in the second station in successive deposition steps.
Another advantageous alternative processing sequence which resolves the dilemma of how to process a device successfully with both the ferroelectric material and the silicon dioxide insulator is now described. In this second alternative process, the device proceeds through the sequence of steps represented by FIGS. 1-6, as previously described, to thereby fabricate the first and second capacitor plates 54 and 60 and the capacitor dielectric 58.
Referring now to FIG. 13, there is shown the result of the next step in the second alternative process. A graded barrier layer 74 is deposited by CVD over the second capacitor plate 60 and the capacitor dielectric 58. The deposition starts with a deposit of pure oxygen diffusion barrier material, e.g., Ti.sub.1-x Si.sub.x O.sub.2 with the number x=o. Gradually the composition of the deposition material is varied to increase the value of the number x toward one. When the number x=1, the process is stopped. The deposited material then is silicon dioxide which becomes the top surface of the graded barrier layer. This second alternative processing sequence is best practiced using binary oxides having continuous solubility in one another, e.g., titanium dioxide and silicon dioxide.
FIG. 14 presents a graph that shows the relationships between the quantity of silicon (Si) and either titanium (Ti) or zirconium (Zr) in the graded barrier layer 74 of FIG. 13. Quantity of the elements silicon and titanium in the material Ti.sub.1-x SiO.sub.2 per molar unit of the oxide material is determined on the horizontal axis. Thickness of the graded barrier layer is shown on the vertical axis. The quantity of titanium is represented by the line 80 and goes to zero at the top surface of the layer. The quantity of silicon is represented by the line 82 and goes to zero at the bottom of the layer, i.e., at the surface of the ferroelectric material. The material Zr.sub.1-x Si.sub.x O.sub.2 is presented similarly in the graph of FIG. 14 where the line 80 represents the quantity of zirconium.
Referring now to FIG. 15, there is a graph showing the quantities of silicon and tantalum or niobium in graded barrier layers of either Ta.sub.5-y Si.sub.y O.sub.10 or Nb.sub.5-y Si.sub.y O.sub.10, where y is a number in a range from zero to five. The graph is similar to the graph of FIG. 14 except that line 90 represents the quantity of tantalum or niobium and the line 92 represents the quantity of silicon.
The foregoing describes device structures and methods for processing integrated circuit devices including ferroelectric materials and reducing insulator materials, which avoid adverse degradation of the electrical characteristics of the ferroelectric material.
Accordingly, while the invention has been illustratively described herein with reference to specific aspects, features and embodiments thereof, it will be appreciated that the invention is not thus limited, and therefore is susceptible of other variations, modifications and other embodiments, and all such variations, modifications, and other embodiments are therefore intended to be encompassed within the spirit and scope of the claims hereafter set forth.
Claims
Certificate of Correction present
The claims shown below may not include correction changes. Use the corrected PDF for authoritative text.
What is claimed is:
1. A method of fabricating a capacitor, comprising the steps of: a. depositing and forming a first conductive plate on a substrate; b. depositing and forming a layer of ferroelectric material over the first conductive plate; c. depositing and forming a second conductive plate on the layer of ferroelectric material; d. depositing over the second conductive plate and a part of the ferroelectric material a diffusion barrier material with residual internal tensile stress in its structure; and e. depositing over the diffusion barrier material an insulative material with a residual internal compressive stress in its structure.
2. The method of claim 1 wherein: the ferroelectric material comprises a material selected from the group consisting of PbZrTiO.sub.3 and SrBi.sub.2 Ta.sub.2 O.sub.9.
3. The method of claim 1 wherein: the diffusion barrier layer material comprises a material selected from the group consisting of TiO.sub.2, ZrO.sub.2, Ta.sub.2 O.sub.5, Nb.sub.2 O.sub.5, Zr.sub.1-x Ti.sub.x O.sub.2, where x is a number in a range from zero to one, and Ta.sub.5-y Si.sub.y O.sub.10, Nb.sub.5-y Si.sub.y O.sub.10, where y is a number in a range from zero to five.
4. The method of claim 1 wherein: the diffusion barrier material is deposited by sputtering.
5. The method of claim 1 wherein: the diffusion barrier layer material is deposited by evaporation.
6. The method of claim 1 wherein: the diffusion barrier layer material is deposited by physical vapor deposition (PVD).
7. The method of claim 1 wherein: the insulative layer material is SiO.sub.2 deposited by chemical vapor deposition (CVD).
8. The method of claim 6 wherein: the insulative layer material comprises a material selected from the group consisting of materials including Si.sub.3 N.sub.4, spin-on-glass, SiF.sub.x O.sub.4-z, and an organic dielectric, where z is a number in a range from zero to four and the selected insulative layer material is spun onto the diffusion barrier layer.
9. A method of fabricating a capacitor, comprising the steps of: a. depositing and forming a first conductive plate on a substrate; b. depositing and forming a layer of ferroelectric material over the first conductive plate; c. depositing and forming a second conductive plate on the layer of ferroelectric material; and d. depositing over the second conductive plate a layered dielectric stack with alternating layers of a diffusion barrier material and of an insulative material.
10. The method of claim 9 wherein: stress in the layered dielectric stack is reduced in comparison to a corresponding capacitor structure lacking the layered dielectric stack, by selecting a desirable number of layers, thickness of layers, and/or deposition conditions, so that tensile stresses in the diffusion barrier material and compressive stresses in the insulative material are correspondingly cancelling of one another.
11. The method of claim 9 wherein: the insulative material of the layered dielectric stack is SiO.sub.2 deposited by chemical vapor deposition (CVD).
12. The method of claim 9 wherein: the insulative material of the layered dielectric stack comprises a material selected from the group consisting of Si.sub.3 N.sub.4, spin on glass, SiF.sub.z O.sub.4-z, and an organic dielectric, where z is a number in a range from zero to four and the selected insulative material is spun onto the barrier layer.
13. The method of claim 9 wherein: the diffusion barrier material comprises a material selected from the group consisting of TiO.sub.2, ZrO.sub.2, Ta.sub.2 O.sub.5, and Nb.sub.2 O.sub.5 and is deposited by a process selected from the group consisting of physical vapor deposition (PVD), sputtering, and evaporation.
14. The method of claim 13 wherein: the insulative material comprises a material selected from the group consisting of Si.sub.3 N.sub.4, spin on glass, SiF.sub.z O.sub.4-z, and an organic dielectric, where z is a number in a range from zero to four and the selected insulative material is spun onto the barrier layer.
15. The method of fabricating a capacitor, the method comprising the steps of: a. depositing and forming a first conductive plate on a substrate; b. depositing and forming a layer of ferroelectric material over the first conductive plate; c. depositing and forming a second conductive plate on the layer of ferroelectric material; d. depositing a graded diffusion barrier material on the layer of ferroelectric material, the graded diffusion barrier material having a content defined by Ta.sub.5-y Si.sub.y O.sub.10 or Nb.sub.5-y Si.sub.y O.sub.10 and the number y varying from zero at the surface of the ferroelectric material to five at a desired distance above the surface of the ferroelectric material.
16. The method of fabricating a capacitor, the method comprising the steps of: a. depositing and forming a first conductive plate on a substrate; b. depositing and forming a layer of ferroelectric material over the first conductive plate; c. depositing and forming a second conductive plate on the layer of ferroelectric material; d. depositing a graded diffusion barrier material on the layer of ferroelectric material, the graded diffusion barrier material having a content defined by Zr.sub.1-x SiO.sub.2 and x varying from zero at the surface of the ferroelectric material to one at a desired distance above the surface of the ferroelectric material.
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