Method and Apparatus for DC Compensation

The invention concerns a DC compensation module for suppressing the DC content of a signal containing a periodic sequence, said module comprising a signal transport path, a signal compensation path and a combination unit.

Due to the frequency inaccuracy between portable and fixed parts, component spreading, temperature drift, etc. a DC component will be present at the output of the FM discriminator in a cordless telephone system, such as a DECT system. This DC component must be removed before the signal arrives at a comparator. Otherwise, the bit error rate will increase dramatically.

The invention provides a DC compensation module which suppresses the DC content of a signal containing a periodic sequence. The DC compensation module comprises a signal transport path, a signal compensation path and a combination unit. The signal transport path transfers the signal from the input of the module to an input on the combination unit. The signal compensation path is coupled to another input on the combination unit and is provided with a low pass filter which filters a signal transferred via the signal compensation path. The low pass filter of the signal compensation path is provided with a notch at a frequency corresponding to the period of the periodic signal. The combination unit supplies a signal in response to the difference between the signals received from the signal transport path and from the signal compensation path. The presence of the notch in the low pass filter of the signal compensation path ensures that the frequency of the periodic signal is suppressed significantly or is removed completely, whereby the DC compensation module will have a transfer characteristic such that said frequency will be transferred without significant attenuation. Thus, the DC compensation module of the invention may have a large band width so that DC compensation may be achieved very quickly--right down to a few periods for the periodic signal.

This is of considerable importance in a DECT receiver, where the DC compensation module is placed between an FM discriminator and a comparator. The DC compensation module must be fast and precise within the first part of the preamble.

This characteristic is achieved in a preferred embodiment by subtracting the compensation signal from the transported signal. When the low pass filter of the signal compensation is a 2nd order low pass filter, good balance is ensured between the desirability of low filter cut-off frequency to remove the DC component and the desirability of fast module transient time.

When, in a preferred embodiment, the DC compensation module of the invention is implemented with the low pass filter in a feedback structure, the filter, in a preferred embodiment which is useful in connection with the DECT system, may have a transfer function: H(s)=k.sub.1 (s-z.sub.1)(s-z.sub.1 *)/s(s-p.sub.1)(s-p.sub.2), where k.sub.1 is a real constant, z.sub.1 is an imaginary zero, z.sub.1 * is the complex conjugate of z.sub.1, and p.sub.1 and p.sub.2 are two real values representing the poles of the filter. When z.sub.1 =3.62.times.10.sup.6, the notch will be positioned around 576 kHz.

Instead of being loop filter (feedback) implemented, the DC compensation module of the invention may be implemented by means of a feed forward filter. In this case, the compensation module comprises a branch means which supplies the received signal to the signal transport path and to the signal compensation path, and then the signals are joined again on the input of the subtraction unit, where the difference is determined. If the same effect is to be achieved with the feed forward principle as with the feedback principle, the transfer function of the filter may be designed so that H.sub.1 (s)=H(s)/(1-H(s)), where H(s) is the filter transfer function used in the feedback principle.

In connection with a DECT signal, where data are transmitted in time slot frames, data are begun in these frames with sixteen alternating bits (preamble) followed by a sync word consisting of sixteen bits in a well-known bit pattern and data in the form of a sequence of bits. When the data signal leaves the FM discriminator of the receiver, the preamble will be a sine oscillation having a frequency of 576 kHz, the bit rate of the digital signal being originally twice as high--viz. 1152 kbits/s. It is important in this case that any DC components are removed quickly during the preamble, so that the clock recovery is performed during the last part of the pre- amble. A clock recovery technique is described in the applicant's US patent application filed on the same day as the present application and claiming priority from British patent application 9602585.3 filed Feb. 8, 1996. This parallel US patent application is hereby incorporated by reference in the present application.

In the preferred embodiment, the DC compensation module of the invention, when used in connection with DECT, may be provided with a DC level hold device in the signal compensation path. The DC level hold device, controlled by a monitor device which monitors the periodic signal on the output of the DC compensation device, can thus hold the DC level on the output of the signal compensation path when correct compensation has been achieved. This means that the DC compensation value determined during the preamble is held at least until the termination of the current data burst. Thus, the DC compensation is not changed even if long sequences having the same bit value occur in the sync word or among data.

In practice, it is the clock recovery module which controls the DC compensation module. The bit error rate will be unacceptably high, if the signal from the FM discriminator contains a DC component.

The invention moreover concerns a portable telephone having a DC compensation module to receive a DECT signal having a periodic preamble and having a sequence of binary data in a data burst.

The invention will be explained more fully below in connection with preferred embodiments and with reference to the drawing, in which:

FIG. 1 schematically illustrates how a DC compensation module of the invention in a preferred embodiment is used in a portable telephone;

FIG. 2 shows a preferred embodiment of the DC compensation module of the invention, where the DC compensation module is constructed according to the feedback principle;

FIG. 3 shows an alternative embodiment of the DC compensation module according to the invention, where the DC compensation module is constructed according to the feed forward principle;

FIG. 4 shows the effect of the notch in the filter of the DC compensation module;

FIG. 5 shows the filter characteristic of a filter used in the DC compensation module shown in FIG. 2;

FIG. 6 shows a step response of the filter whose filter characteristic is shown in FIG. 5; and

FIG. 7 shows an example of how the filter used in the embodiment shown in FIG. 3 may be realised.

The invention will be explained more fully below in connection with DC compensation of a signal which is in accordance with the ETSI standards of cordless systems, such as DECT. The invention is not restricted to this specific use. IN a DECT signal, data are transmitted in frames in time slots. Each frame has sixteen initial, alternating bits (preamble), a sync. word likewise consisting of sixteen bits in a different, but well-known bit pattern, and subsequent data. When the data signal leaves the FM discriminator of the receiver, the preamble assumes the form of a periodic signal, it being a sine signal having a frequency of 576 kHz, the bit rate of the digital signal being originally twice as high--viz. 1152 kbits/s. It is important in this case that any DC components are removed quickly during the preamble so that the clock recovery may be performed during the last part of the preamble.

An example of how a DC compensation module of the invention is used in a portable telephone is shown in FIG. 1. A signal is received by an aerial 1, and the signal is passed via an FM discriminator 2 to a DC compensation module 3, where any DC content is removed. The signal is passed from the DC compensation module 3 to a comparator 4, where the signal is one bit quantized before being passed to a clock recovery module 5 via a sampling device 6.

The quantized signal is oversampled in the sampling device 6, and it is then correlated with a predetermined correlation word in the clock recovery module 5. The clock recovery module 5 determines the most expedient sampling time for the subsequent data bits on the basis of the preamble, which is GFSK modulated. On the basis of the correlation signal the clock recovery module 5 determines the most expedient time of holding the DC compensation level in the DC compensation module 5. Then, the DC compensation level is held at a constant value at least for the rest of the data burst.

A preferred embodiment of a DC compensation module 3 of the invention is shown in FIG. 2. The signal received on the input of the module is passed via a signal transport path 10 to a combination unit in the form of a subtraction unit 11, in which a compensation signal is subtracted from the received signal and is then passed to the outlet 12 of the module. A signal compensation path 13 receives the difference signal from the output of the subtraction unit 11, and this difference signal is returned via a low pass filter 14 having the transfer function H(s) and a sample and hold circuit 15 as the compensation signal to the other input of the subtraction unit 11. The clock recovery module locks the DC correction level by means of the sample and hold circuit 15 for at least the rest of the databurst.

The low pass filter 14 may advantageously be a 2nd order low pass filter, and it has a notch at 576 kHz, which is the frequency of the periodic signal provided by the FM discriminator 2. The low pass filter may e.g. have a transfer function:

where k.sub.1 is a real constant, z.sub.1 is an imaginary zero, z.sub.1 * is the complex conjugate of z.sub.1, and p.sub.1 and p.sub.2 are two real values representing the poles of the filter. The actual values may thus be: k.sub.1 =6.0.times.10.sup.5, z.sub.1 =j3.62.times.10.sup.6, z.sub.1 *=j3.62.times.10.sup.6, and p.sub.1 and p.sub.2 are -3.70.times.10.sup.6 and -3.57.times.10.sup.6, respectively.

If the loop filter is too slow, a too great part of the preamble will be used for DC compensation, and the clock recovery will be poor, resulting in a high bit error rate. If the loop is too fast, the noise suppression will be too poor, and the DC compensation will be too imprecise.

FIG. 3 shows an alternative embodiment of the DC compensation module of the invention, the DC compensation module being constructed here according to the feed forward principle. Thus, it will be seen that the signal received on the input of the module is passed via a signal transport path 10 to a combination unit in the form of a subtraction unit 11. A branch means 16 is provided in the signal transport path 10, diving the incoming signal so that a portion is passed to a signal compensation path 13 provided with a low pass filter 17 having a transfer function H.sub.1 (s) and a sample and hold circuit 15. The compensation signal transferred via the signal compensation path 13 is passed to the subtraction unit 11, where it is subtracted from the received signal. The clock recovery module 5 locks the DC correction level by means of the sample and hold circuit for the rest of the data burst. The reference numbers of the components in the two embodiments are the same for essentially the same components.

In this embodiment the low pass filter 17 may have a transfer function:

where H(s) is the transfer function of the low pass filter 14 in the embodiment shown in FIG. 2.

FIG. 4 shows the effect of the notch in the filter 14 in the first embodiment of the DC compensation module of the invention. The upper curve in both diagrams shows the signal (transferred via the signal transport path 10), which is received on the input of the DC compensation module, while the lower curve in the upper diagram shows the signal which would have been transferred via the signal compensation path 13 if the filter 14 had been without a notch. The lower curve in the lower diagram shows the signal which is transferred via the signal compensation path 13 when the filter 14 is provided with a notch. The filter is a 2nd order low pass filter in both cases.

It will be seen clearly from FIG. 4 that the notch makes it possible to eliminate the ripple which would otherwise occur if the notch had not been present. As long as this ripple is present, the sample and hold circuit 15 will introduce a DC error in response to the sampling time concerned. It will also be seen that the compensation signal on the signal compensation path 1 3 reaches its final, stable value after just 4-5 data bits.

FIG. 5 shows the filter characteristic for the feed forward filter 14 used in the embodiment of the DC compensation module of the invention shown in FIG. 2. The notch 20 is seen clearly at 576 kHz. The step response of the filter is shown in FIG. 6.

FIG. 7 shows an example of how the filter 17 used in the alternative embodiment shown in FIG. 3 may be constructed. It will be seen that the filter 17 may be constructed very simply, as, in practice, it may comprise just a parallel coupling of an inductance L and a capacity C.sub.1 serially connected to a resistor R, and with a further capacitor C.sub.2 arranged above the output. The values of the components may be L=82 .mu.H, C.sub.1 =1nF, R=150 .OMEGA., and C.sub.2 =12nF.

The present invention includes any novel feature or combination of features disclosed herein either explicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigates any or all of the problems addressed.

In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.