Method for Producing a CMOS Circuit

1. Field of the Invention

The present invention relates to a method for producing a CMOS circuit having both an n-channel MOS transistor and a p-channel MOS transistor formed in a semiconductor substrate wherein a masking step is alleviated in the formation of the CMOS circuit thus reducing the overall process outlay.

2. Description of the Prior Art

In the course of miniaturizing components with a view toward increased component density, both lateral and vertical dimensions are reduced. In the case of MOS transistors, this means that not only the lateral dimensions of the gate electrode and the channel length but also the depth of the source/drain regions is reduced.

EP 0 268 941 B1 has proposed a MOS field-effect transistor structure with shallow source/drain zones. The MOS field-effect transistor is arranged between field oxide regions. Monocrystalline, doped silicon layers are arranged between the gate electrode of the MOS transistor and the field oxide regions. Such silicon layers are produced by means of selective epitaxy and service as diffusion sources for producing the source/drain regions. They also form the connection regions with respect to the source/drain terminals arranged above them.

In order to produce a CMOS circuit with complementary MOS transistors, it was proposed in EP 0 268 941 B1, that the monocrystalline doped silicon layers produced by means of selective epitaxy be doped differently. This can be done either by forming an undoped silicon layer or by means of selective epitaxy, both in the region of the n-channel transistors and in the region of the p-channel transistors. The silicon layers are then doped differently, depending on the transistor type, by means of implantation using two masks. As an alternative, n.sup.+ -doped, monocrystalline silicon layers are, first of all, produced by means of selective epitaxy. In this case, regions for p-channel transistors are covered by a mask. Afterwards, the regions for n-channel transistors are covered by a further mask and p.sup.+ -doped n-crystalline silicon layers are formed by means of selective epitaxy. In both cases, two mask steps are necessary to produce the differently doped source/drain regions.

The present invention, therefore, is based on the problem of specifying a method for producing a CMOS circuit in which the process outlay is reduced. According to the principles of the present invention, such problem is solved by the fact that an n-channel MOS transistor and a p-channel -MOS transistor are formed in a semiconductor substrate. In order to form the p-channel MOS transistor, a first gate dielectric and a first gate electrode, whose flanks are provided with insulating spacers, are produced. Therefore, p-doped, monocrystalline silicon structures are formed, by means of selective epitaxy, laterally with respect to the first gate electrode. The p-doped, monocrystalline silicon structures are suitable as a diffusion source for forming source/drain regions of the p-channel MOS transistor. In this case, the selective epitaxy is carried out in such a way that deposition of silicon on surfaces made of insulating material and made of n-doped silicon is suppressed. This exploits the fact that silicon deposition takes place more slowly by a factor of 5 to 20 in the case of in situ n-doped selective epitaxy than in the case of undoped selective epitaxy or in situ p-doped selective epitaxy. During the selective epitaxy for forming p-doped, monocrystalline silicon structures, n-doped silicon regions act locally as a dopant source on the surface of which only n-doped silicon can grow. As a result of this measure, n-doped silicon regions, or regions made of insulated material, need not be covered with a separate mask while the p-doped monocrystalline silicon structures are formed. In this way, a mask is saved in the formation of the CMOS circuit. That means a reduced process outlay.

According to the present invention, after the formation of the first gate dielectric and the first gate electrode for the p-channel MOS transistor, and after the formation of a second gate dielectric and a second gate electrode for the n-channel MOS transistor, whose flanks are provided with insulating spacers, a mask is formed which covers an active region for the p-channel MOS transistor. n-doped source/drain regions for the n-channel MOS transistor are subsequently formed by means of ion implantation. After the removal of the mask, the selective epitaxy for forming the p-doped, monocrystalline silicon structures is carried out. Finally, the source/drain regions of the p-channel MOS transistor are formed by outdiffusion from the p-doped, monocrystalline silicon structures.

In a further embodiment, after the formation of the first gate dielectric, first gate electrode, second gate dielectric and second gate electrode for the p-channel MOS transistor and the n-channel MOS transistor, and after the production of insulating spacers on the flanks of the first gate electrode and of the second gate electrode, a mask is formed which covers the active region of the p-channel MOS transistor. n-doped monocrystalline silicon structures are formed by means of selective epitaxy and are suitable as a diffusion source for forming source/drain regions of the n-channel MOS transistor. Afterwards, the mask is removed and the selective epitaxy for forming the p-doped, monocrystalline silicon structures is carried out. Since this selective epitaxy is selective with respect to insulating material and with respect to n-doped silicon, the p-doped, monocrystalline silicon structures do not grow in the region of the n-channel MOS transistor. The source/drain regions of the p-channel MOS transistor are formed by outdiffusion from the p-doped, monocrystalline silicon structures, and the source/drain regions of the n-channel MOS transistor are formed by outdiffusion from the n-doped, monocrystalline silicon structures.

In both exemplary embodiments, in the manner that is customary in CMOS technology, insulation structures are formed which, in each case, define the active regions for the n-channel MOS transistors and the p-channel MOS transistors. Furthermore, if necessary, n-doped wells and/or p-doped wells for accommodating the p-channel MOS transistors and/or n-channel MOS transistors are produced and channel implantations are performed.

The selective epitaxy for forming the p-doped, monocrystalline silicon structures is preferably effected using a process gas containing H.sub.2, HC1, SiH.sub.2 Cl.sub.2 and B.sub.2 H.sub.6 in the temperature range between 700 and 900.degree. C. and in the pressure range between 1 and 700 torr. Source/drain regions having a depth between 10 and 50 nm can be formed in this way. It lies within the scope of the invention to form the mask from a mask layer, especially one made of SiO.sub.2, which is structured with the aid of photolithographic processing steps.

Additional features and advantages of the present invention are described, and will be apparent from, the Detailed Description of the Preferred Embodiments and from the Drawings.

FIG. 1 shows a section through a semiconductor substrate with insulation structures and both an n-doped well and a p-doped well.

FIG. 2 shows a section through the semiconductor substrate after the formation of a gate dielectric and gate electrodes, whose flanks are provided with insulating spacers.

FIG. 3 shows a section through the semiconductor substrate after the formation of a mask and ion implantation for forming n-doped source/drain regions.

FIG. 4 shows a section through the semiconductor substrate after the removal of the mask, the formation of p-doped, monocrystalline silicon structures and the formation of p-doped source/drain regions by outdiffusion from the silicon structures.

FIG. 5 shows a section through a second embodiment of a semiconductor substrate with insulation structures, an n-doped well and a p-doped well.

FIG. 6 shows a section through the semiconductor substrate after the formation of a gate dielectric and gate electrodes, whose flanks are provided with insulating spacers.

FIG. 7 shows a section through the semiconductor substrate after the reoxidation step.

FIG. 8 shows a section through the semiconductor substrate after the formation of a mask.

FIG. 9 shows a section through the semiconductor substrate after the growth of n-doped, monocrystalline silicon structures and after the removal of the mask.

FIG. 10 shows a section through the semiconductor substrate after etching to expose the semiconductor surface in the region of the n-doped well.

FIG. 11 shows the semiconductor substrate after the selective growth of p-doped, monocrystalline silicon structures and after a heat-treatment step for forming source/drain regions.

As shown in FIG. 1, insulation structures 12 are formed on a surface of a substrate; for example, of a monocrystalline silicon wafer or of the monocrystalline silicon layer of an adjacent SOI substrate. The insulation structures 12 are formed, for example, by local oxidation in a LOCOS process or by filling insulating trenches in a shallow trench insulation process (STI). Furthermore, a p-doped well 13 and an n-doped well 14 are formed in the substrate 11. The insulation structures 12 are configured in such a way that they define an active region for an n-channel MOS transistor within the p-doped well 13 and an active region for a p-channel MOS transistor within the n-doped well 14.

Referring now to FIG. 2, a first gate dielectric 15 and a first gate electrode 16 for the p-channel MOS transistor and a second gate dielectric 17 and a second gate electrode 18 for the n-channel MOS transistor are subsequently formed by whole-area application of a dielectric layer and of a conductive layer and joint structuring by means of photolithographic process steps and anisotropic etching. The first gate dielectric 15 and the second gate dielectric 17 are formed, for example, by thermal oxidation from SiO.sub.2 with a layer thickness of 5 nm. The first gate electrode 16 and the second gate electrode 18 are formed, for example, from doped polysilicon and/or metal silicide with a layer thickness of 200 nm.

Insulating spacers 19 are subsequently formed on the flanks of the first gate electrode 16 and of the second gate electrode 18 by means of conformal deposition of an insulating layer. Such layer may be made, for example, of SiO.sub.2 or Si.sub.3 N.sub.4, with a layer thickness of 10 to 500 nm, and by means of anisotropic etching back.

As shown in FIGS. 3 and 4, a mask 110, which completely covers the active region for the p-channel MOS transistor, is formed by whole-area deposition of an SiO.sub.2 layer to a layer thickness of 100 to 3000 nm, for example, and subsequent structuring by means of photolithographic process steps and anisotropic etching. The active region for the n-channel MOS transistor, on the other hand, is left uncovered by the mask 110. Source/drain regions 111 for the n-channel MOS transistor are subsequently formed by means of ion implantation using, for example, arsenic with an energy of 5 to 80 keV and a dose of 10.sup.14 to 10.sup.21 cm.sup.-2.

After the removal of the mask 110 by etching in hydrofluoric acid, for example, and after preparatory cleaning steps which are necessary for epitaxy, p-doped monocrystalline silicon structures 112 are formed on the uncovered surface of the n-doped well 14 by means of in situ p-doped selective epitaxy. The process parameters are set in such a way that during the selective epitaxy, silicon is not deposited either on insulating material or on n-doped silicon. To that end, a process gas containing H2, HCl, SiH.sub.2 Cl.sub.2, B.sub.2 H.sub.6 is used. The selective epitaxy is carried out at a temperature in the range between 700 and 900.degree. C. and at a pressure in the range between 1 and 700 torr. A dopant concentration of about 10.sup.20 cm.sup.-3 is set here in the p-doped, monocrystalline silicon structures 112.

A heat-treatment process is subsequently effected, during which source/drain regions 113 for the p-channel MOS transistor are formed by outdiffusion from the p-doped, monocrystalline silicon structures 112. At the same time, the dopant in the source/drain regions 111 for the n-channel MOS transistor is activated. The depth of the source/drain regions 111 for the n-channel MOS transistor is about 20 to 200 nm, and the depth of the source/drain regions for the p-channel MOS transistor 113 is about 20 to 300 nm.

In further exemplary embodiment as shown in FIG. 5, an insulation structure 22, a p-doped well 23 and an n-doped well 24 are formed in a substrate 21, in a manner analogous to the first exemplary embodiment. The substrate 21 is once again a monocrystalline silicon wafer or a monocrystalline silicon layer of an SOI substrate. The insulation structure 22 is formed in a LOCOS process or in an STI process, for example. The insulation structure 22 is designed in such a way that it defines an active region for an n-channel MOS transistor in the p-doped well 23 and an active region for a p-channel MOS transistor in the n-doped well 24. In an analogous manner to that in the first exemplary embodiment, FIG. 6 shows a first gate dielectric 25 and a first gate electrode 26 are formed for the p-channel MOS transistor, and a second gate dielectric 27 and a second gate electrode 28 are formed for the n-channel MOS transistor. Insulating spacers 29 are formed on the flanks of the gate electrodes 26, 28.

Reoxidation is subsequently carried out at 800 to 1100.degree. C., for example. As shown in FIG. 7, during the reoxidation process an SiO.sub.2 layer 214 is formed with a layer thickness of about 5 to 100 nm on uncovered surfaces of the p-doped well 23, the n-doped well 24, the first gate electrode 26 and the second gate electrode 28.

Referring now to FIG. 8, a mask 210, which covers the active region for the p-channel MOS transistor, is subsequently formed by application of an SiO.sub.2 layer with a layer thickness of 100 to 3000 nm, for example, and structuring of the SiO.sub.2 layer with the aid of photolithographic methods and by means of anisotropic etching. The active region for the n-channel MOS transistor, on the other hand, is not covered by the mask 210. During the structuring of the mask 210, the surface of the p-doped well 23 is uncovered between the parts of the insulation structure 22 and the insulating spacers 29. n-doped, monocrystalline silicon structures 215 are produced by means of selective epitaxy using a process gas containing H.sub.2, HCl, SiH.sub.2 Cl.sub.2, AsH.sub.3 at a temperature in the range between 700 and 900.degree. C. and a pressure in the range between 1 and 700 torr. The epitaxy is controlled in such a way that silicon is deposited selectively on the uncovered silicon surface of the p-doped well 23 as shown in FIG. 9. By addition of the doping gas AsH.sub.3, the n-doped, monocrystalline silicon structures 215 are in situ n-doped with a dopant concentration of approximately 10.sup.19 cm.sup.-3.

The mask 210 is subsequently removed by etching, for example in hydrofluoric acid. Those parts of the SiO.sub.2 layer 114 which are situated in the region of the active region for the p-channel MOS transistor are subsequently removed by means of selective etching using HF. The uncovered silicon surface of the n-doped well 14 is cleaned, as shown in FIG. 10, for subsequent epitaxy.

As noted in FIG. 11, p-doped, monocrystalline silicon structures 212 are formed on the uncovered surface of the n-doped well 24 by means of selective epitaxy of silicon doped in situ with boron. The selective epitaxy is carried out in such a way that silicon is not deposited either on the surface of insulating material or on the surface of n-doped silicon. To that end, a process gas containing H.sub.2, HCl, SiH.sub.2 Cl.sub.2, B.sub.2 H.sub.6 is used and the epitaxy is carried out at a temperature in the range between 700 and 900.degree. C. and a pressure between 1 and 700 torr. By the addition of the doping gas B.sub.2 H.sub.6 during the selective epitaxy, a dopant concentration of about 10.sup.20 cm.sup.-3 is established in the p-doped, monocrystalline silicon structure 212.

Source/drain regions 211 for the n-channel MOS transistor and source/drain regions 213 for the p-channel MOS transistor are formed in a heat-treatment step at 800 to 1100.degree. C. The depth of the source/drain regions 111 for the n-channel MOS transistor is approximately 20 to 200 nm, and the depth of the source/drain regions 213 for the p-channel MOS transistor is about 20 to 300 nm.

Although the present invention has been described with reference to specific embodiments, those of skill in the art will recognize that changes may be made thereto without departing from the spirit and scope of the invention as set forth in the hereafter appended claims.