Capacitor Structure for a Semiconductor Memory Device

1. Field of the Invention

This invention relates in general to semiconductor memory devices, and more particularly to a charge storage capacitor structure of a dynamic random access memory (DRAM) cell that also includes a transfer transistor.

2. Description of the Related Art

FIG. 1 is a circuit diagram of a memory cell for a DRAM device. As shown in the drawing, a DRAM cell is substantially composed of a transfer transistor T and a charge storage capacitor C. A source of the transfer transistor T is connected to a corresponding bit line BL, and a drain thereof is connected to a storage electrode 6 of the charge storage capacitor C. A gate of the transfer transistor T is connected to a corresponding word line WL. An opposing electrode 8 of the capacitor C is connected to a constant power source. A dielectric film 7 is provided between the storage electrode 6 and the opposing electrode 8.

In the DRAM manufacturing process, a two-dimensional capacitor called a planar type capacitor is mainly used for a conventional DRAM having a storage capacity less than 1M (mega=million) bits. In the case of a DRAM having a memory cell using a planar type capacitor, electric charges are stored on the main surface of a semiconductor substrate, so that the main surface is required to have a large area. This type of a memory cell is therefore not suitable for a DRAM having a high degree of integration. For a high integration DRAM, such as a DRAM with more than 4M bits of memory, a three-dimensional capacitor, called a stacked-type or a trench-type capacitor, has been introduced.

With stacked-type or trench-type capacitors, it has been made possible to obtain a larger memory in a similar volume. However, to realize a semiconductor device of an even higher degree of integration, such as a very-large-scale integration (VLSI) circuit having a capacity of 64M bits, a capacitor of such a simple three-dimensional structure as the conventional stacked-type or trench-type, turns out to be insufficient.

One solution for improving the capacitance of a capacitor is to use the so-called fin-type stacked capacitor, which is proposed by Ema et al., in "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", International Electron Devices Meeting, pp. 592-595, Dec. 1988. The fin-type stacked capacitor includes electrodes and dielectric films which extend in a fin shape in a plurality of stacked layers. DRAMs having the fin-type stacked capacitor are also disclosed in U.S. Pat. Nos. 5,071,783 (Taguchi et al.); 5,126,810 (Gotou); 5,196,365 (Gotou); and 5,206,787 (Fujioka).

Another solution for improving the capacitance of a capacitor is to use the so-called cylindrical-type stacked capacitor, which is proposed by Wakamiya et al., in "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70. The cylindrical-type stacked capacitor includes electrodes and dielectric films which extend in a cylindrical shape to increase the surface areas of the electrodes. A DRAM having the cylindrical-type stacked capacitor also is disclosed in U.S. Pat. No. 5,077,688 (Kumanoya et al.).

With the trend toward increased integration density, the size of the DRAM cell in a plane (the area it occupies in a plane) must be further reduced. Generally, a reduction in the size of the cell leads to a reduction in charge storage capacity (capacitance). Additionally, as the capacitance is reduced, the likelihood of soft errors arising from the incidence of .alpha.-rays is increased. Therefore, there is still a need in this art to design a new structure of a storage capacitor which can achieve the same capacitance, while occupying a smaller area in a plane, and a suitable method of fabricating the structure.

It is therefore an object of the invention to provide a semiconductor memory device which is structured with a tree-type capacitor that allows an increased area for charge storage.

In accordance with the foregoing and other objects of the invention, a new and improved semiconductor memory device is provided.

A semiconductor memory device according to the invention includes a substrate and a transfer transistor on the substrate, the transfer transistor having source/drain regions. The device also includes a storage capacitor electrically connected to one of the source/drain regions of the transfer transistor. The storage capacitor includes a trunk-like conductive layer having a bottom end electrically connected to one of the source/drain regions. The trunk-like conductive layer further has an upright extension which extends substantially upright from the bottom end. The storage capacitor also includes at least one branch-like conductive layer with an L-shaped cross section. One end of the branch-like conductive layer is connected to an inner surface of the trunk-like conductive layer. The trunk-like conductive layer and the branch-like conductive layer together form a storage electrode of the storage capacitor.

The storage capacitor further includes a dielectric layer, formed on the exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and an upper conductive layer on the dielectric layer serving as an opposing electrode of the storage capacitor.

According to another aspect of the invention, the trunk-like conductive layer includes a lower trunk-like portion electrically connected to one of the source/drain regions of the transfer transistor, and an upper trunk-like portion extending substantially upright from an edge of the lower trunk-like portion. The lower trunk-like portion can be either T-shaped or U-shaped in cross section, and the upper trunk-like portion forms a substantially hollow cylinder following the periphery of the lower trunk-like portion.

According to another aspect of the invention, the semiconductor memory device includes a substrate and a transfer transistor formed on the substrate, the transfer transistor having source/drain regions. The device further includes a storage capacitor electrically connected to one of the source/drain regions of the transfer transistor. The storage capacitor includes a trunk-like conductive layer having a bottom end electrically connected to one of the source/drain regions. The trunk-like conductive layer further has an extension that extends substantially upright from the bottom end. The storage capacitor also includes at least one branch-like conductive layer including at least a first extended segment and a second extended segment, wherein one end of the first extended segment connects to the inner surface of the trunk-like conductive layer, and the second extended segment extends from another end of the first extended segment at a determined angle. The trunk-like conductive layer and the branch-like conductive layer form the storage electrode of the storage capacitor, which further includes a dielectric layer formed on exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and an upper conductive layer formed on the dielectric layer, serving as an opposing electrode of the storage capacitor.

According to another aspect of the invention, the semiconductor memory device includes a substrate and a transfer transistor formed on the substrate, the transfer transistor having source/drain regions. The device also includes a storage capacitor electrically connected to one of the source/drain regions of the transfer transistor. The storage capacitor includes a trunk-like conductive layer having a bottom end electrically connected to one of the source/drain regions. The trunk-like conductive layer further has a pillar extension which extends substantially upright from the bottom end. The storage capacitor also includes at least one branch-like conductive layer having one end connected to the inner surface of the trunk-like conductive layer and having an outward extension extending from the other end. The trunk-like conductive layer and the branch-like conductive layer form a storage electrode of the storage capacitor, which further includes a dielectric layer formed on the exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer and an upper conductive layer formed on the dielectric layer, serving as an opposing electrode of the storage capacitor.

According to another aspect of the invention, the semiconductor memory device includes a substrate and a transfer transistor formed on the substrate. The transfer transistor includes source/drain regions. The device also includes a storage capacitor electrically connected to one of the source/drain regions of the transfer transistor. The storage capacitor includes a trunk-like conductive layer having a bottom end electrically connected to one of the source/drain regions. The trunk-like conductive layer further has an upright extension which extends substantially upright from the bottom end. The storage capacitor also includes at least one branch-like conductive layer formed as a substantially hollow cylinder. One end of the branch-like conductive layer is connected to the upper surface of the trunk-like conductive layer. The trunk-like conductive layer and the branch-like conductive layer form a storage electrode of the storage capacitor, which further includes a dielectric layer formed on the exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer, and an upper conductive layer formed on the dielectric layer, serving as an opposing electrode of the storage capacitor.

According to another aspect of the invention, the semiconductor memory device includes a substrate and a transfer transistor formed on the substrate, the transfer transistor having source/drain regions. The device also includes a storage capacitor electrically connected to one of the source/drain regions of the transfer transistor. The storage capacitor includes a trunk-like conductive layer having a bottom end electrically connected to one of the source/drain regions. The trunk-like conductive layer further has an upright extension which extends substantially upright from the bottom end. The storage capacitor also includes a first branch-like conductive layer having an end connected to the upper surface of the trunk-like conductive layer, and having an upright extension which extends substantially upright from the end. The storage capacitor further includes at least a second branch-like conductive layer having an end connected to the inner surface of the trunk-like conductive layer, and having an outward extension which extends substantially outwardly from the end. The trunk-like conductive layer and the branch-like conductive layer form a storage electrode of the storage capacitor which also includes a dielectric layer formed on the exposed surface of the trunk-like conductive layer and the branch-like conductive layer and an upper conductive layer formed on the dielectric layer, serving as an opposing electrode of the storage capacitor.

Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which:

FIG. 1 is a circuit diagram of a memory cell of a DRAM device;

FIGS. 2A through 2H are cross-sectional views depicting the structure of a first embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIG. 3A through 3E are cross-sectional views depicting the structure of a second embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 4A through 4D are cross-sectional views depicting the structure of a third embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 5A through 5C are cross-sectional views depicting the structure of a fourth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 6A through 6D are cross-sectional views depicting the structure of a fifth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 7A through 7D are cross-sectional views depicting the structure of a sixth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 8A through 8E are cross-sectional views depicting the structure of a seventh embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention;

FIGS. 9A through 9E are cross-sectional views depicting the structure of an eighth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention; and

FIGS. 10A through 10D are cross-sectional views depicting the structure of a ninth embodiment of a semiconductor memory cell having a tree-type capacitor according to the invention.

First Preferred Embodiment

The first preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 2A through FIG. 2H.

Referring to FIG. 2A, the surface of a silicon substrate 10 is first thermally oxidized by, for example, a local oxidation of silicon (LOCOS) technique. Therefore, a field oxide layer 12 with a thickness of about 3000 angstroms is formed on the surface of the silicon substrate 10. Next, a thermal oxidation processing is again performed, to form a gate oxide layer 14 with a thickness of about 150 angstroms on the surface of the silicon substrate 10. Then, by using chemical vapor deposition (CVD) technique or low pressure chemical vapor deposition (LPCVD), a polysilicon layer with a thickness of about 2000 angstroms is deposited over all the surface of the silicon substrate 10. To improve the conductivity of the polysilicon layer, phosphorus ions can be implanted into the polysilicon layer. Preferably, a refractory metal layer is deposited and an annealing process is performed to form a polycide layer. Consequently, the conductivity is further enhanced. The refractory metal can be, for example, tungsten, deposited to a thickness of 2000 angstroms. Thereafter, a conventional photolithography and etching technique is performed in order to pattern the polycide layer. Therefore, gates WL1 to WL4 (or word lines WL1 to WL4) are formed as shown in FIG. 2A. Next, arsenic ions are implanted into the substrate 10 to form drain regions 16a, 16b, and source regions 18a, 18b. During this implantation step, the word lines WL1 to WL4 are used as mask layers and the ions are implanted with a dosage of about 10.sup.15 atoms/cm.sup.2 at an energy level of about 70 KeV.

Referring next to FIG. 2B, a planarized insulating layer 20, such as borophosphosilicate glass (BPSG) with a thickness of about 7000 angstroms, is deposited by CVD. Then, an etching protection layer 22, such as a silicon nitride layer with a thickness of about 1000 angstroms, is also formed by CVD. Thereafter, using conventional photolithography and etching techniques, the etching protection layer 22, the planarized insulating layer 20, and the gate oxide layer 14 are etched in succession. Contact holes 24a, 24b for storage electrodes are therefore formed on the top surface of the etching protection layer 22, extending to the surface of the drain regions 16a, 16b. Next, a polysilicon layer 26 is deposited. Preferably, arsenic ions can be implanted into the polysilicon layer 26 to increase the conductivity. As shown in FIG. 2B, the polysilicon layer 26 completely fills the contact holes 24a, 24b and also overlays the surface of the etching protection layer 22.

Referring to FIG. 2C, a thick insulating layer, such as a silicon dioxide layer with a thickness of about 7000 angstroms, is subsequently deposited over the polysilicon layer 26. Conventional photolithography and etching techniques are performed to pattern the insulating layer, such that insulating pillars 28a, 28b are formed as shown in FIG. 2C. The insulating pillars 28a, 28b are preferably located above the drain regions 16a and 16b, respectively, on the polysilicon layer 26. Gaps 29 are thus formed between the insulating pillars 28a, 28b.

Referring to FIG. 2D, by CVD, an insulating layer 30, a polysilicon layer 32, and an insulating layer 34 are formed in succession. The insulating layers 30 and 34 can be, for example, silicon dioxide. The thickness of each of the insulating layer 30 and the polysilicon layer 32 can be, for example, about 1000 angstroms. The thickness of the insulating layer 34 is preferably such that it is able to at least fully fill the gaps 29 between the insulating pillars 28a and 28b. In accordance with the first preferred embodiment, the thickness of the insulating layer 34 is about 7000 angstroms. In order to increase the conductivity of the polysilicon layer 32, arsenic ions may be implanted into the polysilicon layer 32.

Referring to FIG. 2E, the surface of the structure as shown in FIG. 2D is polished by a chemical mechanical polish (CMP) technique until at least the top of the insulating pillars 28a, 28b are exposed.

Referring to FIG. 2F, using conventional photolithography and etching techniques, the insulating layer 34, the polysilicon layer 32, the insulating layer 30, and the polysilicon layer 26 are etched to form an opening 36; the storage electrode of the storage capacitor for each memory cell is now defined by the placement of the conductive layers. Also by the above-mentioned etching step, the polysilicon layers 32 and 26 are divided into segments 32a, 32b, and 26a, 26b, respectively. Then, polysilicon spacers 38a, 38b are formed on the sidewalls of the openings 36. In accordance with the first preferred embodiment, the polysilicon spacers 38a, 38b may be formed by forming a polysilicon layer with a thickness of about 1000 angstroms and etching back the polysilicon layer to form the spacers 38a, 38b. Arsenic ions can be implanted into the polysilicon layer to increase the conductivity of the polysilicon spacers 38a, 38b.

Referring to FIG. 2G, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 34, 30, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 2G includes the lower trunk-like polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 38a, 38b, and the branch-like polysilicon layers 32a, 32b, which are substantially L-shaped in cross section. The lower trunk-like polysilicon layers 26a, 26b directly contact the drain regions 16a, 16b of the transfer transistor, respectively. The cross sections of the lower polysilicon layers 26a, 26b are T-shaped. The upper trunk-like polysilicon layers 38a, 38b connect to the edges of the lower trunk-like polysilicon layers 26a, 26b, respectively, and stand substantially vertically, that is, normal to the surface of the etching protection layer 22. The upper trunk-like polysilicon layers 38a, 38b form hollow cylinders, and the cross sections of which can be circular or rectangular. The branch-like polysilicon layers 32a, 32b connect to the inner surfaces of the upper polysilicon layers 38a, 38b, respectively, and first extend horizontally inward, that is, toward the drain regions, for a determined distance and then extend vertically upright. The term "tree-type storage electrode" refers herein to the complete storage electrode according to the invention, since its structure is unusual. The capacitor including the "tree-type storage electrode" is therefore called the "tree-type storage capacitor".

Referring to FIG. 2H, dielectric films 40a, 40b are formed on the surface of the storage electrodes (26a, 32a, 38a) and (26b, 32b, 38b), respectively. Each dielectric film 40a, 40b may be, for example, a silicon dioxide layer, a silicon nitride layer, an NO structure (silicon nitride/silicon dioxide), or an ONO structure (silicon dioxide/silicon nitride/silicon dioxide). Then, opposing electrodes 42 made of polysilicon are formed on the surface of the dielectric films 40a, 40b. The opposing electrodes are fabricated by forming a polysilicon layer with a thickness of, for example, 1000 angstroms, by CVD, doping the polysilicon layer with, for example, an N-type dopant to increase the conductivity, and patterning the polysilicon layer using conventional photolithography and etching techniques. The storage capacitor of the DRAM cell is then complete.

Though it is not shown in FIG. 2H, it is clear to persons skilled in the art that word lines bonding pads, interconnections, passivations, and packages may be fabricated according to conventional processes to complete the DRAM IC. Because these conventional processes are not related to characteristics of the invention, is not necessary to describe these processes in detail.

In the first embodiment, the lowest polysilicon layer 26 is divided into lower trunk-like polysilicon layers 26a, 26b for each memory cell, as shown in FIG. 2F. However, in accordance with another preferred embodiment of the invention, the polysilicon layer 26 may be patterned to be lower trunk-like polysilicon layers 26a, 26b for each memory cell just after the polysilicon layer 26 is deposited, as shown in FIG. 2B. The further processes are then performed similarly as described above.

Second Preferred Embodiment

In the first embodiment, each storage electrode includes only one branch-like electrode layer that is substantially L-shaped in cross section. However, the invention is not limited in scope to this particular embodiment. The number of substantially L-shaped branch-like electrodes can be two, three, or more. A storage electrode with two branch-like electrode layers substantially L-shaped is described, as the second preferred embodiment.

The second preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 3A through FIG. 3E.

The tree-type storage capacitor of the second embodiment is based on the wafer structure of FIG. 2C. Elements in FIGS. 3A through 3E that are identical to those in FIG. 2C are labeled with the same reference numerals.

Referring to FIGS. 2C and 3A, CVD is performed to alternately form insulating layers and polysilicon layers, in particular, an insulating layer 44, a polysilicon layer 46, an insulating layer 48, a polysilicon layer 50, and an insulating layer 52 in succession, as shown in FIG. 3A. The insulating layers 44, 48, and 52 can be, for example, silicon dioxide. The thickness of the insulating layers 44, 48, and the polysilicon layers 46, 50 can be, for example, 1000 angstroms. The thickness of the insulating layer 52 can be, for example, 7000 angstroms and preferably fills the gaps 29 between the insulating pillars 28a, 28b. To improve the conductivity of the polysilicon layers, ions such as arsenic can be implanted into the polysilicon layers.

Referring to FIG. 3B, a CMP technique can be utilized to polish the surface of the structure shown in FIG. 3A until at least the tops of the insulating pillars 28a, 28b are exposed.

Referring to FIG. 3C, conventional photolithography and etching techniques are utilized to etch the insulating layer 52, the polysilicon layer 50, the insulating layer 48, the polysilicon layer 46, the insulating layer 44, and the polysilicon layer 26 in succession; thus, an opening 54 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 50, 46, and 26 are divided into segments 50a, 50b, 46a, 46b and 26a, 26b, respectively. Then, polysilicon spacers 56a, 56b are formed on the sidewalls of the opening 54. In according with the second preferred embodiment, the polysilicon spacers 56a, 56b may be formed by forming a polysilicon layer with a thickness of about 1000 angstroms and etching back the polysilicon layer to form spacers 56a, 56b. Arsenic ions can be implanted into the polysilicon layer to increase the conductivity of the polysilicon spacers 56a, 56b.

Referring to FIG. 3D, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 52, 48, and 44, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 3D includes the lower trunk-like polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 56a, 56b, and the two layers of branch-like polysilicon 46a, 50a, 46b, 50b, which are substantially L-shaped in cross section. The lower trunk-like polysilicon layers 26a, 26b directly contact the drain regions 16a, 16b of the transfer transistor, respectively. The cross sections of the lower polysilicon layers 26a, 26b are T-shaped. The upper trunk-like polysilicon layers 56a, 56b connect to the edges of the lower trunk-like polysilicon layers 26a, 26b, respectively, and stands substantially vertically. The upper trunk-like polysilicon layers 56a, 56b are formed as hollow cylinders, the cross sections of which can be circular or rectangular. The two layers of the branch-like polysilicon 46a, 50a, 46b, 50b connect to the inner surfaces of the upper polysilicon layers 56a, 56b, respectively, and first extend horizontally inward for a determined distance, and then extend vertically upright.

Referring to FIG. 3E, dielectric films 58a, 58b are formed on the surface of the storage electrodes (26a, 46a, 50a, 56a) and (26b, 46b, 50b, 56b), respectively. Then, opposing electrodes 60 made of polysilicon are formed on the surface of the dielectric films 58a, 58b. The opposing electrodes are fabricated by forming a polysilicon layer with a thickness of, for example, 1000 angstroms, by CVD, doping the polysilicon layer with, for example, an N-type dopant to increase the conductivity, and patterning the polysilicon layer using conventional photolithography and etching techniques. The storage capacitor of the DRAM cell is then complete.

Third Preferred Embodiment

In the first and second preferred embodiments, the branch-like electrode layers of the storage electrode have L-shaped cross sections. However, the invention is not limited thereto. A branch-like electrode layer having a pillar-shaped cross section will be described, as the next preferred embodiment.

The third preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 4A through FIG. 4D.

The tree-type storage capacitor of the third embodiment is based on the wafer structure of FIG. 2C and includes further elements. Elements in FIGS. 4A through 4D that are identical to those in FIG. 2C are labeled with the same reference numerals.

Referring to FIGS. 2C and 4A, polysilicon spacers 62a, 62b are formed on the sidewalls of the insulating pillars 28a, 28b. According to the third preferred embodiment, the polysilicon spacers 62a, 62b are fabricated by depositing a polysilicon layer with a thickness of about 1000 angstroms and etching back the polysilicon layer to form the spacers 62a, 62b. To improve the conductivity of the polysilicon layer, ions such as arsenic can be implanted into the polysilicon layer. Then, CVD is performed to deposit a thick insulating layer 64. Preferably, the gap between the insulating pillars 28a, 28b is therefore filled.

Referring to FIG. 4B, a CMP technique is utilized to polish the surface of the structure shown in FIG. 4A, preferably until the tops of the insulating pillars 28a, 28b and the polysilicon spacers 62a, 62b are exposed.

Referring to FIG. 4C, conventional photolithography and etching techniques are utilized to etch the thick insulating layer 64 and the polysilicon layer 26 in succession; thus, an opening 66 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layer 26 is divided into segments 26a, 26b, respectively. Then, polysilicon spacers 68a, 68b are formed on the sidewalls of the opening 66.

Referring to FIG. 4D, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layer 64, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 4D includes the lower trunk-like polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 68a, 68b, and the branch-like polysilicon layers 62a, 62b, which are substantially pillar-shaped in cross section. The lower trunk-like polysilicon layers 26a, 26b directly contact the drain regions 16a, 16b of the transfer transistor, respectively. The cross sections of the lower polysilicon layers 26a, 26b are T-shaped. The upper trunk-like polysilicon layers 68a, 68b connect to the edges of the lower trunk-like polysilicon layers 26a, 26b, respectively, and stand substantially vertically. The upper truck-like polysilicon layers 68a, 68b are formed as hollow cylinders, the cross sections of which can be circular or rectangular. The branch-like polysilicon layers 62a, 62b connect to the top surface of the lower trunk-like polysilicon layers 26a, 26b and extend upright. According to the third preferred embodiment, the polysilicon layers 62a, 62b are formed as substantially hollow cylinders, the cross sections of which depend mainly on the cross section of the insulating pillars 28a, 28b, which can be circular or rectangular. The branch-like polysilicon layers 62a, 62b are located between the upper trunk-like polysilicon layers 68a, 68b.

Fourth Preferred Embodiment

The following fourth preferred embodiment of the storage capacitor, which includes branch-like electrode layers that are L-shaped in cross section, and branch-like electrode layers that are pillar-shaped in cross section, is described. The fourth preferred embodiment is accomplished by combining aspects of the first and the third preferred embodiments. Therefore, a structure combining the characteristics of the first and third preferred embodiments is constructed.

The fourth preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 5A through FIG. 5C.

The storage capacitor of the fourth embodiment is based on the wafer structure of FIG. 2C. Elements in FIGS. 5A through 5E that are identical to those in FIG. 2C are labeled with the same reference numerals.

Referring to FIGS. 2C and 5A, polysilicon spacers 70a, 70b are formed on the sidewalls of the insulating pillars 28a, 28b, respectively. The polysilicon spacers are fabricated by depositing a polysilicon layer with a thickness of about 1000 angstroms, and etching back the polysilicon layer to form spacers. Then, an insulating layer 72 and a polysilicon layer 74 are deposited in succession by CVD. After that, a thick insulating layer is deposited.

Referring to FIG. 5B, the structure shown is constructed by the processes previously described with reference to FIGS. 2E and 2F. In other words, a CMP technique is utilized to polish the surface of the structure shown in FIG. 5A until the tops of the insulating pillars 28a, 28b, the tops of the polysilicon spacers 70a, 70b, and the tops of the polysilicon layer 74 are exposed.

Conventional photolithography and etching techniques are utilized to etch the insulating layer 76, the polysilicon layer 74, the insulating layer 72, and the polysilicon layer 26, in succession, thus, an opening 78 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 74 and 26 are divided into segments 74a, 74b, and 26a, 26b, respectively. Then, polysilicon spacers 80a, 80b are formed on the sidewalls of the opening 78.

Referring to FIG. 5C, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 76 and 72, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 5C includes the lower trunk-like polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 80a, 80b, the branch-like polysilicon layers 70a, 70b which are substantially pillar-shaped in cross section, and the branch-like polysilicon layers 74a, 74b which are substantially L-shaped in cross section.

The lower trunk-like polysilicon layers 26a, 26b directly contact the drain regions 16a, 16b of the transfer transistor, respectively. The cross sections of the lower polysilicon layers 26a, 26b are T-shaped. The upper trunk-like polysilicon layers 80a, 80b connect to the edges of the lower trunk-like polysilicon layers 26a, 26b, respectively, and stand substantially vertically. The upper truck-like polysilicon layers 80a, 90b are formed as hollow cylinders; the cross sections of which can be circular or rectangular. The branch-like polysilicon layers 74a, 74b, which are substantially L-shaped in cross section, connect to the inner surface of the upper polysilicon layer 80a, 80b, extend inwards horizontally for a determined distance, and then extend substantially upright. The branch-like polysilicon layers 70a, 70b, which are substantially pillar-shaped in cross section, connect to the top surfaces of the lower trunk-like polysilicon layers 26a, 26b and extend substantially upright. The branch-like polysilicon layers 70a, 70b are formed as substantially hollow cylinders.

Fifth Preferred Embodiment

Another storage electrode with a structure similar to the one disclosed as the fourth embodiment, but fabricated in a different manner, is disclosed as the fifth preferred embodiment.

The fifth preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 6A through FIG. 6D.

The storage capacitor of the fifth embodiment is based on the wafer structure of FIG. 2C. Elements in FIGS. 6A through 6D that are identical to those in FIG. 2C are labeled with the same reference numerals.

Referring to FIGS. 2C and 6A, polysilicon layers and insulating layers are deposited alternately by CVD. As shown in FIG. 6A, a polysilicon layer 84, an insulating layer 86, a polysilicon layer 88, and a thick insulating layer 90 are deposited in succession.

Referring to FIG. 6B, a CMP technique is utilized to polish the surface of the structure shown in FIG. 6A until the tops of the insulating pillars 28a, 28b are exposed.

Referring to FIG. 6C, conventional photolithography and etching techniques are employed to etch the insulating layer 90, the polysilicon layer 88, the insulating layer 86, the polysilicon layer 84, and the polysilicon layer 26 in succession; thus, an opening 92 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 88, 84, and 26 are divided into segments 88a, 88b, 84a, 84b, and 26a, 26b, respectively. Then, polysilicon spacers 94a, 94b are formed on the sidewalls of the opening 92.

Referring to FIG. 6D, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 90 and 86, and the insulating pillars 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 6D includes the lower polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 94a, 94b, and the two layers of branch-like polysilicon 84a, 88a, 84b, 88b, which are substantially L-shaped in cross section. The lower trunk-like polysilicon layers 26a, 26b directly contact the drain regions 16a, 16b of the transfer transistor, respectively. The cross sections of the lower polysilicon layers 26a, 26b are T-shaped. The upper trunk-like polysilicon layers 94a, 94b connect to the edges of the lower trunk-like polysilicon layers 26a, 26b, respectively, and stand substantially vertically. The upper trunck-like polysilicon layers 94a, 94b are formed as hollow cylinders, the cross sections of which can be circular or rectangular. The two layers of branch-like polysilicon layers 84a, 88a, 84b, 88b connect to the inner surfaces of the upper trunk-like polysilicon layers 94a, 94b, respectively, and first extend horizontally inward for a determined distance, and then extend substantially upright. The structure according to this preferred embodiment differs from the second preferred embodiment (FIG. 3A through 3E) in that the bottoms of the branch-like polysilicon layers 84a, 84b contact directly with the upper surfaces ofthe lower trunk-like polysilicon layers 26a, 26b. Therefore, the structure of the storage electrode according to the fifth preferred embodiment is similar to the structure of the second preferred embodiment.

Sixth Preferred Embodiment

A storage electrode with a different structure fabricated by a different process is described as the sixth preferred embodiment. The structure of the storage electrode according to the sixth preferred embodiment is very much like the structure according to the second preferred embodiment. A difference between the two embodiments is that the lower trunk-like polysilicon layer of the storage electrode according to the sixth preferred embodiment includes a hollow portion. Therefore, the surface area of the storage electrode is increased.

The sixth preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 7A through FIG. 7D.

The storage capacitor of the sixth preferred embodiment is based on the wafer structure of FIG. 2A. Elements in FIGS. 7A through 7D that are identical to those in FIG. 2A are labeled with the same reference numerals.

Referring to FIGS. 2A and 7A, an insulating layer 96, such as BPSG, is deposited by CVD for planarization. Then, an etching protection layer 98, such as silicon nitride, is formed by CVD. Thereafter using conventional photolithography and etching techniques, the etching protection layer 98, the insulating layer 96, and the gate oxide layer 14 are etched in succession; thus, contact holes 100a, 100b for storage electrodes are formed which extend from the upper surface of the etching protection layer 98 to the surface of the drain regions 16a, 16b. Next, a polysilicon layer 102 is deposited. To increase the conductivity of the polysilicon layer, ions such as arsenic are implanted into the polysilicon layer. As shown in FIG. 7A, the polysilicon layer 102 covers the surface of the etching protection layer 98 and the inner sidewalls of the contact holes 100a, 100b but does not completely fill the contact holes 100a, 100b. Subsequently, the polysilicon layer 102 is hollow and U-shaped in cross section.

Referring to FIG. 7B, a thick insulating layer, such as a silicon dioxide layer with a thickness of about 7000 angstroms, is deposited. Then, the thick insulating layer is defined using conventional photolithography and etching techniques, such that insulating pillars 104a, 104b are formed as shown in FIG. 7B. The insulating pillars 104a, 104b are preferably located above the drain regions 16a and 16b, respectively, on the polysilicon layer 26 and completely fill the hollow structure of the polysilicon layer 102. Gaps 106 are thus formed between the insulating pillars 104a, 104b.

Next, a method similar to that disclosed in accordance with the second preferred embodiment with reference to FIG. 3A through FIG. 3D, is performed to construct the storage electrode according to the sixth preferred embodiment.

Referring to FIG. 7C, CVD is performed to alternately form insulating layers and polysilicon layers, in particular an insulating layer 106, a polysilicon layer 108, an insulating layer 110, a polysilicon layer 112, and a thick insulating layer 114, in succession. A CMP technique can be utilized to polish the surface of the structure until at least the tops of the insulating pillars 104a, 104b are exposed.

Referring to FIG. 7D, conventional photolithography and etching techniques are utilized to etch the insulating layer 114, the polysilicon layer 112, the insulating layer 110, the polysilicon layer 108, the insulating layer 106, and the polysilicon layer 102 in succession; thus, an opening 118 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 112, 108, and 102 are divided into segments 112a, 112b, 108a, 108b, and 102a, 102b, respectively. Then, polysilicon spacers 116a, 116b are formed on the sidewalls of the opening 118. Wet etching is then performed by using the etching protection layer 98 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 114, 110, and 106, and the insulating pillars 104a, 104b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 7D is very much like the structure shown in FIG. 3D. The difference between the two structures is that the lower trunk-like polysilicon layers 102a, 102b of the sixth preferred embodiment are hollow. Therefore, the surface of the storage electrode is increased.

Seventh Preferred Embodiment

A storage electrode with a different structure fabricated by a different process is described as the seventh preferred embodiment. The structure of the storage electrode according to the seventh preferred embodiment is very much like the structure according to the second preferred embodiment. The difference between the two embodiments is that the lower trunk-like polysilicon layer of the storage electrode according to the seventh preferred embodiment does not contact the upper surface of the lower etching protection layer, but rather is separated by a determined distance. Therefore, the surface of the storage electrode is increased.

The seventh preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 8A through FIG. 8E.

The storage capacitor of the seventh preferred embodiment is based on the wafer structure of FIG. 2A. Then, different processing steps are performed to fabricate a different structure. Elements in FIGS. 8A through 8E that are identical to those in FIG. 2A are labeled with the same reference numerals.

Referring to FIG. 8A and 2A, an insulating layer 120, such as BPSG for planarization, is deposited by CVD. Then, an etching protection layer 122, such as silicon nitride, is formed by CVD. Next, an insulating layer 124 such as silicon dioxide is deposited by CVD. Next, using conventional photolithography and etching techniques, the insulating layer 124, the etching protection layer 122, the insulating layer 120, and the gate oxide layer 14 are etched in succession; thus, contact holes 126a, 126b for the storage electrode are formed which extend from the upper surface of the insulating layer 124 to the surface of the drain regions 16a, 16b. Next, a polysilicon layer 128 is deposited. As shown in FIG. 8A, the polysilicon layer 128 completely fills the contact holes 126a, 126b and covers the surface of the insulating layer 124.

Referring to FIG. 8B, a thick insulating layer, such as a silicon dioxide layer with a thickness of about 7000 angstroms, is deposited. Then, the thick insulating layer is defined by conventional photolithography and etching technique, such that insulating pillars 130a, 130b are formed, as shown in FIG. 8B. The insulating pillars 130a, 130b are preferably located above the drain regions 16a and 16b, respectively, on the polysilicon layer 128. Gaps 129 are thus formed between the insulating pillars.

Next, a method similar to that disclosed in accordance with the second preferred embodiment with reference to FIG. 3A through FIG. 3D, is performed to construct the storage electrode according to the seventh preferred embodiment.

Referring to FIG. 8C, CVD is performed to alternately form insulating layers and polysilicon layers, in particular an insulating layer 132, a polysilicon layer 134, an insulating layer 136, a polysilicon layer 138, and a thick insulating layer 140, in succession. A CMP technique can be utilized, to polish the surface of the structure until at least the tops of the insulating pillars 130a, 130b are exposed.

Referring to FIG. 8D, conventional photolithography and etching techniques are utilized to etch the insulating layer 140, the polysilicon layer 138, the insulating layer 136, the polysilicon layer 134, the insulating layer 132, and the polysilicon layer 128 in succession; thus, an opening 142 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 138, 134, and 128 are divided into segments 138a, 138b, 134a, 134b, and 128a, 128b, respectively. Then, polysilicon spacers 144a, 144b are formed on the sidewalls of the opening 142.

Referring to FIG. 8E, wet etching is performed by using the etching protection layer 122 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 140, 136, 132, and 124, and the insulating pillars 130a, 130b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 8E is very much like the structure shown in FIG. 3D. The difference between the two structures is that the lower horizontal surface of the lower trunk-like polysilicon layers 128a, 128b do not contact the top surface of the etching protection layer 122 underneath. Therefore, the surface of the storage electrode is increased.

Eighth Preferred Embodiment

In the first through seventh preferred embodiments, the branch-like electrode layers of the storage electrodes are either vertical structures with single segments or folded structures with two segments that are substantially L-shaped in cross section. However, the invention is not limited in scope to these structures. The number of segments attributed to the folds of the branch-like electrode layer can be three, four, or more. A branch-like electrode layer with four segments is described in detail as the eighth preferred embodiment.

The eighth preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 9A through FIG. 9E.

The storage capacitor of the eighth preferred embodiment is based on the wafer structure of FIG. 2B. Then, different processing steps are performed to fabricate a different structure. Elements in FIGS. 9A through 9E that are identical to those in FIG. 2A are labeled with the same reference numerals.

Referring to FIGS. 9A and 2B, a thick insulating layer, such as a silicon dioxide layer with a thickness of about 7000 angstroms, is deposited over the polysilicon layer 26. A photoresist layer 152 is then formed by a conventional photolithography technique and further is anisotropically etched to form parts of the insulating layer. Therefore, the insulating layers 150a, 150b are formed with gaps 157 there between, as shown in FIG. 9A.

Referring to FIG. 9B, a photoresist erosion technique is utilized to remove portions of the photoresist layer 152, to leave smaller and thinner photoresist layers 152a, 152b. Consequently, portions of the top surfaces of the insulating layer 150a, 150b are exposed.

Referring to FIG. 9C, anisotropic etching is utilized to remove the exposed portions of the insulating layers 150a, 150b and the remaining exposed insulating layer until the polysilicon layer 26 is exposed. Thus, staircase-shaped insulating pillars 150c, 150d are formed. The photoresist layer is then removed.

Next, a method similar to the one used to fabricate the first preferred embodiment, which is described with reference to FIG. 2D to 2G, is performed to form the storage electrode according to the eighth preferred embodiment. Referring to FIG. 9D, an insulating layer 154, a polysilicon layer 156, and a thick insulating layer 158 are then deposited in succession by CVD. Next, a CMP technique is used to polish the surface of the structure until the top surfaces of the insulating pillars 150c, 150d are exposed.

Referring to FIG. 9E, conventional photolithography and etching techniques are utilized to etch the insulating layer 158, the polysilicon layer 156, the insulating layer 154, and the polysilicon layer 26 in succession; thus, an opening 155 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the abovementioned etching step, the polysilicon layers 156 and 26 are divided into segments 156a, 156b and 26a, 26b, respectively. Then, polysilicon spacers 159a, 159b are formed on the sidewalls of the opening 155. Wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 158 and 154, and the insulating pillars 150c, 150d. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode includes, as shown in FIG. 9E, the lower trunk-like polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 159a, 159b, and the branch-like polysilicon layers 156a, 156b, which are folded structures with four segments substantially double L-shaped in cross section. The branch-like polysilicon layers 156a, 156b first connect to the inner surfaces of the upper trunk-like polysilicon layers 159a, 159b, extend inward horizontally for a determined distance, then again extend substantially upright for another determined distance, next extend inward horizontally for another determined distance, and then extend upright vertically.

According to this preferred embodiment, configurations of the insulating pillars and gapped insulating layer control the configuration and the angles of the branch-like polysilicon layer. Therefore, the configuration of insulating pillars and gapped insulating layers according to the invention is not limited to the particular disclosed embodiment. In fact, techniques to modify the disclosed configuration to result in a different final shape according to the eighth preferred embodiment are contemplated. For example, if isotropic etching or wet etching is utilized instead of anisotropic etching to etch the thick insulating layer, shown in FIG. 2C, the resulting insulating layer will be triangle-shaped. Alternatively, also as shown in FIG. 2C, after the insulating pillars 28a, 28b are formed, if insulating spacers are further formed on the sidewalls of the insulating pillars 28a, 28b, insulating pillars with different configurations will be obtained. Therefore, the branch-like polysilicon layer may be formed in several different configurations having various angles according the eighth preferred embodiment.

In accordance with the conception of the preferred embodiment, if branch-like polysilicon layers with more segments are desired, photoresist erosion and anisotropic etching of the gapped insulating layer can be performed once or more to form an insulating pillar with a multiple stair shape.

Ninth Preferred Embodiment

In the first through eighth preferred embodiments, a CMP technique is always utilized to remove the polysilicon layer from above the insulating pillars. However, the invention is not limited in scope by the use of this technique. In the ninth preferred embodiment, a conventional photolithography and etching technique is utilized to split the polysilicon layer on the insulating pillar. Therefore, a storage electrode with a different structure is formed.

The ninth preferred embodiment of the invention, relating to a semiconductor memory device with a tree-type storage capacitor, is described in detail with reference to FIG. 10A through FIG. 10D.

The storage capacitor of the ninth embodiment is based on the wafer structure of FIG. 2C. A DRAM storage electrode with a different structure is fabricated by a further process. Elements in FIGS. 10A through 10D that are identical to those in FIG. 2C are labeled with the same reference numerals.

Referring to FIGS. 10A and 2C, polysilicon layers and insulating layers are deposited alternately by CVD. As shown in FIG. 10A, an insulating layer 160, a polysilicon layer 162, an insulating layer 164, a polysilicon layer 166, and a thick insulating layer 168 are deposited over the silicon layer 26. The insulating layers 160, 164, 168 can be, for example, silicon dioxide layers. The thickness of the insulating layers 160, 164 and the polysilicon layers 162, 166 can be, for example, 1000 angstroms. The thick insulating layer 168 is preferably thick enough to fill the gap on the surface of the polysilicon layer 166.

Referring to FIG. 10B, conventional photolithography and etching techniques are used to etch the insulating layer 168, the polysilicon layer 166, the insulating layer 164, the polysilicon layer 162, the insulating layer 160, and the polysilicon layer 26 in succession; thus, an opening 170 is formed and the storage electrode of the storage capacitor for each memory cell is patterned. Also by the above-mentioned etching step, the polysilicon layers 166, 162, and 26 are divided into segments 166a, 166b, 162a, 162b, and 26a, 26b, respectively. Then, polysilicon spacers 172a, 172b are formed on the sidewalls of the opening 170.

Referring to FIG. 10C, conventional photolithography and etching techniques are used to etch the polysilicon layers 166a, 166b, the insulating layers 164, and the polysilicon layers 162a, 162b in succession; therefore, openings 174a, 174b are formed. Consequently, the polysilicon layers 166a, 166b, and 162a, 162b on the insulating pillars 28a, 28b are partially etched to expose the silicon dioxide layers between the polysilicon layers.

Referring to FIG. 10D, wet etching is performed by using the etching protection layer 22 as an etch end point to remove the exposed silicon dioxide layers, which are the insulating layers 168, 164, 160 and the insulating pillar 28a, 28b. After the wet etching step, the storage electrode of the DRAM storage capacitor is complete. The storage electrode shown in FIG. 10D includes the lower polysilicon layers 26a, 26b, the upper trunk-like polysilicon layers 172a, 172b, and the two layers of branch-like polysilicon 162a, 166a, 162b, 166b having three segments. The two layers of the branch-like polysilicon layers 162a, 166a, 162b, 166b first connect to the inner surface of the upper trunk-like polysilicon layers 172a, 172b, extend inward horizontally for a determined distance, then again extend upright approximately vertically for another determined distance, and then extend inward horizontally for another determined distance.

It is clear to one skilled in the art that the characteristics of the above-mentioned preferred embodiments can also be applied together in combination to form storage electrodes and storage capacitors having various structures. The structures of these storage electrodes and the storage capacitors are all within the scope of the invention.

Although in the accompanying drawings the embodiments of the drains of the transfer transistors are shown as diffusion areas in a silicon substrate, other variations, for example trench-type drain regions, are possible and are contemplated in accordance with the invention.

Elements in the accompanying drawings are schematic diagrams for demonstrative purposes and do not depict an actual scale of the invention. The dimensions of the elements of the invention as shown are not limitations on the scope of the invention.

While the invention has been described by way of example and terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.