Continuous Phase Modulation Digital Communication System

The invention relates to a digital communication system comprising transmission means which are formed by modulation means for producing a radio-frequency signal, which signal is modulated by digital data according to a continuous phase modulation, and receiving means which are formed by converting means for converting the received radio-frequency signal into a baseband signal, detection means for detecting the continuous phase modulation of the baseband signal and sequential decoding means for extracting the digital data from the baseband signal.

The system may be used in satellite transmissions, notably low-rate satellite transmissions or in high-frequency transmissions, notably low-rate high-frequency transmissions.

The invention likewise relates to a receiver for detecting digitally transmitted signals via a continuous phase modulation.

In continuous phase modulations, the information is carried by the phase. These modulations are interesting for their spectral effectiveness, their spectral power and their constant amplitude. Therefore, these modulations may be used with power amplifiers which operate near to their saturation zone.

An example of continuous phase modulation (CPM for short) is described in the document: "Reduced State Sequence Detection of Partial Response Continuous Phase Modulation", A. SWENSSON, IEE Proceedings-1, vol. 138, no. 4, 1991, pages 256 to 268. This document relates to the processing of the signals performed at the receiving end. The receiving means comprise a detector which performs a coherent detection of the baseband signal, followed by a Viterbi decoder. Such a detection does not create intersymbol interference at the receiving end. The Viterbi decoder is only provided and used for correcting the imperfections generated at the transmitting end. But such a system shows various drawbacks. First, the coherent detection needs the presence at the receiving end of a very precise oscillator, which complicates and thus increases the cost of the hardware. Moreover, the precision attained by the coherent detection is insufficient for certain applications. This is the case, for example, for low-rate transmissions (several Mbits/s, for example), for example for satellite links and for high-frequency transmissions (several GHz, for example). When the frequency/rate ratio becomes higher than, for example, 10.sup.4, the techniques described in above document become insufficient.

It is an object of the invention to permit the use of CPM modulations for above transmissions while a sufficient precision is obtained, and also to reduce the cost of hardware needed.

This object is achieved with a system for which the detection means perform a differential detection, the sequential decoding means being such that they correct intersymbol interference generated by the differential detection at the receiving end.

Thus, the differential detection makes it possible to have a great detection precision while the cost of hardware is reduced considerably. Still, it is necessary to devise specific sequential decoding means for compensating for the intersymbol interference caused by the differential detection at the receiving end. The sequential decoding means act on received symbol sequences. Preferably, according to the invention, the sequential decoding means comprise a Viterbi decoder which implements the Viterbi algorithm.

More particularly, the differential detection provides a differential phase which may adopt various possible transition states, the sequential decoding means comprise a Viterbi decoder which acts on a state trellis that includes a reduced number of states, and the Viterbi decoder comprises a feedback loop for reducing computing inaccuracies in the computation of metrics, which inaccuracies are due to the reduction of the number of states.

Preferably, the feedback loop causes a single binary data to occur per survivor state, which data is the result of the reduced Viterbi decoding.

The invention likewise relates to a receiver for receiving radio-frequency signals modulated by digital data according to a continuous phase modulation at the transmitting end. The receiver utilizes a converting means for converting the received radio-frequency signal into a baseband signal, a detection means for detecting the continuous phase modulation of the baseband signal, and a sequential decoding means for extracting the digital data from the baseband signal. The detection means performs a differential detection. The sequential decoding means corrects intersymbol interference caused by the differential detection at the receiving end.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

In the drawings:

FIG. 1 shows a diagram of a communication system which is formed by a transmitter and a receiver;

FIG. 2 shows a diagram of a transmitter;

FIG. 3 shows a diagram of a receiver which includes a differential detector according to the invention;

FIG. 4 shows a diagram of converting means for converting the radio-frequency signal into a baseband signal;

FIG. 5 shows a diagram of a differential detector for determining the phase differences;

FIG. 6 shows a diagram of an embodiment for metrics computing means;

FIG. 7 shows an 8-state trellis for a differential 2-bit detection; and

FIG. 8 gives a diagrammatic representation of the survivor states coming from the reduced trellis.

FIG. 1 is a block diagram of a communication system 5 which is formed by transmitting means TRANS 10 and receiving means RECEIVE 20 which communicate by a communication channel CHA. The transmitter comprises a digital data source DATA 12 which is used for modulating a carrier in modulation means MOD 14 (FIG. 2) to produce a radio-frequency signal RF which is put on the channel. According to the invention, the modulation used is a continuous phase modulation CPM.

FIG. 3 relates to the means 20 used at the receiving end for extracting the CPM modulation digital data. The receiver 20 comprises converting means 21 for converting the received radio-frequency signal RF into a complex baseband signal BB which contains two quadrature components. FIG. 4 provides a diagram of an embodiment for converting means 21. As shown, converting means 21 utilizes a low-pass filter 210 having an output connected to a mixer 212. A local oscillator 214 applies two quadrature signals to the mixer 212, so that a complex baseband signal BB containing two quadrature components is produced at the output of the converting means.

The components of the baseband signal are filtered by a low-pass filter 22, then sampled by a sampler 23 (FIG. 3). The sampled baseband signal BB, then undergoes a differential detection in detection means 24 thereby producing a complex differential signal D(n). The differential phase of the complex differential signal D(n) is then determined in a phase meter 25.

FIG. 5 shows an embodiment for a differential detection means 24 for detecting the CPM modulation. The sampled baseband signal BB.sub.s (n) which leaves the sampler 23 at successive instants determined by n, arrives along two paths, on the one hand, in a mixer 242 and, on the other hand, in delay means 240, which delay means delay the signal k times the binary duration T. The value of the integer k has an influence on the complexity and the performance of the system assembly. More particularly, the value of k occurs in the equation of the metric to be calculated. The output of the delay means 240 is connected to transforming means 244 which transform the signal which is applied to its input into a conjugate signal. The conjugate delayed signal is multiplied by the undelayed input signal in the mixer 242, so that a complex differential signal D(n) is obtained. The latter signal enters the phase meter 25 which produces the measurement of the differential phase. This measurement which is independent of the signal phase forms a differential symbol.

The advantage of using a differential detector resides in the fact that it is not necessary to restore the phase of the carrier signal, which makes it possible to use a local oscillator that performs less well than the local oscillator necessary for carrying out a coherent detection. This leads to hardware that is much less costly.

The differential symbol is quantified in a quantifier 26 which quantifier produces .increment..theta.(n) quantified in p bits. But the data leaving the quantifier cannot be used directly, because the differential detection causes intersymbol interference to occur which has to be corrected. This interference is caused by the existence of the delay path. This correction is made by applying a Viterbi algorithm via sequential decoding means 29. Therefore, the sequential decoding means comprise metric computing means 27 followed by a Viterbi decoder 28. The Viterbi decoding produces a succession of states among possible states. These possible states may be represented in the form of a state trellis. First, the system computes possible transition metrics between states, and then the system selects the paths that connect the states for which the metrics are the lowest. Indeed, it is necessary to compute the metrics of the branches that separate the states, so as to determine the optimum path for covering the trellis. The computation of the metrics is carried out in the metric computing means 27. These metrics are then processed by the Viterbi decoder 28, so that an estimate b.sub.n is produced of the digital data b.sub.n coming from the transmitting end.

The metrics are computed by taking theoretical phase differences into account which would be obtained with a differential detector which functions without noise and phase differences which really exist in the system in operation.

The theoretical phase differences may be written as: ##EQU1## where b.sub.n-i are capable of adopting the value +1 or -1 and where Ci are weight factors. If the memory of the system extends over L bits (b.sub.n-L, . . . , b.sub.n-2, b.sub.n-1, b.sub.n), then the Viterbi detector will have 2.sup.L states, each state having the index n which is determined by the preceding bits (b.sub.n-L, . . . , b.sub.n-1).

In the case of a conventional Viterbi algorithm which acts on all the states of the trellis, the metric is computed for each transition of the state K(b.sub.n-L.sup.K, . . . , b.sub.n-1.sup.K) towards the state S(b.sub.n-L+1.sup.K, . . . , b.sub.n-1.sup.K, b.sub.n.sup.S).

This distance is given by:

with: ##EQU2## where .DELTA..theta.(n) is the phase difference measured on the output of the differential detector, where .crclbar. is the modulo-2.pi. difference sign and where the sign () indicates that they are estimated bits.

The output signal D(n) of the differential detection means 24 which are represented in FIG. 5 is expressed as a function of the input signal BB.sub.s (n) via the relationship:

that is:

By way of example, let us consider a continuous phase frequency modulation TFM (Tame Frequency Modulation) which is a particular type of CPM modulation. In this case, when the optimum sampling instant t.sub.0 is selected, the sampled differential phase is expressed by a linear function of the preceding bits.

In the case where there is a single delay cell 240, that is, k=1, there is obtained:

In the case where there are two delay cells 240, that is, k=2, there is obtained:

In a general manner, for any value of k, the phase variation is written as: ##EQU3##

By way of example of a differential detection, let us consider the case of a three-bit differential detector in which the delay kT is equal to 2T. The theoretical differential phase on the output of the detector is that of equation 7. There will be noticed that the theoretical differential phase produced by the detector depends on the bit b.sub.n received at a given instant defined by n, but also on the bits b.sub.n-3, b.sub.n-2 and b.sub.n-1 received before that instant. These three preceding bits define an 8-state trellis shown in FIG. 7. On the left is represented a state K determined by the bits b.sub.n-3, b.sub.n-2, b.sub.n-1 and on the right is represented a state S which comes after state K. The state S is defined by the state of the bits b.sub.n-2, b.sub.n-1, b.sub.n which come after the three preceding bits. Thus, a state K(-1,-1,-1) will become either the state S(-1,-1,-1) when b.sub.n =-1, or the state S(-1,-1,+1) when b.sub.n =+1. In this example, there are thus 8 possible states S and 16 metrics to be determined. To each value b.sub.n corresponds a phase difference of, for example .DELTA..PHI.=-.pi. for b.sub.n =-1 and .DELTA..PHI.=-3.pi./4 for b.sub.n =+1. For the other states, the phase differences .DELTA..PHI. are indicated on the left of the diagram.

According to the invention, it is possible to apply the Viterbi decoding while taking into account all the L bits which define a state, that is to say, all the 8 states of the trellis in the case of the given example (L=3). Preferably, according to the invention, the Viterbi decoder 28 (FIG. 3) operates with a reduced number of bits L'L, that is, L'=2 in the case of the example, the trellis then being reduced to 4 states. Moreover, to reduce the degradations caused by the reduction of the number of states, according to the invention a feedback loop FB is utilized, which takes into account bits of previous survivor states, that is to say, bits which have been put aside, leading to the reduction of the trellis.

In the case of a reduced Viterbi decoding, a transition from a state K to a state S becomes a transition from a state K' defined by (b.sub.n-L'.sup.K', . . . , b.sub.n-1.sup.K') to a state S' defined by (b.sub.n-L'+1.sup.K', . . . , b.sub.n-1.sup.K', b.sub.n.sup.S'). The metric of the transition from the state K' to the state S' is written as: ##EQU4## with: ##EQU5## where the bits b.sub.n-i.sup.K', i ={L'+1, . . . ,L} are defined by the survivor of the state K'.

In the case of the example of the TFM modulation, with a differential detector operating according to equation 7, there is observed that, compared with a coherent detection, a signal-to-noise degradation of only 0.7 dB is attained for a binary error rate of 10.sup.-5.

As regards the Viterbi decoding, for making a comparison between a Viterbi decoding which acts on the reduced number of states and a Viterbi decoding which acts on the total number of states, let us consider an example based on a 16-state trellis which is reduced to an 8-state trellis, the reduced Viterbi decoding being associated with the feedback loop FB.

Let us consider in this case, a 3-bit differential detector. The theoretical differential phase on the output of the detector is then written as:

The bit b.sub.n of the state S' is thus determined by the bits b.sub.n-4, b.sub.n-3, b.sub.n-2 and b.sub.n-1. By reducing the trellis from L=4 to L'=3, the equations 9 and 10 become: ##EQU6## with: ##EQU7## where b.sub.n.sup.S' is the bit influenced by the transition K'S'.

The term ##EQU8## features the correction made by the feedback loop.

In the case of a TFM modulation, a receiver which includes the combination of such a three-bit differential phase detector, together with a reduced Viterbi decoding which includes a feedback loop, practically has the same performance as a coherent detector with a conventional Viterbi decoding. This is all the clearer as the signal-to-noise ratio is higher.

The metrics which are defined by the equations 2, 9 or 12 can be calculated in real time, but, preferably, they are precalculated and the results are stored in the form of look-up tables in memories. FIG. 6 shows an embodiment for metrics computing means 27. Preferably, means 27.sub.0 to 27.sub.N are utilized for storing precomputed metrics. The means 27.sub.0 to 27.sub.N are a bank of N memories MEM (for N states), for example, PROM memories which are addressed by the p bits coming from the quantifier QUANT 26 and the bits coming from the feedback loop. Preferably, the feedback loop addresses each memory by a single bit, the bit b.sub.n-4 for the example of equation 12. The feedback loop contains N bits (one per state), which are assigned respectively to each memory. A memory is thus addressed by p+1 bits. Each metric is stored in m bits which calls for memories that each have a capacity of 2.sup.p+1.2m bits for producing two metrics per state. The metrics are processed by the Viterbi decoder 28 in a conventional manner. The memory remains small, for example, the size of the memory is 128.times.12=1536 bits for data quantified over p=6 bits and metrics coded in 6 bits.

One state is assigned to one memory. The bit b.sub.n-4 which addresses this memory in the feedback mode thus depends on this state and, more particularly, on the survivor state that has temporarily been retained. FIG. 8 gives a diagrammatic representation of the survivor states. At a given instant, the Viterbi decoder decides on the transition from the state K' to the state S'. If a reduced trellis comprises L' states, the fourth-order survivor contains the bit b.sub.n-4 which is an estimate of the transmitted bit b.sub.n-4 which occurs in equation 11. If the Viterbi decoder acts on L' bits by abandoning, for example, one bit (L-L'=1), the feedback loop will utilize the bit b.sub.n-4 that has temporarily been put aside which is situated in a previous survivor. For each state, there is in this manner a survivor which contains a bit b.sub.n-4 that has been put aside. All the bits b.sub.n-4 of the survivors of the states are thus used for individually addressing one of the N memories 27.sub.0 to 27.sub.N.

It is noticed that the performance attained with the reduced Viterbi decoding (8 states), which is formed by a feedback loop, is nearly identical with that attained with a conventional Viterbi decoding without a reduction of the number of states (16 states), but much better than a Viterbi decoding not reduced to 8 states. The reduction of hardware, on the other hand, is very considerable.

The receiver, according to the patent invention, utilizing differential detection and reduced Viterbi decoding with a feedback loop, performs better, for certain conditions of use, than a receiver having a coherent detection. However, the complexity of the receiver is simplified considerably and may utilize a less precise oscillator than a coherent detection receiver. For example, the oscillator may have less quality and be capable of reaching up to 40 dB additional phase noise, without interfering with the operation of the system.