Multiband Phase Locked Loop Using a Switched Voltage Controlled Oscillator

The invention pertains to phase locked loops. More particularly, the invention pertains to phase locked loops for use with multiple spaced frequency bands.

Phase locked loops have varied and wide applications in communications equipment and other fields. Specifically, they can be used wherever it is necessary to synchronize the phase and/or frequency of two signals. In a typical communications type application, a phase locked loop (PLL) is used to synchronize a local oscillator to the frequency (or phase) of an incoming data signal. Phase locked loops also are used to tune a high frequency local oscillator itself to a separate, more stable, lower frequency local oscillator. For instance, in certain communications applications such as digital telecommunications applications, a very high frequency voltage controlled oscillator (VCO) signal may be necessary for synchronizing to an incoming radio frequency signal at, for example, 800 MHz. In order to very precisely control the frequency of the high frequency VCO, the VCO itself may be in a phase locked loop with a crystal oscillator, since crystal oscillators tend to be extremely accurate. However, crystal oscillators typically do not operate at high enough frequencies to be used directly for high radio frequency applications.

In the telecommunications field, incoming data or voice signals are FM modulated on a radio frequency (RF) carrier frequency of, for example, 800 MHz. The incoming data signal is brought down to the base band frequency, e.g., 0-4 KHz, in two steps. First it is frequency down converted into an intermediate frequency e.g., 70 MHz, and then the intermediate frequency (IF) signal is further down converted to the base band. Commonly, the 800 MHz RF signal is converted down to the IF frequency by means of heterodyning the incoming signal with a local oscillator signal that differs from the RF carrier frequency by an amount equal to the intermediate frequency. Thus, in the present example, a local oscillator operating at 870 MHz is needed. Since crystal oscillators that operate at such high frequencies typically are not available, it is common to utilize a voltage controlled oscillator for generating the 870 MHz local oscillator signal. However, since voltage controlled oscillators require highly accurate voltage control to maintain the local oscillator frequency with precision, the high frequency VCOs typically are embedded within a phase locked loop with a crystal oscillator operating at a much lower frequency.

Because the frequency bands dedicated to cellular telephone communications have rapidly become overloaded with communication traffic, both North America and Europe have recently added new radio frequency (RF) band ranges dedicated for cellular telephone communications. Particularly, in North America, where the 824-894 MHz band has been dedicated to cellular telephone communication use, the 1850-1990 MHz band has been added as a second cellular telephone communication band. In Europe, where 890-960 MHz has been dedicated to cellular telephone communications, 1710-1780 MHz has been added as a second frequency band for cellular telephone communications. Within each band there are a number of channels spaced at, for example, 200 KHz intervals so that multiple telephone calls can be supported in the same geographic cell simultaneously.

In view of these new bands for cellular telephone communications, there is a need for cellular telephones and other cellular communications equipment, including facsimile machines, pagers, wireless PCs, wireless modems, etc., that can receive and transmit signals within two separate RF carrier frequency bands, e.g., 824-894 MHz and 1850-1990 MHz.

Accordingly, there is a need for local oscillators which can operate at two very different RF frequencies. For instance, assuming a 70 MHz intermediate frequency, in order for a cellular telephone to be able to receive and transmit data in either band, it should be capable of generating a local oscillator signal in the 894-964 MHz range and a local oscillator signal in the 1920-2060 MHz range. However, while it is not difficult to produce an oscillator capable of generating signals at different frequencies within a tight band, such as 894-964 MHz or 1920-2060 MHz, it is not practical to produce a single oscillator that can produce signals over so broad a range as to cover 894-2060 MHz. Accordingly, multi-band operation requires special design considerations.

One method of providing multi-band capability is to simply provide two individual phase locked loops, one capable of generating local oscillator signals in the 1920-2060 MHz band and the other capable of generating local oscillator signals in the 894-964 MHz band. However, when switching from one band to the other in such a system, there is necessarily a start-up delay while the capacitors and other circuit components of the PLL charge up. In other words, when the telephone switches from one PLL to the other, there will be a long initial settling period before the VCO in the newly activated PLL locks to the desired frequency. Another disadvantage of this solution is that the use of two PLLs increases the circuit componentry in the telephone and thus also increases the size, weight and cost of the equipment.

Another option is to choose an intermediate frequency for the transceiver that is precisely halfway between the two possible operation bands, i.e., in our example in which the two bands are 824-894 MHz and 1850-1990 MHz, the intermediate frequency would be 1350 MHz. In this manner, only a single band PLL is necessary. However, such an IF frequency constraint, particularly at such a high frequency, can lead to significant overall architectural difficulties and disadvantages.

Accordingly, it is an object of the present invention to provide an improved multi-band phase locked loop.

It is another object of the present invention to provide a multi-band phase locked loop with optimal dynamics and close-in-phase-noise with minimal voltage controlled oscillator tuning voltage.

It is a further object of the present invention to provide a multi-band phase locked loop with maximized voltage controlled oscillator frequency slope.

It is yet a further object of the present invention to provide a multi-band phase locked loop with minimal additional circuitry for handling multiple bands.

It is yet another object of the present invention to provide a multi-band phase locked loop with minimal start-up-lock time upon switching from a first voltage controlled oscillator to another voltage controlled oscillator.

The invention is a phase locked loop with multiple VCOs, one VCO for each frequency band, that can be selectively and alternately coupled into the loop. Given that the natural frequency of a phase locked loop is a direct function of the individual transfer functions of the phase detector, loop filter, voltage controlled oscillator and divider circuit, the natural frequency of the loop is maintained at a single point for any number of frequency bands by switching the transfer function of the phase detector to compensate for any change in the transfer functions of the other circuit components in the loop when frequency band is changed. In most cases, the change in the divide-by ratio of the loop divider circuit that will accompany a change in band will have the most significant effect on the natural frequency of the loop.

The transfer function of the phase detector can be altered, for example, by altering the magnitude of the current source(s) in the phase detector in unison with the switching of bands. In a preferred embodiment, the switching of the current sources is directly responsive to the band select signal.

Alternately, the transfer functions of the various VCOs themselves can be selected so that each VCO transfer function maintains the same natural frequency of the overall loop relative to the change in the divide-by ratio of the loop divider circuit (or any other changes to the overall loop transfer function). This can be accomplished by appropriate selection of the VCO frequency slope (i.e., MHz per volt).

FIG. 1 is block diagram of a multi-band phase locked loop in accordance with the present invention.

FIG. 2 is a block diagram illustrating the transfer function of the phase locked loop of FIG. 1.

FIG. 3 is a more detailed diagram of the phase detector block in FIG. 1.

FIG. 4 is a block diagram of a phase locked loop in accordance with another embodiment of the present invention.

FIG. 1 is a block diagram of an exemplary circuit including a phase locked loop in accordance with the present invention. The phase locked loop is shown at 10. It is a single phase locked loop with multiple VCOs, such as illustrated by VCOs 12 and 14, that can be alternately switched into the loop depending on the band. In operation, the PLL 10 locks the phase of the selected VCO 12 or 14 in synchronism with the reference signal 26 that is input to the PLL 10.

As shown, the reference signal is taken from a crystal oscillator 22 which, preferably, is a temperature controlled crystal oscillator. Divider 24 may or may not be necessary to provide a suitable reference frequency f.sub.ref on input line 26. A phase detector 16 compares the phase of the reference signal f.sub.ref on line 26, with a feedback signal on line 28. The feedback signal on line 28 is the conditioned output signal of the selected voltage controlled oscillator 12 or 14. The signal output of the selected VCO is fed back to the phase detector 16 through a buffer amplifier 30 and a programmable divide-by-N divider circuit 20. Switch 32 selects one of the two VCOs 12 or 14 responsive to a BAND SELECT signal indicating the receive band currently in operation.

The transfer function of a PLL is a function of the individual transfer functions of the loop circuitry, e.g., the phase detector 16, loop filter 18, VCO 12 or 14, and divider 20. In turn, the loop has a natural frequency, .omega..sub.n, that is dictated by the loop transfer function. The natural frequency, .omega..sub.n, should be precisely set so as to minimize the loop settling time and provide optimal loop performance. However, as the loop is switched between frequency bands, the transfer function of the loop will change. Most notably, the division ratio of the divider 20 would need to change dramatically. Also, the different VCOs 12 and 14 might have different transfer functions. Accordingly, the natural frequency of the loop also will change dramatically. Unless somehow "corrected", the natural frequency of the loop cannot be optimally set for more than one of the bands and, therefore, at least one of the bands will have a slower than acceptable settling time.

Further, since the damping coefficient of the loop is proportional to the natural frequency, it too will be changed from the optimal value. The close-in-phase-noise of the system is closely tied to the damping coefficient due to spectral peaking. Accordingly, it too will be set to a less than optimal value for at least one of the bands and, thus, the performance of the PLL will be significantly compromised for at least one of the bands. The changes in the natural frequency and damping coefficient caused by the much smaller changes in the divide-by ratio which occur when the equipment switches between channels within a single band are so small as not to create a concern.

Since the natural frequency of the phase locked loop is a direct function of the individual transfer functions of the phase detector, loop filter, voltage controlled oscillator and divider circuit, the present invention can maintain the natural frequency of the loop at a single optimized point for any number of frequency bands by switching the transfer function of the phase detector to compensate for any change in the transfer functions of the other circuit components in the loop when frequency band is changed. In most cases, the change in the divide-by ratio of the loop divider circuit that will accompany a change in band will have the most significant effect on the natural frequency of the loop.

In the embodiment shown in FIG. 1 where there are only two bands, and thus only two VCOs, the band select signal 40 may be a single bit signal with one level representing the first band, e.g. 824-894 MHz, and the other level signifying the second band, e.g. 1850-1990 MHz. Divider circuits 20 and 24 divide their respective input signals by an integer value selected so as to cause the signals on lines 26 and 28 which are to be compared to each other to have the same frequency so that a phase comparison can be made by phase detector 16. Phase detector 16 outputs a current pulse which is proportional to the difference in phase between the two compared signals on lines 26 and 28. The signal on line 34 is passed through a loop filter 18 prior to being supplied to the voltage controlled oscillators 12 and 14. The loop filter determines the band width of the loop and eliminates out-of-band noise, including, but not limited to, bleed through noise at the frequencies of the crystal oscillator 22, the VCOs 12 and 14, and the phase comparator 16.

The output of the loop filter is a voltage on line 36. As is well known, the VCOs 12 and 14 output a sinusoidal signal at a frequency within their band of operation dictated by the input voltage received on line 36. As previously mentioned, the output of the selected VCO is passed through switch 32 and buffer amplifier 30 and is the output signal of the buffer amplifier. Also as previously mentioned, the output of buffer amplifier 30 is looped back through divide-by-N circuit 20 to the phase detector 16 for comparison with the reference signal.

The dividers 20 and 24 allow the PLL to operate at a low frequency relative to the frequencies of the crystal oscillator 22 and the VCOs 12 and 14. This allows the VCO frequency to be programmed in steps of the phase comparison frequency within the VCO band. Most commonly, the phase comparison frequency is set to the channel separation within the bands, e.g., 200 KHz.

For purposes of the discussion herein, let us assume that the circuit shown in FIG. 1 is embodied in a cellular telephone in which the output signal on line 38 of the PLL is the local oscillator signal for the transceiver of a multi-band cellular telephone for use in North America and that the intermediate frequency of the telephone is 70 MHz. Accordingly, VCO 12 is intended to generate a sinusoidal output signal on line 38 in the 894-964 MHz band, while VCO 14 is intended to generate an output signal on line 38 in the 1920-2060 MHz band. Let us also assume that the dividers 20 and 24 are selected to set a phase detector comparison frequency of 200 KHz. Accordingly, the loop filter is set to have a cut off frequency much lower than 200 KHz to eliminate any reference comparison feedthrough.

Programmable divide-by-N circuit 20 is programmable between at least two division ratios, (i.e., two values of N) responsive to the band select signal 40. Particularly, the feedback signal 28 at the output of divider 20 must have a frequency of approximately 200 KHz. Of course, the divide-by-N circuit also is programmable between the various channels within each band responsive to a separate channel-select signal. However, in order to simplify the discussion, we shall assume one channel of operation in each band at 870 MHz and 1970 MHz, respectively. Thus, when VCO 12 is selected (having a desired output of 870 MHz); the division ratio N.sub.1 for the first band is set to 870 MHz.div.200 KHz=4,350. When VCO 14 (having a desired output frequency of 1970 MHz) is selected, the division ratio N.sub.2 is set to 1970 MHz.div.200 KHz=9,850. The ratio N.sub.2 :N.sub.1, therefore, is 2.2644:1

FIG. 2 is a block diagram illustrating the transfer function of the phase locked loop shown in FIG. 1. With the contributions of the individual circuit elements represented by the different blocks. Block 42 represents the transfer function of the phase detector 16. Sub-block 44 represents the determination of the difference between the feedback signal and the reference signal. Block 46 presents the gain of the detector I.sub.PDx /2.PI., where x is a variable indicating the selected band. I.sub.PDx, for example, may be 2.5 milliamps per 2.PI. radians.

The transfer function of the loop filter is represented in block 48 as function F(S), where S is the phase transfer function in the frequency domain. The capacitors in the loop filter 18 integrate the output current of the phase detector and the filter generates a voltage which is proportional in both magnitude and polarity to the phase difference between the feedback signal and the reference signal.

The transfer function of the selected VCO is shown in block 50 as 2.PI.K.sub.VCOx /S, where K.sub.VCO is the frequency slope of the VCO. The units of K.sub.VCO are Megahertz per volt (MHz/V).

The transfer function 52 of the divider circuit 20 is simply 1/N.sub.x.

In the PLL system illustrated by FIGS. 1 and 2, as in most PLL systems, the loop natural frequency .omega..sub.n can be generally expressed in the form ##EQU1## where C is the integrating capacitance value in the system (contributed primarily by the loop filter 18).

The damping coefficient of the loop can be expressed as ##EQU2## where .tau..sub.S is the time constant of the loop filter F(S).

As can be seen from Equations 1 and 2 above, when the division ratio N is switched to accommodate the particular, selected VCO, the loop natural frequency .omega..sub.n is also changed in direct inverse proportion thereto. Thus, in our example, in which the two frequencies are 870 MHz and 1970 MHz, and wherein the ratio n.sub.2 :n.sub.1 is 2.2644:1, the shifting of the loop natural frequency .omega..sub.n is significant since it varies as ##EQU3## Furthermore, it can also be seen that the damping coefficient, .rho., changes directly proportionally to the change in .omega..sub.n. Thus, if the transfer functions of the phase detector, filter and selected VCO are held constant, the natural frequency of the loop will be altered dramatically from band to band.

Thus, in accordance with the present invention, the I.sub.PD value of the phase detector 16 also is altered responsive to the band select signal 40. I.sub.PD1 is selected when VCO 12 is in operation, i.e., when the 870 MHz band is selected (hereinafter Band1) and I.sub.PD2 is selected when VCO 14 is selected, i.e., when the 1970 MHz band is selected (hereinafter Band2) The ratio of I.sub.PD1 to I.sub.PD2 is dictated in accordance with the equations below. Particularly, as previously described, ##EQU4## Thus, ##EQU5## and, therefore, ##EQU6## Further, ##EQU7## Accordingly, ##EQU8## Thus, the phase detector gain is controlled in accordance with Equation 8, preferably so that the frequency slope of each of the VCOs can be held as high as tolerated while still maintaining optimum PLL dynamics. If the frequency slopes of the VCOs are both maintained at maximum reliable slope and those values are relatively equal, i.e., K.sub.VCO1 =K.sub.VCO2, then the ratio of Equation 8 reduces to; ##EQU9##

By maintaining the natural frequency of the loop at the appropriate point for all of the potential operation bands, start up lock time can be kept to a minimum, oscillator frequency slope can be maximized without restriction, and the VCO control voltage levels can be kept low. Further, the close-in-phase-noise can be optimized. Also, the additional circuitry for accommodating multiple frequency bands is minimal.

FIG. 3 is a circuit diagram of an exemplary phase detector with programmable current gain in accordance with the present invention. In a manner well known to those acquainted with the art, the phase detection portion 70 of the phase detector determines the difference in phase between the two input signals, f.sub.ref and f.sub.VCOx and outputs a pulse on either its UP output line 72 or its DOWN output line 74, depending on whether f.sub.VCOx is lagging or leading f.sub.ref, respectively. The duration of the pulse is directly proportional to the magnitude of the phase difference.

Current sources 76, 78, 80 and 82 are turned on responsive to the pulses on lines 72 and 74. More particularly, current sources 76 and 80 are responsive to a pulse on UP line 72, while current sources 78 and 82 are responsive to a pulse on DOWN line 74. Even more particularly, current source 80 contributes 1.45 milliamps to the output of the phase detector and is controlled directly by the pulse on line 72. Current source 76 contributes about 1.83 milliamps to the output of the phase detector 16. However, AND-gate 84 only allows the control pulse on line 72 to reach current source 76 when the BAND SELECT signal is set to Band2 (1970 MHz). Thus, when Band1 is selected (and the VCO phase lags the reference phase), phase detector 16 generates an output signal for controlling the frequency of the VCO having a magnitude of 1.45 milliamps and a duration corresponding to the duration of the pulse on line 72. If Band2 is selected, the output has a magnitude of about 3.28 milliamps (i.e., the 1.45 milliamps from current source 80 plus the 1.05 milliamps from current source 76) for the duration of the current pulse. The current ratios, i.e., about 3.28 mA:1.45 mA, were selected assuming that the frequency slopes of the two VCOs are equal and thus, the current ratio should be equal to the N.sub.2 :N.sub.1 ratio in accordance with equation 9 (2.2644:1 in the present example).

It should be apparent that current sources 78 and 82 operate in a parallel manner as that discussed above with respect to current sources 76 and 80, except that they are responsive to the pulses on DOWN line 74 rather than UP line 72.

FIG. 4 is a block diagram of a second embodiment of the present invention. In this embodiment, the phase detector 16a is not programmable, but has a constant I.sub.PD value. Rather, the separate VCOs 12a and 14a have K values in accordance with Equation 10 below; ##EQU10##

This embodiment is advantageous over the embodiment of FIG. 1 in that it further minimizes circuitry requirements since the phase detector need not be programmable. However, it is disadvantageous over the embodiment of FIGS. 1-3 in that the frequency slope K.sub.VCO of at least one of the VCOs cannot be maximized and/or one of the VCOs will require a much larger input voltage swing than the other. Either of these conditions is undesirable, particularly in a battery or solar operated device where it is advantageous to keep voltage requirements to a minimum in order to minimize power requirements.

Having thus described a few particular embodiments of the invention, various other alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. The foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.