US 5,903,232 AGrant
Apparatus and Method for Sampling Rate Conversion With Rational Factors
Issue Date:1999-05-11
•23 Claims
•10 Drawing Sheets
Abstract
A rational decimation circuit (200) has an integration filter (210) and an FIR-filter (220). The integration filter (210) has N serially arranged integrator blocks (230-n) and an interpolator block (250). The FIR-filter (220) has K filter channels (260-k) and a commutator (290) which are controlled by a control block (300). Each channel (260-k) has a multiplier unit (270-k) and an accumulator unit (280-k). The integration filter (210) has a transfer function with N-fold poles and the FIR-filter (220) has a transfer function with zeros which cancel the poles. FIR-coefficients h.sub.k (T.sub.V) in the FIR-filter (220) are related to the F.sub.V /F.sub.X ratio of the interpolator block (250) and to the number N of integrator blocks (230-n). A method is also described.
Metadata
Assignee
- Motorola Inc.
Inventors
- Michael Zarubinsky
- Vladimir Koifman
- Eliezer Sand
Application Information
Application Number:US 9437150
Filing Date:1997-10-03
Priority Date:1997-10-03
Art Unit:289
Classifications
IPC:
H03M7/00
Field of Search:
34136450;61;143724.1
Patent Drawings (10 sheets)
Description
FIELD OF THE INVENTION
The present invention generally relates to electronic circuits, and, more particularly to a circuit which converts sampling rates of digital signals.
BACKGROUND OF THE INVENTION
Digital signal processing (DSP) is concerned with the representation of signals by sequences of numbers or symbols ("digits") and the processing of these digital signals ("time discrete signals"). DSP has a wide variety of applications and its importance is evident in such fields as radio communication, telecommunications, pattern recognition, and many others. It is often required to change sampling rates of these signals in sampling rate converters. For the application of sampling rate converters, the following references are useful:
1! Crochiere, R. E. and Rabiner, L. R.: "Interpolation and Decimation of Digital Signals--A Tutorial Review", Proceedings of the IEEE, vol. 69, No. 3, March 1981;
2! Proakis, J. G., Manolakis, D. G.: "Digital Signal Processing", Third Edition, Prentice Hall, Upper Saddle River, 1996, ISBN 0-13-373762-4, sections 10.1 to 10.6 of chapter 10 "Multirate Digital Signal Processing";
3! Norsworthy, S. R., Schreier, R., Temes, G. C.: "Delta-Sigma Data Converters", IEEE Press, New York, 1997, ISBN 0-7803-1045-4; and
4! Chu, Shuni; Burrus, C. S.: "Multirate Filter Designs Using Comb Filters", IEEE Transactions on Circuits and Systems, vol. CAS-31, pages 913-924, November 1984.
According to reference 1!, by "decimation", the sampling rate F of a given digital signal is digitally converted to a lower sampling rate F'(F'<F) by a factor M, called the "decimation factor"; and by "interpolation", the sampling rate F is converted to a higher sampling rate F'(F'>F) by a factor L, called the "interpolation factor". 1! also teaches sampling rate converting by, for example, interpolators (sampling rate expanders), decimators (sampling rate compressors), low-pass filters, sample- and hold circuits, finite impulse response filters (FIR) in polyphase structures with commutators and by other means. 1! discusses the quality of sampling rate conversion by frequency spectra. While factors M and L are, conveniently, integers, modern telecommunication applications often require rational conversion factors, such as M/L. FIG. 4 of 1! illustrates a cascade of an integer interpolator and an integer decimator for achieving rational conversion.
In the art, the term "down-sampling" is used as a synonym for "decimating", and the "up-sampling" is used for "interpolating".
The present invention seeks to provide an improved circuit for sampling rate conversion which mitigates or avoids disadvantages and limitations of the prior art.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a simplified block diagram of data processing system;
FIG. 2 illustrates simplified time diagrams for an analog signal and for digital signals occurring in the system of FIG. 1;
FIG. 3 illustrates a simplified block diagram of a rational decimation circuit of the prior art which can be used in the data processing system of FIG. 1;
FIGS. 4-5 illustrate a simplified block diagram of a rational decimation circuit of the present invention which is preferably used in the system of FIG. 1;
FIG. 6 illustrates a simplified time diagram of a digital intermediate signal;
FIG. 7 illustrates a simplified time diagram of a further digital intermediate signal;
FIG. 8 illustrates simplified spectra of digital signals occurring in the circuit of FIGS. 4-5 and of transfer functions of elements of the circuit of FIGS. 4-5;
FIG. 9 illustrates a simplified time diagram of coefficients provided by a control block and supplied to channels in the system of FIGS. 4-5; and
FIG. 10 illustrates a simplified flow chart diagram of a method according to the present invention.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
For convenience, a glossary of terms used here and their definitions is provided prior to the claims. Apparatus and method of the present invention are explained in the following order: (a) in the text, introducing conventions for a Z-transformation of signals; (b) by FIG. 1, illustrating data processing system 100; (c) by FIG. 2, illustrating signals x(t), X.sub.0 (T.sub.X) and Y.sub.0 (T.sub.Y) in system 100; (d) by FIG. 3, illustrating prior art rational decimation circuit 600; (e) by FIGS. 4-5, illustrating rational decimation circuit 200 of the present invention; (f) by FIG. 6, illustrating signal X.sub.n (T.sub.X) occurring in circuit 200; (g) by FIG. 7, illustrating signal V.sub.1 (T.sub.V) occurring in circuit 200; (h) by FIG. 8, illustrating signal spectra for explaining frequency transfer functions H.sub.XV (Z) and H.sub.VY (Z); (i) in the text, explaining a preferred FIR-function; (j) in the text, explaining further modifications of the FIR-function; (k) in the text in connection with tables I and II, explaining FIR-coefficients of the FIR-function; (l) explaining further details of the FIR-function; (m) in the text with table III and by FIG. 9, illustrating the generation of the FIR-coefficients; (n) by FIG. 10, illustrating a method of the present invention; and (o) further discussion of the present invention.
(a)
A discrete time signal .THETA.(.nu.) has substantially constant magnitudes .THETA. during a discrete time interval T which is counted by .nu.. Intervals T can be identified by other integer numbers, such as e.g., T=0, T=1, T=2 and so on, or by indices, such as, e.g., p, P, a, v, or .gamma.. A Z-transform Z{.THETA.(.nu.)} of signal .THETA.(.nu.) can be calculated by: ##EQU1## wherein the z is the dimensionless Z-transformation operator. The Z-transformation operator is described, for example, in section 3.1 ("The Z-transform") of 2!. The notation z(-.nu.) represents the function z.sup.-.nu.. This convention is used hereafter. The Z-transformation is useful also for expressing frequency transfer functions H(z). The present invention uses discrete time signals .THETA.(.nu.) written as X.sub.0 (T.sub.X), V.sub.1 (T.sub.V) and Y.sub.0 (T.sub.Y) and others which can are based on different time intervals
with
For further explanations, unless otherwise specified, the Z-transformations are referred to the shortest time interval T.sub.V counted by .nu.': ##EQU2## This is convenient for explanation by not essential for the present invention. For example, to obtain the Z-transform Z{.THETA.(T.sub.X)} of .THETA.(T.sub.X), time interval T.sub.V of equation (a.5) is substituted by T=T.sub.V *L.sub.XV : ##EQU3##
(b)
FIG. 1 illustrates a simplified block diagram of data processing system 100 (hereinafter system 100). System 100 comprises analog-to-digital (A/D) converter 110, rational decimation circuit 200 (hereinafter circuit 200), and processor 130 which are coupled in a chain. Circuit 200 is preferably, implemented according to the present invention, while A/D converter 110 and processor 130 can be circuits known in the art. Circuit 200 of the present invention and a preferred method of its operation are explained in connection with FIGS. 2 and 4-10. To distinguish circuit 200 of the present invention over the prior art, prior art circuit 600 is explained in connection with FIG. 3. Prior art circuit 600 can be used instead of circuit 200.
System 100 can be used in a variety of telecommunication and other applications. Conveniently, system 100 can be part of cellular phones operating according to international standards, such as for example CDMA (Code Division Multiple Access) and GSM (Global System for Mobile Communication).
A/D converter 110 is, preferably a sigma-delta modulator. A/D converter 110 receives analog input signal x(t) (reference number 101) and provides digital signal X.sub.0 (T.sub.X) (reference number 112). Decimation circuit 200 receives X.sub.0 (T.sub.X) at input terminal 211 and provides digital signal Y.sub.0 (T.sub.Y) (reference number 122) at output terminal 222. Or, prior art circuit 600 transfers signals from input terminal 611 to output terminal 622. Preferably, processor 130 is a digital-signal processor (DSP) which further processes Y.sub.0 (T.sub.Y).
Analog signal x(t) has frequency components f=0 to a maximum frequency f.sub.max. For example, x(t) can be a voice signal with f.sub.max =8 kHz. Preferably, digital signal X.sub.0 (T.sub.X) has a sampling rate F.sub.X in the megahertz (MHz) region, with for example,
but other values or also possible. Decimation circuit 200 digitally converts sampling rate F.sub.Y of X.sub.0 (T.sub.X) to a lower sampling rate F.sub.Y of Y.sub.0 (T.sub.Y) by rational overall decimation factor M.sub.XY :
For convenience, factor M.sub.XY (M.sub.XY >1) has indices "X" and "Y" indicating a conversion direction "from X to Y". The same convention is followed with respect to other factors, such as "L.sub.XV ", "M.sub.VY " or "H.sub.XY (z)". Conveniently, processor 130 processes Y.sub.0 (T.sub.Y) with sampling rate F.sub.Y in the kilohertz region, e.g.,
used in, for example, CDMA and GSM systems, but other sampling rates F.sub.Y can also be used. Decimation factor M.sub.XY can have values, such as, for example:
The present invention is explained in reference to numeric values of equations (b.5) and (b.6) for CDMA-systems. This "CDMA-example" is not intended to be limiting. Those of skill in the art are able, based on the description herein, to also apply the present invention to others applications.
(c)
FIG. 2 illustrates simplified time diagram 105 for analog signal x(t), diagram 115 for digital signal X.sub.0 (T.sub.X), and diagram 125 for digital signal Y.sub.0 (T.sub.Y) occurring in system 100. Diagrams 105, 115, and 125 have vertical axes for signal amplitudes and horizontal axes for the time.
Diagram 105, illustrates signal x(t) (trace 108) during time t. Points 106 and 107 on trace 108 show that x(t) is sampled by A/D converter 110 in each discrete interval T.sub.X. T.sub.X is the reciprocal representation of sampling rate F.sub.X :
According to the well known sampling theorem, F.sub.X is equal or larger than the twofold maximum frequency of f.sub.max of x(t):
It is convenient for further explanation to assume that A/D converter 110 uses oversampling, that means relatively large F.sub.X :
In the CDMA-example, voice (e.g., f.sub.max .apprxeq.8 kHz) is oversampled with the interval:
or in other words, T.sub.X is approximately a quarter (1/4) of a micro second.
Diagram 115 illustrates digital signal X.sub.0 (T.sub.X) during discrete time intervals T.sub.X (e.g., T.sub.X CDMA). To indicate that X.sub.0 (T.sub.X) is assumed to be constant during T.sub.X, horizontal signal traces 116 and 117 illustrate X.sub.0 (T.sub.X) parallel to the time axis T.sub.X. Auxiliary traces 119 go vertically between traces 116, 117 and the time axis. Traces 119 are not part of the signal and provided only for convenience. This convention is applied also in other diagrams.
Converter 110 provides X.sub.0 (T.sub.X) for every time interval T.sub.X. Preferably, digital signal 0.sub.X (T.sub.X) has a binary data range {X.sub.0 } with positive ("+1", traces 116) and negative ("-1", traces 117) values:
For example, X.sub.0 (0) at T.sub.X =0, X.sub.0 (1) at T.sub.X =1, X.sub.0 (4) at T.sub.X =4, X.sub.0 (6) at T.sub.X =6, X.sub.0 (p) at T.sub.X =P (trace 116') are "+1"; and X.sub.0 (3) at T.sub.X =3 and X.sub.0 (P+1) at T.sub.X =P30 1 are "-1". To use such a data range is convenient, but not necessary.
Diagram 125 illustrates digital signal Y.sub.0 (T.sub.Y) during discrete time intervals T.sub.Y. Decimation circuit 200 provides Y.sub.0 (.gamma.) at T.sub.Y =.gamma. (trace 126), Y.sub.0 (.gamma.+1) at T.sub.Y =.gamma.+1 (trace 127), Y.sub.0 (.gamma.+2) at T.sub.Y =.gamma.+2 (trace 128), etc. T.sub.Y is the reciprocal representation of sampling rate F.sub.Y :
In the CDMA-example, T.sub.Y is, e.g.:
Rational decimation factor M.sub.XY is conveniently illustrated by looking at diagrams 115 and 125. Vertical line 129 goes from the end of time interval T.sub.Y =.gamma. in diagram 125 through trace 116' with signal X.sub.0 (P) in diagram 115. Vertical line 129' connects the vertical amplitude axes. Line 129 and 129' project T.sub.Y from diagram 125 to diagram 115. An integer number of P signals X.sub.0 (T.sub.X) (e.g., X.sub.0 (O) to X.sub.0 (P-1) ) fits into T.sub.Y, wherein one signal (e.g., X.sub.0 (P) ) overlaps. The number P is the integer part of M.sub.XY :
For the CDMA-example, P is obtained as:
Distances of traces 126, 127 and 128 to the T.sub.Y -axis symbolize a magnitude of Y.sub.0 (T.sub.Y). Conveniently, Y.sub.0 (T.sub.Y) during T.sub.Y =.gamma. is represented by a digital word having U bits. Preferably, the digital words has a data range:
Preferably, U equal U=16 bits, but other values U and other ranges can also be used.
(d)
FIG. 3 illustrates a simplified block diagram of rational decimation circuit 600 of the prior art (hereinafter circuit 600) which can be used in the data processing system 100. Circuit 600 comprises serially coupled interpolation circuit 610 and decimation circuit 620. Interpolation circuit 610 receives digital signal X.sub.0 '(T.sub.X) from input terminal 611 and provides intermediate signal V.sub.1 '(T.sub.V) to line 612. Decimation circuit 620 receives intermediate signal V.sub.1 '(T.sub.V) from line 612 and provides output signal Y.sub.0 '(T.sub.Y) at output terminal 622.
Sampling rates F.sub.X ' of X.sub.0 ', F.sub.V ' of V.sub.1 ', and F.sub.Y ' of Y.sub.0 ' are related as:
with partial interpolation factor L.sub.XV ';
with partial decimation factor M.sub.VY '; and
with overall decimation factor M.sub.XY '.
Interpolation circuit 610 comprises differentiator chain 613, interpolator 615, and integrator chain 617 serially coupled between input terminal 611 and line 612. Decimation circuit 620 comprises integrator chain 623, decimator 625, and differentiator chain 627 serially coupled between line 612 and output terminal 622. Differentiator chain 613 comprises N.sub.1 differentiators 614 and differentiator chain 627 comprises N.sub.2 differentiators 628. Integrator chain 617 comprises N.sub.1 integrators 618 and integrator chain 623 comprises N.sub.2 integrators 624.
In the CDMA-example (M.sub.XY CDMA =262.5), L.sub.XV ' and M.sub.VY ' are conveniently chosen as:
resulting in F.sub.V '=16.8 MHz. Differentiator chain 613 in interpolation circuit 610 and integrator chain 623 in decimation circuit 620 operate at the relatively high sampling rates F.sub.X ' and F.sub.V ', respectively, which is not wanted. In the CDMA-example, integrator chain 623 must accommodate signal changes which occur at time intervals
Such short intervals T.sub.V ' are similar to the operation time of hardware components in which the integrators are often implemented.
(e)
FIGS. 4-5 illustrate a simplified block diagram of rational decimation circuit 200 (hereinafter circuit 200) of the present invention. Circuit 200 is the preferred embodiment used in system 100 of FIG. 1. FIGS. 4-5 are connected by placeholder 1 and should be considered together. Circuit 200 comprises integration filter 210 (FIG. 4) and FIR-filter 220 (FIG. 5) shown by dashed frames. Integration filter 210 has N integrator blocks 230-n (hereinafter INTEG n) and interpolator block 250 or "converter" (hereinafter CONV). INTEG 1 to INTEG N are collectively referred to as integrator chain 230 (dashed frame). FIR-filter 220, is preferably, a polyphase filter with K filter channels 260-k (k=1 to K, dashed frames), optional commutator 290 (hereinafter MUX), and control block 300 (hereinafter CONTROL). Filter channel 260-k has multiplier unit 270-k (hereinafter MULT k) and accumulator unit 280-k (hereinafter ACCU k). The term "commutator" is intended to include multiplexers, switches or other circuits which select one signal out of a plurality of signals.
In FIGS. 4-5, arrows.fwdarw.on connection lines indicate a preferred signal flow direction. In the next paragraphs of this section (e), numbers 510 to 550 in brackets ! refer to method steps of 500 which will be explained in detailed in connection with FIG. 10. In integration filter 210, INTEG 1 receives input signal X.sub.0 from input terminal 211 and provides intermediate signal X.sub.1 on line 234-1 for INTEG 2. In general, INTEG 230-n (n>1) receives signal X.sub.n-1 on line 234-(n-1) from INTEG (n-1) and provides intermediate signal X.sub.n to line 234-n. INTEG N provides X.sub.N to line 234-N step 510!. Preferably, the number N of integrator blocks is N=3, but other values can also be used. INTEG n can be implemented by digital circuitry well known in the art, such as counters, adders, or other means. For convenience, an example for signal X.sub.n (T.sub.X) is explained in connection with FIG. 6. CONV receives intermediate signal X.sub.N (T.sub.X) on line 234-N and transforms it to intermediate signal V.sub.1 (T.sub.V) on line 254 step 520!. CONV (providing V.sub.1 (T.sub.V) ) can be implemented, for example, by a comb-filter described in section III of 4!. For convenience, an example for signal V.sub.1 (T.sub.V) which based on time interval T.sub.V is illustrated in FIG. 7.
In FIR-filter 220, line 254 from integration filter 210 (placeholder 1) is coupled to inputs 272-k of MULT k for substantially simultaneously distributing intermediate signal V.sub.1 (T.sub.V) to MULT 1-K. Output 276-k of MULT k provides signal V.sub.2k (T.sub.V) to input 282-k of ACCU k step 530-k!. ACCU k provides intermediate signal W.sub.k (T.sub.V) to input 292-k of MUX step 540-k!. At one time interval T.sub.Y, bar 295 of MUX couples one of inputs 292-1 to 292-K to output 296 on output terminal 222. Thereby, circuit 200 provides output signal Y.sub.0 (T.sub.Y) cf. FIG. 2 and step 550 of FIG. 10!. Optionally, MUX comprises register 299 coupled between output 296 and output terminal 222 for keeping Y.sub.0 (T.sub.Y) constant during T.sub.Y. But this feature is not essential for the present invention.
At output 302, CONTROL simultaneously provides filter coefficients h.sub.k (T.sub.V) (k=1 to K) ("FIR-coefficients") every T.sub.V to inputs 274-k of MULT k (k=1 to K) within step 530-k!. An example will be explained in connection with the operation diagram of FIG. 9. At output 304, CONTROL consecutively provides reset signals R.sub.k (k=1 to K) to inputs 284-k of ACCU k step 560-k!. As illustrated by a line from output 306 to bar 295 of MUX, control block also controls MUX.
A person of skill in the art is able, based on the description herein, to implement circuit 200 by circuitry well known in the art. For example and not intended to be limiting, circuit 200 can be integrated on a monolithic chip manufactured in CMOS technology. The present invention can also be practiced on a digital signal processor (DSP) or on a general purpose processor.
When explaining the operation of circuit 200 in the following, signal propagation times trough the lines and the components are not considered for convenience.
(f)
FIG. 6 illustrates simplified time diagram 235 of digital intermediate signal X.sub.n (T.sub.X) in circuit 200. Diagram 235 has a vertical axis for signal amplitude of X.sub.n (T.sub.X) and a horizontal axis for discrete time intervals T.sub.X,
Preferably, INTEG 1 consecutively receives X.sub.0 (T.sub.X) and X.sub.0 (T.sub.X +1) and provides X.sub.1 (T.sub.X +1) (n=1) according to:
wherein symbol+stands for modulo addition. For example, the "1" and "-1" sequence of signal X.sub.0 (T.sub.X) of diagram 115 (FIG. 2) is integrated to
INTEG n receives X.sub.n-1 (T.sub.X) and X.sub.n-1 (T.sub.X +1) and provides X.sub.n (T.sub.X +1) according to:
Signals X.sub.n (T.sub.X) have magnitudes between a minimum magnitude X.sub.n min and a maximum magnitude X.sub.n max in a preferred data range:
Preferably, X.sub.n min and X.sub.n max are substantially at equal distance from a zero-magnitude X.sub.n =0(at the T.sub.X -axis). For example, traces 236 illustrate positive X.sub.n, and traces 237 illustrate negative X.sub.n. Conveniently, the magnitude of signal X.sub.n can be represented by U.sub.n bits. For example, X.sub.n min and X.sub.n max can be integer numbers with opposite sign:
Such a representation is convenient because X.sub.n has an average of zero. Preferably, the number of bits U.sub.n is equal for all INTEG 1 to INTEG N :
This is convenient, but not essential for the present invention. In the CDMA-example, signals X.sub.n are, preferably, represented by U=16 bits (2.sup.15 =32768), in a data range:
For example, INTEG n can be implemented by an accumulator whose output (i.e. X.sub.n (T.sub.X +1)) is incremented or decremented by X.sub.n-1 (T.sub.X). To avoid overflow, INTEG n resets automatically to minimum value X.sub.n min once maximum value X.sub.n max has been reached trace 238); and resets to a X.sub.n max once X.sub.n min has been reached. Such accumulators are well known in the art under the term "wrap-around accumulator".
INTEG n operates at longer time intervals (i.e. T.sub.X) than integrators 624 in prior art circuit 200 of FIG. 3. This is an important advantage of the present invention and simplifies the hardware implementation of INTEG n.
It is known in the art that the operation speed of an integrator (e.g., INTEG n) is related to its bit resolution U. For example, a speed increase of factor 2 results in an increase of one bit resolution, of factor 4 results in an increase of 2 bits, an so on. Integrators 618 of prior art circuit 600 can be compared with INTEG n of the present invention. Integrators 618 operate at an e.g., L.sub.XV =4 higher speed than INTEG n. Considering the number N of e.g., N=3, integrators 618 require a 2*N=2*3=6 higher bit resolution than INTEG n of the present invention.
(g)
FIG. 7 illustrates simplified time diagram 255 of digital intermediate signal V.sub.1 (T.sub.V) and defines thereby time intervals T.sub.V. Diagram 255 has a vertical axis for signal amplitude of V.sub.1 (T.sub.V) and a horizontal axis for the discrete time intervals T.sub.V.
Discrete time interval T.sub.V is related to T.sub.X by partial interpolation factor L.sub.XV and related to T.sub.Y by partial decimation factor M.sub.VY :
L.sub.XV and M.sub.VY are conveniently chosen as integer factors of overall decimation factor M.sub.XY of circuit 200 introduced in section (b):
Interval T.sub.V can be considered as the reciprocal representation of an intermediate sampling rate F.sub.V :
Signal V.sub.1 (T.sub.V) has preferably, a substantially equal data range as signal X.sub.N (T.sub.X):
Groups 251 with each L.sub.XV consecutive signals
have substantially equal magnitudes which are substantially equal to the magnitude of X.sub.N (T.sub.X):
Rational fraction M.sub.XY is illustrated by measurement lines 252 and 252'. Line 252 illustrates time interval T.sub.Y (cf. FIG. 2) which comprises M.sub.VY signals V.sub.1 (T.sub.V). Lines 252' illustrates that only a number of
signals V.sub.1 (T.sub.V) fit completely into one time interval T.sub.Y. Number A is the product of L.sub.XV and P:
In other words, P groups 251 fit and one group (reference number 251') overlaps. In the CDMA-example (M.sub.XY CDMA =262.5, P.sub.CDMA= 262), L.sub.XV is conveniently chosen as:
and M.sub.VY is chosen as:
(h)
FIG. 8 illustrates simplified spectra of transfer function H.sub.XV (z) of integrator filter 210, H.sub.VY (z) of FIR-filter 220, and an overall transfer function H.sub.XY (z). Diagram 236 illustrates the frequency transfer function H.sub.XV (z) (vertical axis) versus the frequency F (horizontal axis). Transfer function H.sub.XV (z) is defined as the ratio between V.sub.1 (z) and X.sub.0 (z):
H.sub.XV (z) has poles at frequencies F.sub.X, 2*F.sub.X, 3*F.sub.X and so on. The poles are N-fold. Function H.sub.XV (z) is the multiple product of transfer functions H.sub.n (z) of INTEG n (for n=1 to N) and transfer function H.sub.V (z) of CONV: ##EQU4##
H.sub.n (z) of INTEG n can be obtained, for example, by
which is the Z-transform of an integrator.
When, for example, CONV is implemented by a comb-filter (a FIR-filter with only "1" coefficients), then CONV has the transfer function H.sub.V (z): ##EQU5## such as given in equation (14) of 4!. Combining equations (h.2), (h.3) and (h.4), the transfer function H.sub.XV (z) is written as: ##EQU6##
Diagram 241 illustrates the frequency transfer function H.sub.VY (z) of FIR-filter 220 versus the frequency F. Transfer function H.sub.VY (z) is defined as the ratio between Y.sub.0 (z) and V.sub.1 (z):
H.sub.VY (z) has substantially zeros at that frequencies (e.g., 0, F.sub.X, 2*F.sub.X, etc.) where H.sub.XV (z) (diagram 236) has poles.
Diagram 256 illustrates the overall transfer function H.sub.XY (z) of circuit 200. Function H.sub.XY (z) is the product of both partial transfer functions H.sub.XV (z) and H.sub.VY (z):
Poles are compensated by zeros and fluctuations are substantially avoided. Transfer function H.sub.XY (z) is implemented by transfer functions H(z) of filter channels 260-k.
(i)
Function H(z) of filter channel 260-k ("FIR-function") can equivalently be represented in a product form (symbols II and *) and in sum form (symbol.EPSILON.). ##EQU7## N is the number of zeros and v.sub.max is an order of H(z). In equations (i.1) and (i.2), H'(z) is an optional factor initially assumed to be H'(z)=1; and in equation (i.3), H"(z) is an additional summand initially assumed to be H"(z)=0. The product form (equations i.1 and i.2) is conveniently used discuss zeros of H(z), and the sum form is conveniently used to define filter coefficients h(v).
With the zeros, filter channel 260-k suppresses the N-fold poles of the transfer function H.sub.N (z) of equations (h.1) to (h.5). To have the zeros of H(z) at that frequencies where H.sub.N (z) has its poles, exponents i.sub.n are preferably, divisible by L.sub.XV.
Transfer function H(z) in the product form (II) of equations (i.1) and (i.2) is transferred by polynomial multiplication well known in the art to the sum form (.EPSILON.) of equation (i.3). For convenience, an example is given for N=3:
The exponents i.sub.n are summed according to the calculation rules for powers. Filter coefficients h(v) and their indices v are obtained as follows:
(i) taking the .+-.sign in front of the z-operand as coefficient h(v)=+1 or h(v)=-1 and
(ii) taking the sum of the exponents as position index v.
The resulting coefficients are, for example:
The first summand "1" in equation (i.5) has been considered as
(j)
With FIR-function H(z)of equations (i.1) to (i.5), N-fold zeros are provided. FIR-function H(z) is, preferably, modified with optional factor H'(z) to obtain further zeros. H'(z) is given as follows: ##EQU8## For example, H'(z) provides additional .PSI.-fold zeros at F.sub.X *2, so the resulting zeros of H(z) are (N+.PSI.)-fold at F.sub.X *2, but other frequencies can also be used. Preferably, .PSI. is smaller or equal to N:
With optional term H'(z) written into equations (i.1) and (i.2), transfer function H(z) is expressed as: ##EQU9##
Preferably, exponents i.sub.n (n=1 to N) and j.sub.105 (.PSI.=1 to .PSI.) are different between themselves:
Similar as in equations (i.4) to (i.5), the product form (II and *) of H'(z) is transferred to the sum form (.EPSILON.), such as in a convenient example for .PSI.=2:
H'(z) is further multiplied with the right side of equation (i.2): ##EQU10##
Preferably, exponents i.sub.n (n=1 to N) and j.sub.105 (.PSI.=1 to .PSI.) are chosen in that way that coefficients in H(z) become either "+1", "-1", or "0". This is convenient, but not essential.
(k)
Conveniently, exponents i.sub.n and j.sub..PSI. can be obtained as follows for the CDMA-example. With, for example, M.sub.XY CDMA =262.5, P=262, L.sub.XY =4, and A=L.sub.XY *P exponents i.sub.n are calculated as
with b being an L.sub.XY =4 divisible integer variable (for example, b=24).
Exponents j.sub.105 are calculated according to
with c=(L.sub.XY /2)*P=A/2(for example, c=2) and d being, preferably:
Integer d is, preferably, an even number which is not divisible by L.sub.XV ; but other values for d can also be used.
Table I illustrates the frequency transfer function H(z) by equations (k.8) to (k.1). Equation (k.8) was obtained from equation (j.9) by multiplication and uses exponents i.sub.n (i.sub.1,i.sub.2,i.sub.3) and j.sub..PSI. (j.sub.1, j.sub.2). Equation (k.9) was obtained from (k.8) by replacing i.sub.1, i.sub.2, i.sub.3, j.sub.1, and j.sub.2 using A, b, c, and d as defined in equations (k.1) to (k.6). Equation (k.10) is a simplification of equation (k.9). Equation (k.11) illustrates calculation results for the CDMA-example with the numbers from equations (k.1) to (k.6). In table I, column (1) references the summands ("terms") of H(z) by incrementing numbers 1 to 32.
In equations (k.10) and (k.11), the following terms cancel each other:
In table I, the cancellation is illustrated by canceled terms. Function H(z) is thereby further simplified and has 22 instead of 32 terms for the example given.
Similar to equation (i.6), FIR-coefficients h(T.sub.V) are obtained from equation (k.11) in table I with the .+-.sign for "-1" and "+1" coefficients, and exponents of the z-operator as index q.
Table II illustrates a simplified FIR-function H(z). Especially, table II shows
in column (1), term numbers for convenience;
in column (2), group indices g for groups of terms;
in column (3), equation (k.17) which is equation (k.9) of table I without the canceled terms and in a convenient order;
in column (4), T.sub.V -indices of coefficients h(T.sub.V) as combinations of A, b, c, and d; and
in column (5), coefficients h(T.sub.V) with T.sub.V -indices for the CDMA-example (cf. (k.11).
(l)
FIR-order Q of filter channel 260-k is calculated according to: ##EQU11## For N=3 and .PSI.=2, equation (1.1) is similar to term (22) in column (3) of table II.
CDMA-example, the order Q is obtained as:
The number K of filter channels 260-k is:
In the CDMA-example, K=4 fulfills the equation:
It is an important advantage of the present invention, that the number of non-zero coefficients (e.g., 22 coefficients h(T.sub.V).noteq.0)) is small compared to the FIR-order. This advantage contributes to a reduced power consumption during processing compared to the prior art.
(m)
Table III illustrates FIR-coefficients h.sub.1 (T.sub.V), h.sub.2 (T.sub.V), h.sub.3 (T.sub.V) and h.sub.4 (T.sub.V) (columns (2) to (5) (collectively h.sub.k (T.sub.V)) which CONTROL supplies to MULT 1 to MULT 4 of filter channels 260-1, 260-2, 260-3 and 260-4, respectively, in system 200. For convenience, column (1) indicates group index g of table II. T.sub.V in the parenthesis () indicate the time interval T.sub.Y by which MULT k multiplies h.sub.k (T.sub.V) with V.sub.1 (T.sub.V). MULT 1 receives coefficients h(T.sub.V) as given in columns (5) of table II. MULT k receives coefficients h.sub.k (T.sub.V) (channel index k) at a start time S.sub.k. Start time S.sub.k of MULT k is M.sub.VY time intervals T.sub.V later than start time S.sub.k-1 of MULT (k-1). In the CDMA-example, start times are S.sub.1 =0 for MULT 1, S.sub.2 =M.sub.VY =1050 for MULT 2, S.sub.3 =2*M.sub.VY =2100 for MULT 3, S.sub.4 =3*M.sub.VY =3150 for MULT 4, in a repetition S.sub.1 =4*M.sub.VY =4200 for MULT 1 and so on.
FIG. 9 illustrates by a simplified time diagram 400 how CONTROL provides coefficients h.sub.1 (T.sub.V), h.sub.2 (T.sub.V), h.sub.3 (T.sub.V), and h.sub.4 (T.sub.V). FIG. 9 is intended to be an example for CDMA. A person of skill in the are is able to implement CONTROL, based on the description herein, by circuitry well known in the art for the CDMA and for other applications. Coefficients h(T.sub.V) can be precalculated and stored in a memory or CONTROL can have computational elements which calculate h(T.sub.V) in real time, but such as distinction is not important for the present invention.
Horizontal line 401 indicates discrete time intervals T.sub.V which are counted from T.sub.V =0. Vertical lines 451, 452, 453, 454, 455, 456, and 457 at S.sub.1 =0, S.sub.2 =1050, S.sub.3 =2100, S.sub.4 =3150, S.sub.1 '=4200, S.sub.2 '=5250, and S.sub.3 '=6300 (equidistant with "M.sub.VY "), respectively, cross horizontal lines 410, 420, 430 and 440. Lines 410, 420, 430, and 440 have symbols .vertline. for coefficients h.sub.1 (T.sub.V), h.sub.2 (T.sub.V), h.sub.3 (T.sub.V), and h.sub.4 (T.sub.V), respectively. Symbols .vertline. above lines 410-440, indicate h.sub.k ="+1", and symbols .vertline. below lines 410-440 indicate h.sub.k ="-1". When at any time T.sub.V, a line does not have a symbol, then coefficient h.sub.k (T.sub.V) is zero (h.sub.k =0). The time intervals between S.sub.k +(Q-1) (e.g., 4192 on line 410) and S.sub.k '(e.g., 4200) are waiting times T.sub.WAIT k in which MULT k receives h.sub.k =0.
Dashed frame 530-1 cf. step 530-1 in FIG. 10! which encloses line 410 from T.sub.V =0 to T.sub.V =4192 indicates a first cycle in which CONTROL sends h.sub.1 (T.sub.V) to MULT 1. Dashed frames 490-g (g=1 to 8) around the coefficient symbols .vertline. on line 420 indicate groups g of tables II and III. Dashed time line 495 at
illustrates that for each cycle, coefficients h.sub.k (T.sub.V) are, preferably, in an anti-symmetric time sequence. For example, group 1 is anti-symmetric to group 8 with h.sub.k =(T.sub.V)"+1" and "-1" coefficients; group 2 is anti-symmetric to group 7; group 3 to group 6; and group 4 to group 5.
A cycle repetition is indicated by symbols .vertline. for h.sub.1 (T.sub.V) enclosed in dashed frame 530-1'(right-side-open). The first cycle is repeated beginning with T.sub.V =4200 (K*M.sub.VY). For simplicity, further cycles for h.sub.2 (T.sub.V) (beginning at T.sub.V =5250), h.sub.3 (T.sub.V) (beginning at T.sub.V =6300) and h.sub.4 (T.sub.V) (beginning at T.sub.V =7350) are not shown.
(n)
FIG. 10 illustrates a simplified flow chart diagram of method 500 according to the present invention. Method 500 comprises method steps 510, 520, 530-k, 540-k, 550-k and 560-k illustrated by blocks. Index k is the channel index from k=1 to K. For convenience, time axis 501 represents the time in T.sub.V intervals progressing to the right of FIG. 10. For convenience, time axis 501 gives characteristic start times S.sub.k for the CDMA-example (e.g., S.sub.1 =0, S.sub.2 =1050, S.sub.3 =2100, S.sub.4 =3150, in repetitions S.sub.1 '=4200, S.sub.2 '=5250, S.sub.3 '=6300, etc.) but these T.sub.V -numbers are not essential for the present invention. Steps can be performed in parallel. Repetitions of steps in multiple cycles are indicated by prime markers, such as, e.g., in step 530- 1' or for start times S.sub.k '. For convenience, components INTEG 1-N, CONVERT, MULT k, ACCU k, and MUX of circuit 200 (FIGS. 4-5) which participate in certain steps are indicated within the blocks by bold letters. Method 500 comprises integrating step 510 performed by INTEG 1 to INTEG N, interpolating step 520 performed by CONVERT, multiplying step 530-k by MULT k and CONTROL, accumulating step 540-k by ACCU k, reading step 550-k by MUX and CONTROL, and resetting step 560-k by ACCU k and CONTROL.
In integrating step 510, INTEG 1 to INTEG N continuously integrate X.sub.0 (T.sub.X) to X.sub.N (T.sub.X), for example as described in connection with FIG. 6. Integrating step 510 is, preferably, performed all the time.
In interpolating step 520, CONVERT continuously interpolates X.sub.N (T.sub.X) to V.sub.1 (T.sub.V) and provides V.sub.1 (T.sub.V) to MULT 1 to MULT K. For example, CONVERT receives X.sub.N (T.sub.X) and provides V.sub.1 (s) (see FIG. 7) which goes via line 254 (FIG. 5) to MULT 1, to MULT 2, to MULT 3, and to MULT 4. Then, CONVERT provides V.sub.1 (a+1) which also goes to MULT 1 to MULT 4. After having provided V.sub.1 (a+L.sub.XV -1), CONVERT takes X.sub.N (T.sub.X +1) and so on. Converting step 520 is, preferably, performed, all the time.
In multiplying step 530-k CONTROL generates coefficients h.sub.k (T.sub.V) (sections (h) to (m)). MULT k provides intermediate result, for example, according to:
Multiplying step 530-k is, preferably, repeated every time interval T.sub.V within S.sub.k and S.sub.k +(Q-1). In the waiting time (before new S.sub.k '), coefficients h.sub.k are assumed to be at zero so that V.sub.2k =0.
In accumulating step 540-k, ACCU k accumulates V.sub.2k (T.sub.V) to W.sub.k (T.sub.V), for example, according to: ##EQU12##
For example, ACCU I receives V.sub.2k (T.sub.V) beginning at T.sub.V =S.sub.1 =0 and finishes the accumulation of W.sub.1 (T.sub.V) at T.sub.V =Q-1. In the CDMA-example, steps 530-1 and 540-1 provide W.sub.1 according to (equations n.1, n.2, and coefficients h(T.sub.V) from table II, columns (2)): ##EQU13## Accumulating step 540-k is repeated at every time interval T.sub.V. For simplicity of implementation, step 540-k can also be performed during the waiting time T.sub.WAIT k.
In reading step 550-k, MUX reads W.sub.k from ACCU k and forwards W.sub.k as Y.sub.0 (T.sub.Y) to output terminal 222. In reading step 550-k, register 299 can optionally store Y.sub.0 (T.sub.Y) over T.sub.Y, In FIG. 10, the blocks for step 550-k are larger than the time required for performing the step which can be smaller than one time interval T.sub.V.
In resetting step 560-k, CONTROL sends reset signal R.sub.k to ACCU k, so that
Resetting step 560-k is performed after reading step 550-k, preferably during waiting time T.sub.WAIT k. In FIG. 10, the blocks for step 560-k are larger than the time required for performing the step.
Multiplying step 530-k, accumulating step 540-k, reading step 550-k, and resetting step 560-k are cyclically repeated (steps 530-k', 540-k', 550-k', 560-k' and so on). Steps k and steps (k+1) are performed with a shift of T.sub.Y.
(o)
While the present invention has been described in terms of particular structures, devices and materials, those of skill in the art will understand based on the description herein that it is not limited merely to such examples and that the full scope of the invention is properly determined by the claims that follow.
The rational decimation circuit and the method of the present invention are distinguished from the prior art by the following features: (i) The present invention uses an integration filter which integrates first and interpolates second (interpolation after integration). Prior art circuits interpolate and then integrate (interpolation before integration). (ii) A Finite Impulse Response filter "FIR-filter", coupled to the integration filter, suppresses signal fluctuations which could arise because of poles in an integrating function H.sub.XV (z). In the FIR-filter, "0", "-1" and "+1" filter coefficients provide a filter function H.sub.VY (z) which has zeros where the integrating function H.sub.XV (z) has poles. A resulting overall transfer function H.sub.XY (z) has a reduced number of poles. (iii) The FIR-filter is, preferably, a polyphase filter with a plurality of filter channels are switched by a commutator. (iv) The numbers of "+1"-coefficients and "-1"-coefficients in the FIR-filter are, preferably, equal in all filter channels. Preferably, the total number of "+1" and "-1" coefficients is larger than the total number of "0" coefficients. (v) Integrators operates at the input sampling rate and not at a higher intermediate sampling rate.
Glossary of Terms
In the following, (i) abbreviations, (ii) physical units, and (iii) writing conventions are listed alphabetically. This glossary is provided only for convenience.
Claims
We claim:
1. A method for converting a sampling rate F.sub.X of an input signal X.sub.0 to a sampling rate F.sub.Y =F.sub.X /M.sub.XY of an output signal Y.sub.0, with M.sub.XY being an overall decimation factor, said method comprising the steps of: integrating said input signal X.sub.0 to an intermediate signal X.sub.N without changing said sampling rate F.sub.X ; interpolating said intermediate signal X.sub.N to an intermediate signal V.sub.1 having a sampling rate F.sub.V =L.sub.XV *F.sub.X, with L.sub.XV being an intermediate decimation factor; multiplying said intermediate signal V.sub.1 with filter coefficients h.sub.k and accumulating the products to provide intermediate signals W.sub.k, with cycles starting at distances M.sub.VY =M.sub.XY *L.sub.XY, with M.sub.VY being an intermediate decimation factor; and reading every T.sub.Y =1/F.sub.Y said intermediate signal W.sub.k to provide said output signal Y.sub.0.
2. The method of claim 1 further comprising a resetting step being performed at the send of said cycles to set said intermediate signals W.sub.k to zero.
3. The method of claim 1 wherein L.sub.XV =4.
4. The method of claim 1 wherein said filter coefficients h.sub.k have values "+1", "-1" and "0" arranged in an anti-symmetric time sequence.
5. The method of claim 1 wherein said integrating step is performed by N integrators, and wherein said filter coefficients h.sub.k are calculated by polynomial multiplication of ##EQU14## with exponents "i.sub.n " being divisible by said intermediate interpolation factor L.sub.XV and H'(z) a factor with any value.
6. The method of claim 5 wherein said factor H'(z) is ##EQU15## with .PSI..ltoreq.N.
7. A method for converting a first time discrete signal X.sub.0 (T.sub.X) based on first time intervals T.sub.X to a second time discrete signal Y.sub.0 (T.sub.Y) based on second time intervals T.sub.Y =M.sub.XY *T.sub.X, with M.sub.XY >1 being a decimation factor, said method using a third, intermediate signal V.sub.1 (T.sub.V) based on third time intervals T.sub.V =L.sub.XV *T.sub.X ; said method comprising the following steps: continuously integrating X.sub.0 (T.sub.X) to a fourth, intermediate signal X.sub.N (T.sub.X); continuously interpolating X.sub.N (T.sub.X) to V.sub.1 (T.sub.V); and in K cycles identified by index k; (i) multiplying V.sub.1 (T.sub.V) with FIR-coefficients h.sub.k (T.sub.V) to obtain fifth, intermediate signals V.sub.2k (V.sub.T)=V.sub.1 (T.sub.V)*h.sub.k (T.sub.V); (ii) accumulating V.sub.2k (T.sub.V) to a sixth, intermediate signal W.sub.k (T.sub.V); (iii) repeating steps (i) and (ii) for Q-1 time intervals T.sub.V, with Q being an FIR-order; (iv) providing Y.sub.0 (T.sub.Y) as W.sub.k (T.sub.V); (v) resetting W.sub.k, with said K cycles being performed in parallel wherein cycles k and k+1 start with M.sub.VY *T.sub.V time shifts.
8. The method of claim 7 wherein Q<M.sub.VY *L.sub.XV.
9. The method of claim 7 wherein K>integer (Q-1)/(M.sub.VY +1).
10. The method of claim 7 wherein said FIR-coefficients h.sub.k (T.sub.V), used in said multiplying step (i), provide a frequency transfer function with zeros at that frequencies at which poles are produced during said integrating and interpolating steps.
11. The method of claim 7 wherein said FIR-coefficients h.sub.k (T.sub.V) are calculated by polynomial multiplication of ##EQU16## with H(z) being a transfer function for steps (i) to (v) canceling poles of said integrating and interpolating steps, exponents i.sub.n being divisible by L.sub.XV.
12. An apparatus for transforming a first signal having a first sampling rate to a second signal having a second sampling rate, said apparatus comprising: a first filter receiving said first signal, integrating said first signal and interpolating said first signal to a third, intermediate signal having a third sampling rate, said first filter having a first frequency transfer function with poles; and a second filter receiving said third signal and providing said second signal, said second filter having a second frequency transfer function with zeros at some or all of frequencies at which said first filter has said poles, said apparatus having an overall transfer function in which some or all poles of said first filter are canceled.
13. The apparatus of claim 12 wherein said first sampling rate is smaller than said second sampling rate and wherein said third sampling rate is larger than said second sampling rate.
14. The apparatus of claim 12 wherein said first filter integrates said first signal by N integrators and said second filter provides zeros which are at least N-fold.
15. The apparatus of claim 12 wherein said second filter employs K channels and a multiplexer, (i) each channel at said third sampling rate multiply said third signal with FIR-coefficients to provide fourth, intermediate signals, and accumulate said fourth signals to provide sixth, intermediate signals, (ii) said multiplexer at said second sampling rate forwarding said sixth, intermediate signals to said second signals.
16. The apparatus of claim 12 wherein said second filter employs K channels which are FIR-filters of the order Q, said Q/K being smaller than the ratio between said third sampling rate and said first sampling rate.
17. The apparatus of claim 12 wherein said second filter employs K channels, a multiplexer and a control block, channels filtering said third signal to K filter signals, said multiplexer at said second sampling rate transferring said filter signals to said second signal, and said control block providing cycles of FIR-coefficients to said channels.
18. An apparatus for providing a rational decimation by transferring a first, high sampling rate 1/T.sub.X of an input signal X.sub.0 (T.sub.X) to a second, lower sampling rate 1/T.sub.Y of an output signal Y.sub.0 (T.sub.Y), said apparatus comprising: an integration filter having an integrator chain for integrating said input signal X.sub.0 (T.sub.X) to an intermediate signal X.sub.N (T.sub.X), an interpolator block for interpolating X.sub.N (T.sub.X) to an intermediate signal V.sub.1 (T.sub.V) at a third, highest sampling rate 1/T.sub.V ; and a FIR-filter for decimating V.sub.1 (T.sub.V) to said output signal Y.sub.0 (T.sub.Y), said FIR-filter employing FIR-coefficients such that poles introduced to the spectrum of V.sub.1 (T.sub.V) by a first transfer function of said integration filter are canceled by zeros in the spectrum of a second transfer function of said FIR-filter.
19. The apparatus of claim 18 wherein said integrator chain comprises N serially arranged integrator block and wherein said second transfer function has at least N-fold zeros.
20. The apparatus of claim 18 wherein said integrator chain comprises wrap-around accumulators.
21. The circuit of claim 18 wherein said interpolator is implemented by a comb-filter.
22. The circuit of claim 18 wherein said FIR-filter comprises K filter channels which are multiplexed and operate time-shifted.
23. The circuit of claim 18 wherein said FIR-filter comprises K filter channels: K=(Q-1)/(M.sub.VY +1), with Q being an FIR-order of said channels and M.sub.VY being M.sub.VY =T.sub.Y /T.sub.V.
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