Very Low-Gain Voltage Controlled Oscillator

This invention relates to all voltage controlled oscillators (VCOS) and particularly those used in phaselocked loop systems.

A voltage controlled oscillator is a device whose output frequency (Fout) is a function of its input voltage (Vin). A VCO is often used to track a reference signal. It does this by using a phase-locked loop. A phase detector compares the phase of the reference input signal (Fref) and the divided VCO output signal (Fout/N, N=1, 2, 3, 4, . . . ). Depending on this phase difference, the input node of the VCO is either charged or discharged, thereby altering the VCO's frequency of oscillation. When the frequencies of the two phase detector input signals are matched within a given error margin, the PLL is then said to be "locked" to the reference signal. VCO design is critical in determining the overall performance of a PLL. The VCO's stability to small fluctuations in its input voltage is very important in determining PLL stability and jitter. Jitter can be thought of as spurious variations in the time positions of a series of successive pulses. Let's now look at the typical characteristic of a VCO.

The VCO characteristic shown in FIG. 1 assumes for simplicity sake that as the DC input voltage (Vin) increase, the output frequency (Fout) also increase. Of course, the reverse characteristic also exists. While temperature and power-supply variations will cause the oscillation frequency to change (indicated by <-> in FIG. 1), the far biggest influence on where the characteristic ultimately lies and its slope is the actual process condition ("bst", "typ" and "wst") at the time of manufacture. "bst" represents the process condition (resistor value, transistors parameter values, wire capacitance value) which results in highest output speed, "typ" represents those values which result in average output speed while "wst" represents those values which result in lowest speed. FIG. 1 assumes typical temperature and power-supply conditions.

The input voltage ranges (Va, Vb, Vc) which produce the actual required output target Fout(target) frequency range depend heavily on the process condition. Consequently, the current range (Ia, Ib and Ic) shown in the I-Fout characteristic of FIG. 2) which a current controlled oscillator requires to produce oscillations in the Fout(target) frequency range changes drastically from one process condition to another. The required current range (Ic) is widest in the worst ("wst") process condition and narrowest (Ia) in the best ("bst") process condition.

FIG. 3 shows a conventional VCO. The conventional VCO 140' comprises a bias generator 170' for generating a bias voltage in response to a DC input voltage (Vin) and a single current controlled oscillator 180' for generating an output signal having an output frequency (Fout) in response to the bias voltage. Such conventional VCOs are disclosed in, for example, U.S. Pat. No. 4,876,519 issued to Craig M. Davis et al., U.S. Pat. No. 5,331,295 issued to Jules J. Jelinek et al., U.S. Pat. No. 5,359,301 issued to Anthony B. Candage, U.S. Pat. No. 5,300,898 issued to Dao-Longe Chen et al., and U.S. Pat. No. 5,298,870 issued to Christopher Cytera et al.

Traditionally, irrespective of the process condition, a fixed current range (Itrad) has been used to produce the required Fout(target). See FIG. 2. Hence, the same current range is supplied to the VCO 140' in FIG. 3 in the worst case where a large current range (Ic) is required to produce oscillations in the Fout(target) frequency range as it is in the best case where in contrast only a small current range (Ia) is needed. It will now be illustrated with an example that using this traditional approach, small fluctuations in input current can produce significant shifts in output frequency and hence, increase jitter and degrade system stability.

For example let's assume that:

(a) Itrand=250 .mu.A, Ia=20 .mu.A, Ib=40 .mu.A and Ic=90 .mu.A,

(b) the VCO operates over a Ftarget=120 MHz frequency range,

(c) that a 50 mV fluctuation in input voltage produces a (Itrand/50) variation in input current.

This 5 .mu.A change in input current will produce a 30 MHz, 15 MHz and 6.67 MHz change in oscillation frequency for a "bst", "typ" and "wst" case process condition, respectively. In fact, the steeper the slope (gain) of the I-Fout characteristic, the bigger the frequency shift. Consequently, system stability is degraded and jitter increase.

It is therefore an object of this invention to provide a very low-gain voltage controlled oscillator which is capable of improving system stability.

It is another object of this invention to provide a very low-gain voltage controlled oscillator of the type described, which is capable of decreasing jitter.

Other objects of this invention will become clear as the description proceeds.

Thus in conclusion to produce low jitter, a VCO is needed which has low gain in the target Fout(target) frequency range irrespective of process variations. While the "typ" and "bst" I-Fout characteristics have high gain in the desired Fout(target) frequency range shown in FIG. 2, they have very low gain in much higher frequency ranges, namely M*Fout(target) and P*Fout(target), respectively. Consequently, by forcing the "typ" and "bst" current controlled oscillators to operate in the M*Fout(target) and P*Fout(target) low-gain frequency ranges, respectively and then using dividers M and P at their respective outputs, a very stable and low jitter Fout(target) PLL system can be achieved irrespective of process variations. A control circuit is used to provide the optimum current range to each current controlled oscillator and select the appropriate current controlled oscillator output so as to enable lock.

This present invention guarantees that irrespective of process variations, a voltage controlled oscillator has very low gain I-Fout characteristics in the Fout(target) frequency range.

Bias control signals BC1 to BCN from a control circuit determines which one of bias output signals BG1 to BGN of a bias generator is active at any one time. The active (BG1 to BGN) bias output signal defines a unique current range in one of the current controlled oscillators in the current controlled oscillator block and hence a unique output frequency range. Only one of the current oscillators is ON at any one time. Control signals CT1 to CTN determine which one of the multiplexer inputs is active at any one time.

By using multiple current controlled oscillators and/or dividers, it is possible to generate very low gain voltage controlled oscillator characteristics in the Fout(target) frequency range irrespective of process variations. The current controlled oscillators I-Fout characteristic should be optimized for each type ("bst", "typ" and "wst") of process chip. A control circuit is used to command the bias generator to supply each type of current controlled oscillator with its optimum current range and to select the current controlled oscillator which produce oscillations in the desired Fout(target) frequency range.

FIG. 1 shows a traditional VCO Vin-Fout characteristic;

FIG. 2 shows a traditional Vco I-Fout characteristic;

FIG. 3 shows a block diagram of a conventional voltage controlled oscillator;

FIG. 4 shows a block diagram of a very low-gain voltage controlled oscillator according to the present invention;

FIG. 5 shows a block diagram of a very low-gain voltage controlled oscillator according to a first embodiment of the invention incorporated in a phaselocked loop circuit;

FIG. 6 shows a block diagram of the very low-gain voltage controlled oscillator according to the first embodiment of the invention;

FIG. 7 shows a block diagram of a very low-gain voltage controlled oscillator according to a second embodiment of the invention;

FIG. 8 shows a block diagram of a very low-gain voltage controlled oscillator according to a third embodiment of the invention;

FIG. 9 shows a block diagram of a very low-gain voltage controlled oscillator according to a fourth embodiment of the invention;

FIG. 10 shows a block diagram of a very low-gain voltage controlled oscillator according to a fifth embodiment of the invention;

FIG. 11 shows a block diagram of a very low-gain voltage controlled oscillator according to a sixth embodiment of the invention; and

FIG. 12 shows a block diagram of a very low-gain voltage controlled oscillator according to a seventh embodiment of the invention.

Referring to FIG. 4, description will proceed to a very low-gain voltage controlled oscillator according to the present invention. The illustrated very low-gain voltage controlled oscillator guarantees that the I-Fout characteristic of the VCO has low gain in the desired Fout(target) frequency range irrespective of process variations. The VCO consists of a control circuit 160, a bias generator 170, a current controlled oscillator block 180, a divider block 190, and an n-1 multiplexer 200. The current controlled oscillator block 180 contains one or more current controlled oscillators (not shown) which will later become clear.

The bias generator 170 responds to a DC input voltage Vin and bias control signals (BC1 to BCN) from the control circuit 160 to produce one or more bias output signals (BG1 to BGN). The output(s) of the bias generator 170 are connected input(s) of one or more current controlled oscillators in the current controlled oscillator (CCO) block 180. Each output of the current controlled oscillator is directly connected to a different input of the n-1 multiplexer 200 or an input of a divider with a fixed or programmable division ratio R (>1). The n-1 multiplexer 200 is only used if the divider block 190 has more than one output or in the case where no divider block is used, if more than one current controlled oscillator is used. The n-1 multiplexer 200 has n input signals and produces a single output frequency signal Fout. In the divider block 190 with fixed/programmable division ratio(s) R (R1, R2, . . . ), an input of each divider is connected to the output of a corresponding current controlled oscillator, an output of each divider is connected to a different input of the n-1 multiplexer 200. When a programmable divider block is used, the n-1 multiplexer is placed between the CCO block and the programmable divider block.

Description will proceed to operation of the VCO illustrated in FIG. 4.

The bias control signals BC1 to BCN from the control circuit 160 determine which one of the bias output signals BG1 to BGN of the bias generator 170 is active at any one time. The active (BG1 to BGN) bias output signal defines a unique current range in one of the current controlled oscillators in the current controlled oscillator block 180 and hence a unique output frequency range. Only one of the current controlled oscillators is ON at any one time. Selection control signals CT1 to CTN determine which one of the multiplexer 200 inputs is active at any one time.

FIG. 5 shows a very low-gain voltage controlled oscillator according to a first embodiment of the invention incorporated in a phase-locked loop circuit 100. A phase detector 110 responds to differences in phase between a reference signal Fref and a divided output signal (Fout/N) to produce two output signals UP and DN. When the frequency of the reference signal Fref is greater than the VCO's divided frequency of the divided output signal (Fout/N), the UP signal is high. And when the frequency of the reference signal Fref is less than the VCO's divided frequency of the divided output signal (Fout/N), the DN signal is high. A charge pump 120 generates a difference signal VCP in response to the input signals UP and DN. A low pass filter (LPF) 130 filters the VCP voltage signal and generates a Vin signal which is used to control the oscillation frequency of the VCO 140. A programmable divider 150 divides an output frequency signal Fout of the VCO 140 by an integer value N to produce the divided output signal (Fout/N). The integer value N of the programmable divider 150 is set by its select inputs. The VCO 140 is said to be in the synchronous state or "locked" state when the frequency of the reference signal Fref and the VCO's divided frequency of the divided output signal (Fout/N) are matched within an error margin. In contrast, the VCO 140 is said to be in the unsynchronous state or "unlocked" state when the frequency of the reference signal Fref and the VCO's divided frequency of the divided output signal (Fout/N) are unmatched within an error margin. The time taken for the PLL 100 to achieve the "locked" state is called the lock-up time, tlck. All the above mentioned blocks are general blocks that can be found in most phase-locked loop systems. "Normal PLL operation" involves only these blocks. The conventional VCO 140' shown in FIG. 3 just contains the bias generator 170' and the single current controlled oscillator 170'. The divider block and multiplexer at the output of the current controlled oscillator block together with the control circuit and the bias generator constitute the present invention.

The control circuit 160 commands the bias generator 170 to supply the "optimum current range" to each current controlled oscillator. "Optimum current range" means the input current range which corresponds to very low VCO gain. In FIG. 2, these ranges correspond to Ia', Ib' and Ic. Generally only one of its bias output signals (BG1 to BGN) is active at any one time. The selection control signal CT1 to CT2 of the control circuit 160 determines which one of the input signals (A, B, C) of the 3-1 multiplexer 200 is active at any one time.

The bias generator 170 accepts an input voltage Vin and depending on the bias control signals BC1 to BCN from the control circuit 160 decides which one of three current controlled oscillators (namely, CCO1, CCO2 and CCO3) is active at any one time. Consequently, only one of its bias output signals BG1, BG2 and BG3 is active at any one time.

The current controlled oscillator block 180 contains three current controlled oscillators, namely CCO1 (182), CCO2 (184) and CCO3 (186). only one of these current controlled oscillators is active at any one time. The reason for having three current controlled oscillators is to optimize the VCO characteristic for each type of process chip i.e. worst case ("wst"), typical case ("typ") and best case ("bst"). CCO1 is used for a worst case chip, CCO2 for a typical case chip and CCO3 for a best case chip. By providing each one of these current controlled oscillators with its "optimum current range", a VCO with very low gain I-Fout characteristics can be generated irrespective of process variations.

In the embodiment shown in FIG. 5, a divider block 190 is placed at the output of the current controlled oscillator block 180. It consists of two dividers, namely 192 and 194. A divider placed at the output of a current controlled oscillator is used to transfer its low-gain I-Fout characteristic to the desired Fout(target) frequency range. Hence, since CCO2 has a low-gain I-Fout frequency response at M times the desired Fout(target) frequency range, the divider 192 with a fixed division ratio M is required at the output of CCO2. Similarly, since CCO3 has a low-gain I-Fout characteristic at P times the desired Fout(target) frequency range, the divider 194 with a fixed division ratio P in needed at the output of CCO3.

The 3-1 multiplexer 200 placed at the output of the divider block 190 generates the output frequency signal Fout. Select signals S0 and S1 determine which one of the input signals (A, B or C) is selected.

The operation of the present invention is as follows. The control circuit 160 defines an initial "optimum current range" in the bias generator 170. Let's assume that this initial "optimum current range" corresponds to BG1=Vbg1 (>0), BG2=0 and BG3=0. The initial state of the select signals S0 and S1 (say "00" for example) selects one of the inputs of the 3-1 multiplexer 200 (in this case A). Therefore in this case, CCO1 oscillates but CCO2 and CCO3 do not. After a given time longer than tlck elapses, the control circuit 160 checks whether the PLL 100 has achieved the "locked" state or not. If is has, then the values of signals S0, S1, BC1 to BCN remain the same. "Normal PLL operation" adjusts the bias voltage of the reference signal Vin for temperature and supply variations to maintain lock. Otherwise the values of these signals are changed. A change in the values of the select signals S0 and S1 (e.g. "00" to "01") results in a different input of the 3-1 multiplexer 200 being selected (say B for example). A change in the values of the bias control signals BC1 to BCN results in a different "optimum current range" being defined in the bias generator 170 and hence a change in the values of the bias output signals BG1, BG2 and BG3 (in this case, BG1=0, BG2=Vbg2 (>0), BG3=1). Again after a given time longer than tlck elapses, the control circuit 160 checks whether the PLL 100 has achieved the "locked" state or not. If it has then the values of the signals S0, S1, BC1 to BCN remain the same. "Normal PLL operation" adjusts the bias voltage of the reference signal Vin for temperature and supply variations to maintain lock. Otherwise the values of these signals are changed. A change in the values of the select signals S0 and S1 (e.g. "01" to "10") results in the last input of the 3-1 multiplexer 200 being selected (in this case input C). A change in the value of the bias control signals BC1 to BCN results in a different "optimum current range" being defined in the bias generator 170 and hence a change in the values of the bias output signals BG1, BG2 and BG3 (in this case, BG1=0, BG2=0 V, BG3=Vbg3>0). The PLL 100 is guaranteed to reach the "locked" state using one of the three current controlled oscillators, which one depends on the type of process chip at the time of manufacture.

In the first embodiment of the invention shown in FIG. 6, three current controlled oscillators CCO1, CCO2 and CCO3 are used to optimize the VCO characteristic for each type ("bst", "typ" and "wst") of process chip. The divider block 190 is used to transfer the low gain I-Fout characteristics of the current controlled oscillators CCO2 and CCO3 to the desired Fout(target) frequency range. Hence low gain I-Fout characteristics in the Fout(target) frequency range can be achieved irrespective of process variations.

While the divider block 190 is used in the first embodiment shown in FIG. 6, it is not always necessary. For example, the VCOs do not contain any divider block. In a sixth embodiment shown in FIG. 11, the I-Fout characteristic of each current controlled oscillator is optimized to have low gain in the desired Fout(target) frequency range. Therefore very low gain I-Fout characteristics can also be achieved by this approach which doesn't use a divider block. From a circuit size point of view, there is no real difference. Irrespective of whether a divider block is used or not, it is recommended to use three current controlled oscillators CCO1, CCO2 and CCO3 to achieve the best performance (i.e. lowest gain I-Fout characteristics).

While a second embodiment shown in FIG. 7 doesn't achieve as good performance as either FIG. 6 or FIG. 11, it can be implemented in a smaller area. The main difference between FIG. 6 and FIG. 7 is that FIG. 7 has only two current controlled oscillators CCO1, CCO2 and CCO3 as opposed to three in FIG. 6. CCO2 in FIG. 7 has a low gain I-Fout characteristic at M*Fout(target) and hence needs the divider 192 with division ratio M at its output to produce oscillations in the required Fout(target) frequency range. If however, the I-Fout characteristic of CCO2 is optimized to produce oscillations in the Fout(target) frequency range, the divider 192 with division ratio M is not needed, resulting in a seventh embodiment shown in FIG. 12.

A fourth embodiment of the invention is shown in FIG. 9. Note that it only use one current controlled oscillator namely CCO. The "A", "B" and "C" inputs of the 3-1 multiplexer 200 are used for "wst" case, "typ" case and "bst" case chips. While this embodiment cannot achieve as good performance as that shown in FIG. 6 or FIG. 11, it can be implemented in a much smaller area.

A third embodiment of the invention is shown in FIG. 8. It uses only one divider as opposed to two in FIG. 9. Therefore while it cannot achieve an equivalent performance, it doesn't requires as much area.

A fifth embodiment shown in FIG. 10 achieves an equivalent performance of FIG. 8 and FIG. 9 by replacing the divider block and multiplexer block in FIG. 8 and FIG. 9 with a programmable divider block 190C.

This present invention guarantees that a VCO has vary low gain in the desired Fout(target) frequency range irrespective of process variations. Furthermore when incorporated in a PLL system, it guarantees that the PLL will lock to the desired Fout(target) frequency range, will display very low jitter irrespective of process variations and will be able to maintain this lock over a very wide operating temperature range.

While this invention has thus far been described in conjunction with several preferred embodiments thereof, it will now be readily possible for those skilled in the art to put this invention into practice in various other manner.