1.5 Bootstrapped Pass-Transistor-Based Manchester-Carry-Chain Circuit Suitable for Low-Voltage CMOS VLSI

CMOS Manchester-carry-chain circuit as shown in FIG. 1 based on pass transistors and dynamic logic techniques have been used to implement arithmetic circuit ›N. H. E. Weste and K. Eshraghian, "Principles of CMOS VLSI Design," Addison Wesley: New York, N.Y., 1985; J. Kernhof, M. A. Beunder, B. Hoefflinger, and W. Haas, "High-Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment," IEEE J. Solid-State Circuits, pp. 570-575, June 1989; J. B. Kuo H. J. Liao and H. P. Chen, "A BiCMOS Dynamic Carry-Look-Ahead Adder Circuit for VLSI Implementation of High Speed Arithmetic Unit," IEEE J. Solid-State Circuits, March 1993; and J. B. Kuo, S. S. Chen, C. S. Chang, K. W. Su, and J. H. Lou, "A 1.5 V BiCMOS Dynamic Logic Circuit Using a "BiPMOS Pull-Down" Structure for VLSI Implementation of Full Adders," IEEE Trans. Circuits and Systems-I, Vol. 41, No. 4, pp. 329-332, April 1994!. The Manchester-carry-chain circuit is used to process the propagate (P.sub.i) and generate (G.sub.i) signals produced by the half adders to generate the carry signals (C.sub.i ), wherein a clock signal (CK) is required for the processing. With the pass transistor configuration, Manchester-carry-chain circuit has the smallest transistor count among all carry-chain circuits including domino and other static techniques introduced in the above-mentioned prior art references. The function of the Manchester-carry-chain circuit is:

wherein i=1.about.n, where n is the bit number; C.sub.i is an inverted carry signal; G.sub.i and P.sub.i are the generate and propagate signals (G.sub.i =X.sub.i .multidot.Y.sub.i, P.sub.I =X.sub.i .sym.Y.sub.i) produced from two inputs (X.sub.i, Y.sub.i) to the half adder. In the Manchester-carry-chain circuit, each bit carry signal (C.sub.i ) is low if the generate signal (G.sub.i) is high or if the propagate signal (P.sub.i) is high and the carry signal of the previous bit (C.sub.i-1 ) is low. Pass transistors have been used to control the operation of the Manchester-carry-chain circuit. However, when the Manchester-carry-chain chain is long, as in a 64-bit adder, the ripple-carry propagation delay becomes unacceptable due to the RC delay of the pass transistor. In other words, the density advantage of the Manchester-carry-chain circuit is offset by the drawback in the speed. This is especially serious when the supply voltage is scaled down, which is a trend for deep-submicron VLSI.

A high-speed 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for low-voltage CMOS VLSI is described in this invention, which comprises in a conventional Manchester-carry-chain circuit a bootstrapper circuit consisting essentially of two P-type metal-oxide-semiconductor (PMOS) transistors MPB and MP, each of which having a drain terminal, a source terminal and a gate terminal; one N-type metal-oxide-semiconductor (NMOS) transistor MN having a drain terminal, a source terminal and a gate terminal; a capacitor device having a top plate and a bottom plate; and an inverter having an input terminal and output terminal. Said source terminal of said NMOS transistor MN is earthed, and said input terminal of said inverter is provided with an input signal P.sub.i . Said drain terminal of said PMOS transistor MP and said source terminal of said PMOS transistor MPB are both connected to said bottom plate of said capacitor device. The source terminal of said PMOS transistor MP is connected to a power V.sub.dd, and said drain terminal of said PMOS transistor MPB is connected to said drain terminal of said NMOS transistor MN. The gate terminals of said NMOS transistor MN and PMOS transistor MPB are provided with said input signal P.sub.i . The gate terminal of said PMOS transistor MP and said top plate of said capacitor device are both connected to said output terminal of said inverter. An intermediate node between said drains of said PMOS transistor MPB and said NMOS transistor MN is connected to a gate terminal of a NMOS transistor as a pass transistor in said conventional Manchester-carry-chain circuit so that a carry propagation signal P.sub.i is provided from said intermediate node to said gate terminal of said pass transistor.

Preferably, said capacitor device is a PMOS transistor MPC having a drain terminal, a source terminal and a gate terminal, of which the drain terminal and source terminal are connected with each other. The connected drain terminal and source terminal of PMOS transistor MPC are connected to said drain terminal of said PMOS transistor MP and to said source terminal of said PMOS transistor MPB as said bottom plate, and said gate terminal of PMOS transistor MPC is connected to said output terminal of said inverter as said top plate of said capacitor device.

With the bootstrapped technique, the speed performance of a 4-bit Manchester-carry-chain circuit can be enhanced by 70% at a supply voltage of 1.5 V as compared to the conventional Manchester-carry-chain circuit.

FIG. 1 shows a circuit diagram of a conventional 4-bit Manchester-carry-chain circuit.

FIG. 2a shows a circuit block diagram of a 4-bit Manchester-carry-chain circuit using a 1.5 V bootstrap pass-transistor-based circuit in each Manchester-carry-chain cell thereof.

FIG. 2b shows a detailed circuit diagram of the Manchester-carry-chain cell in FIG. 2a using a 1.5 V bootstrap pass-transistor-based circuit.

FIG. 3a is a Voltage (V) versus time (ns) plot showing transients of the 4-bit Manchester-carry-chain circuit using the 1.5 V bootstrapped pass-transistor-based circuit.

FIG. 3b is a Voltage (V) versus time (ns) plot showing transients of the 4-bit Manchester-carry-chain circuit without the 1.5 V bootstrapped pass-transistor-based circuit.

FIG. 4 shows a delay time (ns) versus bit number of the Manchester-carry-chain circuit using the 1.5 V bootstrapped pass-transistor-based circuit and without.

FIG. 5 shows delay time (ns) versus supply voltage (V) of the 4-bit Manchester-carry-chain circuit using the 1.5 V bootstrapped pass-transistor-based circuit and without.

FIGS. 2a and 2b show a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit according to a preferred embodiment of the present invention. As shown in FIG. 2b, the bootstrapper circuit ›"A 1.5 V Full-Swing Bootstrapped CMOS Large Capacitive-Load Driver Circuit Suitable for Low-Voltage Deep-Submicron CMOS VLSI," U.S. patent application Ser. No. 08/627,482, filed Apr. 4, 1996, Notice of Allowance received!, which functions as an inverter, is used to boost the input signal to the gate of the pass transistors. As shown in FIG. 2b, when the input P.sub.i to a bootstrapper circuit 10 switches from high to low, the output of P.sub.i will change from low to surpass V.sub.dd. When the input P.sub.i to the bootstrapper circuit 10 is high, the PMOS transistor MPB is off and the NMOS transistor MN is on. Therefore, the output of the bootstrapper circuit 10 is pulled low to ground. At the same time, V.sub.I is low, hence the PMOS transistor MP is on and V.sub.b is pull high to V.sub.dd. At this time, the bootstrap transistor MPC, which is made of a PMOS device with its source and drain terminal tied together, stores an amount of (V.sub.dd -.vertline.V.sub.TP .vertline.)C.sub.ox WL charge, where C.sub.ox is unit area gate oxide capacitance (C.sub.ox =.epsilon..sub.ox /t.sub.ox), and V.sub.TP is the threshold voltage of the PMOS device. When the input switches from high to low, the MN turns off and MPB turns on. Meanwhile, V.sub.I changes to high and MP turns off. Since the bootstrap transistor MPC turns off, the evacuated holes from the channel of the PMOS device will make V.sub.b go up to exceed V.sub.dd --the internal voltage overshoot. Consequently, the output P.sub.i of the bootstrapper circuit 10 will also go up to surpass V.sub.dd. The voltage overshoot at the output P.sub.i of the bootstrapper circuit 10, which is supplied to a gate terminal of a NMOS transistor MNP (pass transistor) of a Manchester-carry-chain circuit, enhances the speed performance of the pass-transistor-based Manchester-carry-chain circuit owing to the extra gate overdrive voltage. The advantages of the bootstrapper circuit 10 are especially noticeable for the low supply voltage applications.

FIGS. 3a and 3b show the transients of the 4-bit Manchester-carry-chain circuit using the 1.5 V bootstrapped pass-transistor-based circuit and without, respectively. As shown in the FIGS. 3a and 3b, with the bootstrapper circuit, during the transient, the P.sub.0 signal to gate of the pass transistor can surpass 1.5 V. As a result, the pass transistor can turn on eariler as compared to the one in the conventional Manchester-carry-chain circuit. Consequently, a higher speed can be expected for the Manchester-carry-chain circuit with the bootstrapper circuit. FIG. 4 shows the delay time versus bit number of the Manchester-carry-chain circuit using the 1.5 V bootstrapped pass-transistor-based circuit and without. As shown in FIG. 4, a consistent improvement in speed can be seen for the Manchester-carry-chain circuit with the bootstrapped pass-transistor-based circuit. At 8 bits, the speed enhancement is 2.1 times.

It can be understood from the above description to the preferred embodiment with reference to the drawings that the bootstrapped pass-transistor-based Manchester-carry-chain circuit is especially advantageous for low supply voltage applications. FIG. 5 shows the delay time versus supply voltage of the 4-bit carry look-ahead circuit using the 1.5 V bootstrapped pass-transistor-based circuit and without. As shown in FIG. 5, at a supply voltage of 1.5 V, the improvement is 1.7 times.

It is apparent to people skilled in the art that the bootstrapper circuit 10 in FIG. 2b may be modified by replacing the PMOS transistor MPC with a capacitor, and the modified circuit can be contemplate as an equivalent in function.