US 5,886,701 AGrant
Graphics Rendering Device and Method for Operating Same
Issue Date:1999-03-23
•24 Claims
•35 Drawing Sheets
Abstract
A graphics rendering chip serially renders a stream of geometric primitives to image regions called chunks. A set-up processor in the chip parses rendering commands and the stream of geometric primitives and computes edge equation parameters. A scan-convert processor receives the edge equation parameters from the set-up processor and scan converts the geometric primitives to produce pixel records and fragment records. An internal, double-buffered pixel buffer stores pixel records for fully covered pixel addresses and also stores references to fragment lists stored in a fragment buffer. A pixel engine performs hidden surface removal and controls storage of pixel and fragment records to the pixel and fragment buffers, respectively. An anti-aliasing engine resolves pixel data for one pixel buffer while the pixel engine fills the other pixel buffer with pixel data for the next chunk.
Metadata
Assignee
- Microsoft Corporation
Inventors
- Joseph W. Chauvin
- Steven A. Gabriel
- Howard Good
- Kent E. Griffin
- Mark L. Kenworthy
- William Chambers Powell, III
- George Easton Scott, III
- Michael A. Toelle
- John G. Torborg, Jr.
- James E. Veres
Application Information
Application Number:US 6720862
Filing Date:1996-06-27
Priority Date:1995-08-04
Art Unit:272
Classifications
IPC:
G06F 1500
Field of Search:
345418-20;426-38;501-7
Patent Drawings (35 sheets)
Description
TECHNICAL FIELD
The invention relates to graphics rendering and specifically relates to the architecture and operation of a graphics rendering device called the tiler.
BACKGROUND
With the widespread use of computers in all aspects of modern life, there is an increasing demand to improve the human-machine interface through the use of visual information. Advances in graphical software and hardware have already improved the human-machine interface drastically. Interactive graphics such as windowing environments for desk-top computers, for example, have improved the ease of use and interactivity of computers drastically and are common place today. As the price-performance ratio of hardware drops, the use of computer generated graphics and animation will become even more pervasive. Unfortunately, the cost of producing truly interactive and realistic effects has limited its application. There is a need, therefore, for new graphics processing techniques and architectures that provide more interactive and realistic effects at a lower cost.
Although there are numerous ways to categorize graphics processing, one common approach is to describe an image in terms of the dimensions of the objects that it seeks to represent. For example, a graphics system may represent objects in two dimensions (e.g., having x and y coordinates); in which case the graphics are said to be "two-dimensional", and three dimensions (e.g., having x, y, and z coordinates), in which case the graphics are said to be "three-dimensional" ("3-D").
Since display devices such as cathode ray tubes (CRTs) are two-dimensional ("2-D"), the images displayed by computer graphic systems are generally 2-D. As discussed in greater detail below, however, if the computer maintains a graphical model representing the imaged object in three-dimensional space, the computer can alter the displayed image to illustrate a different perspective of the object in 3-D space. In contrast, although a 2-D graphic image can be transformed prior to display (e.g., scaled, translated, or rotated), the computer can not readily depict the object's appearance from a different perspective in 3-D space.
The increasing ability of modem computers to efficiently handle 2-D and, particularly, 3-D graphics has resulted in a growing variety of applications for computers, as well as fundamental changes in the interface (UI) between computers and their users. The availability of 3-D graphics is becoming increasingly important to the growth of entertainment related applications including production quality film animation tools, as well as lower resolution games and multimedia products for the home. A few of the many other areas touched by 3-D graphics include education, video conferencing, video editing, interactive user interfaces, computer-aided design and computer-aided manufacturing (CAD/CAM), scientific and medical imaging, business applications, and electronic publishing.
A graphics processing system may be thought of as including an application model, application program, graphics sub-system, as well as the conventional hardware and software components of a computer and its peripherals.
The application model represents the data or objects to be displayed, assuming of course that the image processing is based upon a model. The model includes information concerning primitives such as points, lines, and polygons that define the objects' shapes, as well as the attributes of the objects (e.g., color). The application program controls inputs to, and outputs from, the application model-effectively acting as a translator between the application model and graphics sub-system. Finally, the graphics sub-system is responsible for passing user inputs to the application model and is responsible for producing the image from the detailed descriptions stored by the application model.
The typical graphics processing system includes a physical output device which is responsible for the output or display of the images. Although other forms of display devices have been developed, the predominant technology today is referred to as raster graphics. A raster display device includes an array of individual points or picture elements (i.e., pixels), arranged in rows and columns, to produce the image. In a CRT, these pixels correspond to a phosphor array provided on the glass faceplate of the CRT. The emission of light from each phosphor in the array is independently controlled by an electron beam that "scans" the array sequentially, one row at a time, in response to stored information representative of each pixel in the image. Interleaved scanning of alternate rows of the array is also a common technique in, for example, the television environment. The array of pixel values that map to the screen is often referred to as a bitmap or pixmap.
One problem associated with raster graphics devices is the memory required to store the bitmap for even a single image. For example, the system may require 3.75 megabytes (Mb) of random access memory to support a display resolution of 1280.times.1024 (i.e., number of pixel columns and rows) and 24 bits of color information per pixel. This information, which again represents the image of a single screen, is stored in a portion of the computer's display memory known as a frame buffer.
Another problem with conventional raster graphics devices such as CRTs is the relatively quick decay of light emitted by the device. As a result, the display must typically be "refreshed" (i.e., the raster re-scanned) at a rate approaching 60 Hz or more to avoid "flickering" of the image. This places a rigorous demand on the image generation system to supply image data at a fixed rate. Some systems address this problem by employing two frame buffers, with one of the buffers being updated with pixmap information corresponding to subsequent image frame, while the other buffer is being used to refresh the screen with the pixmap for the current image frame.
The demands placed upon the system are further exacerbated by the complexity of the information that often must be processed to render an image from the object stored by the application model. For example, the modeling of a three-dimensional surface is, in itself, a complex task. Surface modeling is performed by the application model and may involve the use of polygon meshes, parametric surfaces, or quadric surfaces. While a curved surface can be represented by a mesh of planar polygons, the "smoothness" of its appearance in the rendered image will depend both upon the resolution of the display and the number of individual polygons that are used to model the surface. The computations associated with high resolution modeling of complex surfaces based upon polygon meshes can be extremely resource intensive.
As intimated above, there is a demand to produce more realistic and interactive images. The term, "real-time," is commonly used to describe interactive and realistic image processing systems. In a "real-time" system, the user should perceive a continuous motion of objects in a scene. In a video game having real-time capabilities, the active characters and view point should respond with minimal delay to a user's inputs, and should move smoothly.
To produce such real-time effects, an image rendering system has to generate a new image at a sufficiently high rate such that the user perceives continuous motion of objects in a scene. The rate at which a new image is computed for display is referred to as the "computational" rate or the "computational frame" rate. The computational rate needed to achieve realistic effects can vary depending on how quickly objects move about the scene and how rapidly the viewing perspective changes. For a typical application, a real-time graphics system recomputes a new image at least twelve times a second to generate a series of images that simulate continuous motion. For high-quality animation applications, however, the computational rate must be significantly higher.
Another critical issue for real-time systems is transport delay. Transport delay is the time required to compute and display an image in response to input from the user, i.e. motion of a joystick to move a character in a scene. To the extent transport delay time is noticeable to a user, "real-time" interactivity is impaired. Ideally, the user should not perceive any transport delay. However, in practice there is always some delay attributed to rendering objects in a scene in response to new inputs and generating a display image. Improvements in real-time interactivity are highly desirable without discarding data, which can interfere with image quality.
As introduced above, conventional graphics systems typically include a frame buffer. To generate an image, the graphic system renders all of the objects in a scene and stores the resulting image in this frame buffer. The system then transfers the rendered image data to a display. In a conventional graphics architecture, the entire frame buffer is erased and the scene is re-rendered to create a next frame's image. In this type of system, every object must be redrawn for each frame because the frame buffer is cleared between frames. Every object therefore is updated at the same rate, regardless of its actual motion in the scene or its importance to the particular application.
This conventional architecture presents several hurdles to producing highly realistic and interactive graphics. First, every object in a scene for a particular frame is rendered with the same priority at the same update rate. As such, objects in the background that have little detail and are not moving are re-rendered at the same rate as objects in the foreground that are moving more rapidly and have more surface detail. As a result, processing and memory resources are consumed in re-rendering background objects even though these background objects do not change significantly from frame to frame.
Another drawback in this conventional architecture is that every object in the scene is rendered at the same resolution. In effect, the rendering resources consumed in this type of approach are related to the size of the screen area that the object occupies rather than the importance of the object to the overall scene. An example will help illustrate this problem. In a typical video game, there are active characters in the foreground that can change every frame, and a background that rarely changes from frame to frame. The cost in terms of memory usage for generating the background is much greater than generating the active characters because the background takes up more area on the screen. Image data must be stored for each pixel location that the background objects cover. For the smaller, active characters however, pixel data is generated and saved for only the pixels covered by the smaller characters. As a result, the background occupies more memory even though it has lesser importance in the scene. Moreover, in a conventional architecture the entire background has to be re-rendered for every frame, consuming valuable processing resources.
One principal strength of the frame buffer approach is that it can be used to build an arbitrary image on an output device with an arbitrary number of primitive objects, subject only to the limit of spatial and intensity resolution of the output device. However, there are several weakness for a graphics system using a frame buffer.
A frame buffer uses a large amount (e.g. 64-28 Mb) of expensive memory. Normal random access memory (RAM) is not adequate for frame buffers because of its slow access speeds. For example, clearing the million pixels on a 1024.times.1024 screen takes 1/4 of a second assuming each memory cycle requires 250 nanoseconds. Therefore, higher speed, and more expensive video RAM (VRAM), or dynamic RAM (DRAM) is typically used for frame buffers. High-performance systems often contain two expensive frame buffers: one frame buffer is used to display the current frame, while the other is used to render the next frame. This large amount of specialized memory dramatically increases the cost of the graphics system.
Memory bandwidth for frame buffers is also a problem. To support processing a graphics image with texturing, color, and depth information stored for each pixel requires a bandwidth of about 1.7 Gigabytes-per-second for processing an image at 30 Hz. Since a typical DRAM is only has a bandwidth of 50 Mb-per-second, a frame buffer must be built from a large number of DRAMs which are processed with parallel processing techniques to accomplish the desired bandwidth.
To achieve real-time, interactive effects, high-end graphics systems use parallel rendering engines. Three basic parallel strategies have been developed to handle the problems with large frame buffer: (1) pipelining the rendering process over multiple processors; (2) dividing frame buffer memory into groups of memory chips each with its own processor; and (3) combining processing circuitry on the frame buffer memory chips with dense memory circuits. These techniques have improved the processing of graphics systems using large frame buffers, but have also dramatically increased the cost of these systems.
Even with expensive parallel processing techniques, it is very difficult to support sophisticated anti-aliasing technique. Anti-aliasing refers to processes for reducing artifacts in a rendered image caused by representing continuous surfaces with discrete pixels. In typical frame buffer architectures, pixel values for an entire frame are computed in arbitrary order. Therefore, to perform sophisticated anti-aliasing, pixel data must be generated for the entire frame before anti-aliasing can begin. In a real-time system, there is not enough time to perform anti-aliasing on the pixel data without incurring additional transport delay. Moreover, anti-aliasing requires additional memory to store pixel fragments. Since a frame buffer already includes a large amount of expensive memory, the additional specialized memory needed to support anti-aliasing makes the frame buffer system even more expensive.
Image compression techniques also cannot be easily used on a graphic system using a frame buffer during image processing. The parallel processing techniques used to accelerate processing in a graphics system with a frame buffer cause hurdles for incorporating compression techniques. During parallel processing, any portion of the frame buffer can be accessed at random at any instance of time. Most image compression techniques require that image data not change during the compression processing so the image data can be decompressed at a later time.
In frame buffer architectures the expensive memory and parallel processing hardware is always under-utilized because only a small fraction of the frame buffer memory or parallel processing units are actively being used at any point in time. Thus, even though a frame buffer architecture includes a large amount of expensive memory and processing hardware, this hardware is not fully utilized.
Low cost, high-quality, real-time processing of 3-D graphics images without using a large expensive frame buffer, or parallel processing techniques has been an elusive quest for the last three decades. As is apparent from the issues outlined above, there is a need for an improved architecture capable of generating high-quality images, at a much lower cost.
SUMMARY OF THE INVENTION
The invention provides a novel graphics rendering device referred to as the "tiler." The tiler receives sets of geometric primitives corresponding to image regions called "chunks" and generates resolved image data for pixel locations in the chunk. The tiler rasterizes each geometric primitive to generate pixel data for pixel locations in the chunk either fully or partially covered by the primitive. The tiler stores pixel data for fully covered pixels in a pixel buffer, and stores a fragment list of partially covered pixels in a fragment buffer. To perform hidden surface removal, a pixel engine in the tiler performs depth compare operations between generated pixel data and pixel data in the pixel buffer.
After rasterizing geometric primitives for a chunk, the tiler resolves the filly covered pixels and the fragment lists to compute resolved pixel values for pixel locations in the chunk. The pixel buffer and fragment buffers are designed to allow a scan convert engine in the tiler to rasterize primitives for a chunk at the same time as an anti-aliasing engine resolves the fragment lists. Processing chunks of an image in this fashion hides the overhead associated with processing fragment lists for pixel locations in a chunk since the tiler resolves fragments in a post-processing step as it rasterizes primitives for another chunk.
The tiler architecture supports texture mapping in an environment with high latency for fetching texture data from memory. To hide the latency, one implementation of the tiler employs a pixel queue, which serves as a FIFO buffer for partially rendered pixel data. The scan convert block scans primitives, computes texture coordinates and filter parameters, and then stores this data in the FIFO queue. A texture cache control receives the texture coordinates from the scan convert engine, fetches a block (or blocks) of texture data to satisfy the texture request, and stores them in a texture cache on the tiler. Then, to perform a texture map operation or shadowing operation, a texture filter engine reads the texture coordinates from the queue and makes a request for the texture data from the texture cache. The texture filter engine filters texture data from the texture cache to compute filtered color component values.
The tiler supports a number of rendering modes. In texture modulation mode, the texture filter engine modulates interpolated values from the scan convert engine with the filtered values to compute composed pixel values. The pixel engine can combine interpolated or composed values with pixel values stored in the pixel buffer and fragment buffer as well.
In one implementation, the tiler includes a decompression engine to decompress compressed texture data. The decompression engine employs either a lossy or lossless form of decompression. The tiler also includes a compression engine to compress pixel data after it is resolved in the anti-aliasing engine.
Further advantages and features will become apparent with reference to the following detailed description and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an image processing system.
FIG. 2 is a block diagram of the system environment for an embodiment of the invention.
FIG. 3 is a block diagram of system architecture for an embodiment.
FIG. 4A is a block diagram of image processing hardware for an embodiment.
FIG. 4B is a block diagram illustrating portions of an image processor for rendering geometric primitives in an embodiment.
FIGS. 5A and 5B are flow diagrams illustrating an overview of the rendering process in an embodiment.
FIG. 6 is a flow diagram illustrating an overview of the display generation process of an embodiment.
FIG. 7 is a diagram illustrating one aspect of display generation in terms of frame periods in an embodiment.
FIG. 8 is a block diagram of a digital signal processor (DSP) in an embodiment.
FIGS. 9A-C are block diagrams illustrating alternative embodiments of a tiler.
FIG. 10 is a block diagram illustrating a system for accessing texture data from memory.
FIG. 11 is a block diagram illustrating a system for accessing texture data from memory.
FIGS. 12A-B are block diagrams illustrating alternative implementations of a gsprite engine.
FIG. 13 is a block diagram of a compositing buffer in an embodiment.
FIG. 14 is a block diagram of a digital-to-analog converter (DAC) in an embodiment.
FIGS. 15A-F are flow diagrams illustrating aspects of pixel and fragment generation in three alternative embodiments.
FIG. 16 is a flow diagram illustrating background sorting of fragments in an embodiment.
FIG. 17 is a block diagram illustrating one implementation of a pixel fragment resolution subsystem.
FIG. 18 is a block diagram illustrating another implementation of a pixel fragment resolution subsystem.
FIG. 19 is a flow diagram illustrating fragment blending in one embodiment of the invention.
FIG. 20 is a block diagram illustrating the compression architecture in one embodiment of the invention.
FIG. 21 is a block diagram illustrating an implementation of a texture and shadow filter.
FIG. 22 is a block diagram illustrating an implementation of the key generator in FIG. 21.
FIG. 23 is a block diagram illustrating an implementation of the color interpolators in FIG. 21.
FIG. 24 is a block diagram illustrating an implementation of the shadow filter accumulator in FIG. 21.
FIG. 25 is a block diagram illustrating an implementation of the accumulator and post processor in FIG. 21.
SYSTEM OVERVIEW
In the following detailed description, we describe the tiler in context of an image processing system.
The image processing system supports real-time image rendering and generation for both graphics and video processing. Due to the novel architecture and image processing techniques employed in the system, it can produce sophisticated real-time 3-D animation at a significant cost savings over present graphics systems. In addition to graphics processing, the system supports video processing such as video editing applications, and can also combine video and graphics. For instance, the system can be used to apply video to graphical objects, or conversely, can be used to add graphical objects to video data.
The system supports a wide range of interactive applications. Its ability to support advanced real-time animation makes it well-suited for games, educational applications, and a host of interactive applications. The system supports sophisticated user interfaces including 3-D graphics or combined graphics and video. Improving upon the limited graphics capabilities of today's windowing environments for personal computers, the system can support improved 3-D graphical user interfaces for applications ranging from office information processing on desk-top computers to interactive television applications in a set-top box. The system makes very efficient use of memory and processor time and therefore can provide impressive image processing and display without unduly hindering performance of the application or responsiveness of the user interface to user actions.
FIG. 1 is a block diagram of the image processing system 100. The image processing system comprises an image data source and store 102, an image preprocessor 104, an image processor 106, and a display device 108, if immediate display of rendered images is desired. The elements in the system communicate through a system interface 110. The image data source and store 102 supplies image data to the system, and stores image data and commands. The image preprocessor 104 is responsible for manipulating the image data to prepare it for rendering. Examples of preprocessing functions include: defining objects in terms of geometric models, defining lighting and shadowing models, determining object locations, determining the location of a viewpoint and light sources, and geometry processing.
The image processor 106 renders the images, and generates a display image to be displayed on the display device 108. Rendering refers to the process of creating images from models and includes such functions as geometry processing (note that geometry processing can also be a preprocessing function), visible-surface determination, scan conversion, and lighting, to name a few. After rendering an image or parts of an image, the image processor 106 transfers rendered image data to the display device for display.
Below, we describe several features of the image processing system 100 in detail with reference to specific hardware and software architectures. However, it is important to note that the image processing described below can be implemented in a variety of alternative architectures.
The image processing system 100 achieves a vast price-performance improvement over existing high quality 3-D graphics systems known to the inventors. A number of advances in computer graphics contribute to this improvement. These advances include: composited image layers, image compression, chunking, and multi-pass rendering. We introduce these advances here, and describe these and other advances in more detail below.
Composited Image Layers (Gsprites)
In our system, multiple independent image layers may be composited together at video rates to create the output video signal. These image layers, which we refer to as generalized gsprites, or gsprites, can be rendered into and manipulated independently. The system will generally use an independent gsprite for each non-interpenetrating object in the scene. This allows each object to be updated independently, so that object update rate can be optimized based on scene priorities. For example, an object that is moving in the distant background may not need to be updated as often, or with as much accuracy, as a foreground object.
Gsprites can be of arbitrary size and shape. In one implementation, we use rectangular gsprites. Pixels in the gsprite have color and alpha (opacity) information associated with them, so that multiple gsprites can be composited together to create the overall scene.
Several different operations may be performed on gsprites at video rates, including scaling, rotation, subpixel positioning, and transformations to mimic motion, such as affine warps. So, while gsprite update rates are variable, gsprite transformations (motion, etc.) may occur at full video rates, resulting in much more fluid dynamics than could be achieved by a conventional 3-D graphics system that has no update rate guarantees.
Many 3-D transformations can be simulated by 2-D imaging operations. For example, a receding object can be simulated by scaling the size of the gsprite. By utilizing 2-D transformations on previously rendered images for intermediate frames, overall processing requirements are significantly reduced, and 3-D rendering power can be applied where it is needed to yield the highest quality results. This is a form of temporal level of detail management.
By using gsprite scaling, the level of spatial detail can also be adjusted to match scene priorities. For example, background objects, cloudy sky, etc., can be rendered into a small gsprite (low resolution) which is then scaled to the appropriate size for display. By utilizing high quality filtering, the typical low resolution artifacts are not as noticeable.
A typical 3-D graphics application (particularly an interactive game) trades off geometric level of detail to achieve higher animation rates. Gsprites allow the system to utilize two additional scene parameters--temporal level of detail and spatial level of detail--to optimize the effective performance as seen by the user. The spatial resolution at which the image of an object is rendered does not have to match the screen resolution at which it will be rendered. Further, the system can manage these trade-offs automatically without requiring application support.
Image Compression
Perhaps the most significant factor in determining system cost and performance is memory. A traditional high-end 3-D graphics system, for example, has over 30 Mbytes of memory, including frame buffers (double buffered), a depth buffer, a texture buffer, and an anti-aliasing buffer. And most of this is specialized memory which is significantly more expensive than DRAM. Memory bandwidth is always a critical bottleneck. The cost of high performance systems are often driven by the need to provide numerous banks of interleaved memory to provide adequate bandwidth for pixel and texture data accesses.
The system broadly applies image compression technology to solve these problems. Image compression has traditionally not been used in graphics systems because of the computational complexity required for high quality, and because it does not easily fit into a conventional graphics architecture. By using a concept we call chunking (described below), we are able to effectively apply compression to images and textures, achieving a significant improvement in price-performance.
In one respect, graphics systems have employed compression to frame buffer memory. High end systems utilize eight bits for each of three color components, and often also include an eight bit alpha value. Low end systems compress these 32 bits per pixel to as few as four bits by discarding information and/or using a color palette to reduce the number of simultaneously displayable colors. This compression results in very noticeable artifacts, does not achieve a significant reduction in data requirements, and forces applications and/or drivers to deal with a broad range of pixel formats.
The compression used in our system can achieve very high image quality yet still provide compression ratios of 10:1 or better. Another benefit of our approach is that a single high quality image format can be used for all applications, as distinguished from the standard PC graphics architecture which requires a trade-off between spatial resolution and color depth.
Chunking
Another significant advance in our system is referred to as chunking. A traditional 3-D graphics system (or any frame buffer for that matter), can be (and is) accessed randomly.
Arbitrary pixels on the screen can be accessed in random order. Since compression algorithms rely on having access to a fairly large number of neighboring pixels (in order to take advantage of spatial coherence), compression can only be applied after all pixel updates have been made, due to the random access patterns utilized by graphics algorithms. This makes the application of compression technology to display buffers impractical.
This random access pattern also means that per-pixel hidden surface removal and anti-aliasing algorithms must maintain additional information for every pixel on the screen. This dramatically increases the memory size requirements, and adds another performance bottleneck.
Our system takes a different approach. A scene, or portions of a scene, can be divided into pixel regions (32.times.32 pixels in one specific implementation), called chunks. In one implementation, the system divides the geometry assigned to gsprites into chunks, but an alternative implementation could perform chunking without gsprites. The geometry is presorted into bins based on which chunk the geometry will be rendered into. This process is referred to as chunking. Geometry that overlaps a chunk boundary is preferably referenced in each chunk it is visible in. As the scene is animated, the data structure is modified to adjust for geometry that moves from one chunk to another.
Chunking provides several significant advantages. The use of chunking provides an effective form of compression. Since all the geometry in one chunk is rendered before proceeding to the next, the depth buffer need only be as large as a single chunk. By using a relatively small chunk size such as 32.times.32 pixels, the depth buffer can be implemented directly on the graphics rendering chip. This eliminates a considerable amount of memory, and also allows the depth buffer to be implemented using a specialized memory architecture which can be accessed with very high bandwidth and cleared during double buffer operations, eliminating the traditional frame buffer memory clearing overhead between frames.
Anti-aliasing is also considerably easier since each chunk can be dealt with independently. Most high-end Z-buffered graphics systems which implement anti-aliasing utilize a great deal of additional memory, and still perform relatively simplistic filtering. With chunking however, the amount of data required is considerably reduced (by a factor of 1000), allowing practical implementation of a much more sophisticated anti-aliasing algorithm.
In addition to Z-buffering and anti-aliasing, the system can also simultaneously support translucency in a correct and seamless manner. While a chunk is being built, the system can perform both anti-aliasing and translucency computations on another chunk. In other words, in the time required to build a chunk, the system can perform anti-aliasing and translucency processing on another chunk. The system can "ping-pong" between chunks, and thus perform sophisticated processing without adding delay in processing an image for real time applications.
Yet another advantage is that chunking enables block oriented image compression. Once a chunk has been rendered (and anti-aliased), it can then be compressed with a block transform based compression algorithm. Therefore, in addition to the compression achieved from rendering chunks separately, chunking supports more sophisticated and adaptable compression schemes.
Multi-Pass Rendering
Another advantage of the architecture of our system is the opportunity for 3-D interactive applications to break out of the late 1970's look of CAD graphics systems: boring lambertian Gouraud-shaded polygons with Phong highlights. Texture mapping of color improves this look but imposes another characteristic appearance on applications. In the 1980's, the idea of programmable shaders and procedural texture maps opened a new versatility to the rendering process. These ideas swept the off-line rendering world to create the high-quality images that we see today in film special effects.
The rigid rendering pipelines and fixed rendering modes of today's typical high-end 3-D graphics workstations make it impossible to implement such effects without drastic reductions in real-time performance. As a result, users who require real-time display must put up with the limited rendering flexibility.
By reducing the bandwidth requirements using the techniques outlined above, the system of the present invention can use a single shared memory system for all memory requirements including compressed texture storage and compressed gsprite storage. This architecture allows data created by the rendering process to be fed back through the texture processor to use as data in the rendering of a new gsprite. Because of this support for feedback, the system can perform efficient multi-pass rendering.
By coupling efficient multi-pass rendering with a variety of compositing modes and a flexible shading language, the system can provide a variety of rendering effects in real-time that have previously been the domain of off-line software renderers. This includes support of functions such as shadows (including shadows from multiple light sources), environment mapped reflective objects, spot lights, ground fog, realistic underwater simulation, etc.
In one embodiment, the image processing system (100) includes a combination of software and hardware. In the following section, we describe the system environment below with reference to a hardware and software architecture. Where possible, we describe alternative architectures. However, the software and hardware architectures can vary, and therefore are not limited to the specific examples provided below.
The image processing system, or portions of it, can be implemented in a number of different platforms including desktop computers, set-top boxes, and game systems.
FIG. 2 is a block diagram of a computer system 130 in which the image processing system can be implemented. The computer system 130 includes a processor 132, main memory 134, memory control 136, secondary storage 138, input device(s) 140, display device 142, and image processing hardware 144. Memory control 136 serves as an interface between the processor 132 and main memory 134; it also acts as an interface for the processor 132 and main memory 134 to the bus 146.
A variety of computer systems have the same or similar architecture as illustrated in FIG. 2. The processor within such systems can vary. In addition, some computer systems include more than one processing unit. To name a few, the processor can be a Pentium or Pentium Pro processor from Intel Corporation, a microprocessor from the MIPS family from Silicon Graphics, Inc., or the PowerPC from Motorola.
Main memory 134 is high speed memory, and in most conventional computer systems is implemented with random access memory (RAM). Main memory can interface with the processor and bus in any of variety of known techniques. Main memory stores 134 programs such as a computer's operating system and currently running application programs. Below we describe aspects of an embodiment with reference to symbolic representations of instructions that are performed by the computer system. These instructions are sometimes referred to as being computer-executed. These aspects of the embodiment can be implemented in a program or programs, comprising a series of instructions stored on a computer-readable medium. The computer-readable medium can be any of the devices, or a combination of the devices described herein, in connection with main memory or secondary storage.
The bus 146 interconnects the memory control 136, secondary storage 138, and the image processing hardware 144. In one implementation for example, the bus is a PCI bus. The PCI standard is well-known, and several computer system boards are designed to support this standard. Computer systems having other bus architectures can also support the image processing system. Examples include an ISA bus, EISA bus, VESA local bus, and the NuBus.
The display device 142 is a color display, with continuous refresh to display an image. The display device in one embodiment is a cathode ray tube (CRT) device, but it can also be a liquid crystal display (LCD) device, or some other form of display device.
The secondary storage device 138 can include a variety of storage media. For example, the secondary storage device can include floppy disks, hard disks, tape, CD-ROM, etc. and other devices that use electrical, magnetic, optical or other recording material.
The input device(s) 140 can include a keyboard, cursor positioning device such as a mouse, joysticks, as well as a variety of other commercially available input devices.
In one implementation detailed below, the image processing hardware 144 is implemented on board that couples with the computer system through a PCI bus. In an alternative implementation, the image processing hardware can be located on a system board along with a processor or other image processing hardware and memory. For example, in a game system, image processing hardware is typically located on the mother board. Similarly, image processing hardware in a set-top box can also be located on the mother board.
While we have outlined the architecture of a computer system, we do not intend to limit our invention to the system architecture illustrated in FIG. 2. Our image processing system can be implemented in game systems, set-top boxes, video editing devices, etc. Below we describe an embodiment of an image processing system in the environment of the system architecture shown in FIG. 2. We describe alternative implementations throughout the following description, but we do not intend our description of alternatives to be a complete listing of other possible implementations. Based on our detailed description below, those having ordinary skill in the art can implement our the image processing system, or aspects of it, on alternative platforms.
FIG. 3 is a block diagram illustrating the relationship between the software and hardware in one embodiment. In this embodiment, the image processing system is implemented using processing resources of the processor of the host computer and the image processing hardware 144. The image processing hardware 144 is implemented on an expansion board 164 which includes a processor (e.g. a Digital Signal Processor) 166 and image processing circuitry 168. The processors of the host computer 130 and the image processing board 164 share image processing tasks. Below we outline generally the functions performed by the host computer 130 and the image processing board 174.
Graphics support software 160 executes on the host computer system 130 and communicates with the image processing board 164 through the hardware abstraction layer (HAL) 162. The image processing board 164 includes a programmable digital signal processor called the DSP 166 and additional image processing hardware 168 detailed below.
The graphics support software 160 can include functions to support memory management, view volume culling, depth sorting, chunking, as well as gsprite allocation, transformation, and level of detail. The graphics support software can include a library of graphics functions, accessible by graphics applications, to perform the functions enumerated here.
The graphics support software 160 includes functions that support the gsprite paradigm introduced above. As indicated above, gsprites are rendered independently, and do not need to be rendered on every frame. Instead, changes in position of a gsprite can be approximated with affine or other transformations. The graphics support software 160 provides functions to help assign an object or objects to a gsprite and to track motion data describing the position and motion of the gsprite. The graphics support software also provides functions to determine when a rendered gsprite needs to be updated. The need to update a gsprite can vary depending on object movement, viewpoint movement, lighting changes, and object collisions.
We provide further detail with respect to the functions of the graphic support software below. The image processing board 164 performs low level geometry processing, including transforms, lighting and shading, texturing, anti-aliasing, translucency, etc. In one embodiment, the DSP 166 is responsible for front end geometry processing and lighting computations, but a number of these functions can be performed by the processor 132 of the host.
Overview of the Image Processing Board
FIG. 4A is a block diagram illustrating the image processing board 174. The image processing board 174 communicates with the host computer through the bus 146. It includes a DSP 176, tiler 200, shared memory 216, the gsprite engine 204, compositing buffer 210, and a digital-to-analog converter (DAC) 212. The bus 146 (FIG. 2) transfers commands and data between the host and the DSP 176. In response to commands from the host, the image processing board 174 renders images and transfers display images to a display device 142 (FIG. 2) through the DAC 212.
In the embodiment illustrated in FIGS. 2-4A, the host processor and the DSP share the finctions of the image preprocessor of FIG. 1. The image processor comprises the tiler 200, gsprite engine 204, compositing buffer 210, and DAC 212. Below, we provide more detail regarding these elements. It should be kept in mind, however, that the implementation of the image processing system can vary.
The shared memory 202 stores image data and image processing commands on the image processing board 174. In one embodiment, the shared memory is used to store gsprite and texture data in compressed form, DSP code and data, and various buffers used to transfer data between processing subsystems.
The DSP 176 is responsible for video compression/decompression and front-end graphics processing (transformations, lighting, etc.). Preferably, the DSP should support floating point and integer computations greater than 1000 MFLOPS/MOPS.
The tiler 200 is a VLSI chip which performs scan-conversion, shading, texturing, hidden-surface removal, anti-aliasing, translucency, shadowing, and blending for multi-pass rendering. The resulting rendered gsprite chunks are then compressed and stored in compressed form in the shared memory. The tiler additionally performs decompression and recompression of gsprite data in support of video and windowing operations.
The gsprite engine 204 operates at video rates to address and decompress the gsprite chunk data and perform the necessary image processing for general affine transformations (which include scaling, translation with subpixel accuracy, rotation, reflection and shearing). After filtering, the resulting pixels (with alpha) are sent to the compositing buffers where display pixel data is calculated.
Gsprite chunk data is processed a number of scan lines at a time for display. In one implementation, chunk data is processed 32 scan lines at a time. The compositing buffer (210) includes two 32 scan line color buffers which are toggled between display and compositing activities. The compositing buffer also includes a 32 scan line alpha buffer which is used to accumulate alpha for each pixel.
The DAC 212 includes a R G B video DAC and corresponding video port 214, to video editing devices. Individual components can be used to implement the functionality of the DAC.
System Operation
FIGS. 5A and 5B are flow diagrams illustrating steps in rendering an image in the image processing system. Before the image processor 106 begins rendering an image for the view space, the image preprocessor 104 determines object and viewpoint locations (240). In the embodiment illustrated in FIGS. 2 and 3, the graphics support software 160, running in the host computer system 132, determines the object and viewpoint locations from data provided by a graphics application. The graphics application, running on the host processor, defines models representing the relevant objects, and supplies a modeling transform, which is used to place the object with other objects in "world" coordinates.
Next, the image preprocessor 104 selects potentially visible objects (242). It determines potentially visible objects based on the view volume. The view volume is a three-dimensional space in world coordinates that provides the boundaries for a scene. The preprocessor selects potentially visible objects by traversing objects and determining whether their boundaries intersect the view volume. Objects that intersect the view volume are potentially visible in the geometric or spatial sense.
In some cases, it is useful to determine "temporally" potentially visible objects outside the current view volume, to account for future changes in the scene. This enables the system to adjust for rapid changes in the view volume. In typical 3-D graphics systems, the only way to respond to this rapid change is to completely generate a new scene based on the changed input, interposing significant transport delay. Such a long delay has negative effects on the user, creating problems such as over-control and nausea. To reduce this delay, the image preprocessor of the present invention can calculate the location of objects positioned in an extended range outside the visible range, and the image processor can render and store images within this extended range. Using the affine transform capability of the system, viewpoint input for a subsequent frame can be used to reposition the gsprites from this extended range reducing system transport delay to less than 2 computational frames. Such a short transport delay is unachievable with current 3-D graphics hardware systems known to the inventors, and will enable much higher quality simulations with much better user immersion.
The image preprocessor determines the configuration of gsprites for the image (244). This step involves finding how to map potentially visible objects to gsprites. As part of this process, the image preprocessor 104 allocates gsprites, which includes creating a gsprite data structure to store image data corresponding to one or more potentially visible objects. If processing resources allow, each non-interpenetrating object in the scene is assigned to an independent gsprite. Interpenetrating or self-occluding objects may be processed as a single gsprite.
The image preprocessor 104 can aggregate gsprites when the image processor does not have the capacity to composite the gsprites at the desired computational frame rate or there is insufficient system memory to store the gsprites. Rendering to separate gsprites will always be more computationally efficient, so if the system has the memory and compositing capacity, non-intersecting objects should be rendered into separate gsprites. If the system is incapable of storing or generating a display image based on a current assignment of gsprites, some gsprites can be aggregated to alleviate this problem.
After an object or objects are assigned to gsprites, the image processor divides the gsprites into image regions called "chunks" (248). The image preprocessor loops on gsprites and divides the gsprites into chunks (246, 248). In one embodiment, this process includes transforming bounding volumes of objects to the view space and finding rectangular image regions that enclose the transformed bounding volumes. These image regions define the dimensions of the gsprite in terms of the two-dimensional space to which the gsprite's object or objects are rendered. The gsprite is divided into chunks by dividing the rectangular image region into chunks and associating these chunks with the gsprite data structure.
As an optimization, the transformed bounding volume can be scaled and/or rotated so that the number of chunks required to render the gsprite is minimized. Because of this added transformation (scaling or rotating), the space to which the objects assigned to the gsprite are rendered is not necessarily screen space. This space is referred to as gsprite space. In the process of generating a display image, the gsprite should be transformed back to screen space.
The next step is determine how to divide the object geometry among the chunks (250). The image preprocessor determines how the geometric primitives (e.g. polygons) should be divided among the chunks by transforms the polygons to 2-D space (252) and determining which chunk or chunks the polygons project into. Due to the expense of clipping polygons, the preferred approach is to not clip the polygons lying at the edge of a chunk. Instead, a chunk includes polygons that overlap its edge. If a polygon extends over the border of two chunks, for example, in this approach the vertices of the polygon are included in each chunk.
The image preprocessor then queues the chunk data for tiling. Tiling refers to the process of determining pixel values such as color and alpha for pixel locations covered or partially covered by one or more polygons.
Decision step (254) (FIG. 5B) and the step (256) following it represents the process of tiling the polygons within the chunk. While the image processor has included polygons that overlap the boundaries of the current chunk, it only produces pixels that lie within the chunk. The produced pixels include information for antialiasing (fragment records), which are stored until all pixels have been generated.
After completing the tiling of polygons in a chunk, the image processor resolves the anti-aliasing data (such as fragment records) for the pixels (258). In one embodiment, the tiler 200 uses double buffering to resolve a previous chunk while the next is tiled. Alternatively, the tiler can use a common buffer with a free list. The free list represents free memory in the common buffer that is allocated as new fragment records are generated and added to when fragment records are resolved. A combination of double buffering and common memory can be used as well.
The image processor compresses the resolved chunk using a compression scheme described further below (260). As the image processor resolves a block of pixels, it can compress another block. The image processor stores the compressed chunk in shared memory (262).
FIG. 6 is a flow diagram illustrating the steps executed to display an image. On the image processing board 174 described above, images are read from shared memory 216, transformed to physical output device coordinates by the gsprite engine 204, composited in the compositing buffer 210, transferred to the DAC 212, and then transferred to an output device.
During the display process, the image processor accesses a list of gsprites to be displayed for the current frame. In the process of determining the gsprite configuration, the image preprocessor determines the depth order of gsprites (280). As noted above, one object is preferably assigned to a gsprite. However, the image preprocessor can assign more than one object to a gsprite, for example, to accommodate processing constraints of a particular image processor being used in the system. The image preprocessor sorts objects in Z-order, i.e. in distance from the viewpoint. In addition to sorting objects, it sorts gsprites in depth order as well and stores this depth data in the gsprite data structures.
The decision step (282) in FIG. 6 represents a loop on gsprites in the display process. The steps within this loop can include 1) calculating a transform for a rendered gsprite; and 2) building a gsprite display list to control how gsprites are displayed. These steps are described below.
For gsprites in the potentially visible range, the image processor calculates gsprite transforms. A gsprite transform refers to a transformation on a rendered 2-D gsprite. In one embodiment, the image processor can perform a transformation on a gsprite to reduce rendering overhead. Rather than rendering each object for every frame, the image processor reduces rendering overhead by re-using a rendered gsprite.
It is not necessary to compute a gsprite transform for every frame of image data. For instance, if a gsprite is rendered for the current frame of image data, it may not need to be transformed, unless e.g. the gsprite has been transformed to better match the bounding box for the object. In addition, some gsprites may not need to be re-rendered or transformed because the object or objects assigned to them have not changed and are not moving. As such, the step of transforming a gsprite is optional.
The gsprite may be multiplied by the unity matrix in cases where the position of the gsprite has not changed. This may apply, for example, in cases where the image processor has rendered the gsprite for the current frame, or where the gsprite position has not changed since it was originally rendered.
To specify how gsprites are to be displayed, the image processor creates a gsprite display list. The display list refers to a list or lists that define which gsprites are to be displayed on the display screen. This concept of display list can also apply to other output devices for presenting a frame of image data. The image processor uses the display list in mapping and compositing rendered gsprites to the physical device coordinates. While the step of building the display list is illustrated as part of a loop on gsprites, it is not necessary that the list or lists be generated specifically within this loop.
The display list can refer to a list of gsprites or a list of gsprites per band. A "band" is a horizontal scanline region of a display screen. For instance, in one embodiment a band is 32 scanlines high by 1344 pixels wide. The display list can include a separate list of gsprites for each band, in which case the band lists describe the gsprites impinging on the respective bands. Alternatively, the display list can be comprised of a single list implemented by tagging gsprites to identify which bands the gsprites impinge upon.
The display list in the illustrated embodiment is double-buffered. Double buffering enables the system to generate one display list while it reads another. As the system calculates the gsprite transforms and build the display list for one frame, it reads the display list for another frame and displays the image data in this list.
Because of the double buffering, the steps shown in FIG. 6 are over-lapped: the image preprocessor performs steps (280-286) for one frame while the image processor performs steps (290-298) for another frame.
FIG. 7 is a block diagram illustrating the timing of these steps. After the system completes steps (280-286) (FIG. 6) for a frame 310, it waits for a frame sync signal (vertical retrace) and then performs the buffer swap. The display list it has just created is then used to determine the gsprites to be displayed in the current frame 312. While that display list is processed 312, gsprite transforms are computed and a display list is constructed for a next frame 314. In the next frame, the gsprite transforms and display list that were generated in the previous frame 314 are then used to generate the display image 316.
The image processor converts gsprites to output device coordinates based on the list of gsprites in the display list. The image processor reads gsprite data from shared memory, including color, alpha, and data identifying the gsprite's position. Based on this data, the image processor determines the color and alpha for pixels covered by the gsprite.
In one embodiment, the image processor loops on each band, transforming gsprites that impinge upon that band according to the gsprite display list. We will describe this display process in more detail below.
After transforming gsprite data, the image processor composites the resulting pixel data. This includes computing the color and alpha for pixels in output device coordinates based on the gsprite transforms. The image processor transforms the pixel data for gsprites in the display list and then composites the transformed pixel data. The process involves determining the color and alpha at a pixel location based on the contribution of one or more pixel values from gsprites that cover that pixel location.
In one embodiment, the image processor loops on bands and composites pixel data for each band. The image processor double buffers pixel data: it transforms and composites gsprite data for a band in one buffer while it displays composited pixel data for another band.
After compositing pixel data, the image processor then transfers composited pixel data to an output device. The most typical output device used in connection with this system is, of course, a display. To display the pixel data, it is converted to a format compatible with the display.
Having described system operation of an embodiment, we now provide more detail regarding the image processing board.
The Image Processing Board
In the implementation shown in FIG. 4A, the shared memory 216 comprises 4 Mbytes of RAM. It is implemented using two 8-bit Ram bus channels. The shared memory is implemented with RDRAM devices but the specific amount and type of memory can vary.
FIG. 8 is a block diagram illustrating the DSP 336 on the image processing board 174. The DSP 336 is responsible for parsing the command stream from the host processor and performing some video processing, and front end geometry processing. The DSP performs front end geometry and lighting calculations used for 3-D graphics. This includes model and viewing transformations, clipping, and lighting. Portions of the gsprite animation management are also handled in the DSP such as gsprite motion extrapolation.
Rendering commands are stored in main memory buffers and DMAed to the image processing board 174 over the PCI bus and through the PCI bus controller 342. These commands are then buffered in the shared memory 216 on the board until needed by the DSP 336 (FIG. 8).
The DSP core 338 includes a processor for performing the image processing computations described above. In addition the DSP core performs scheduling, and resource management.
The Memory interface 340 supports high speed data transfers, e.g. 64 bits at 80 MHz. It is designed to interface with conventional DRAM and SDRAM devices. The tiler 200 is designed to directly connect to this bus, simulating the memory timing required by the DSP.
The data formatter and converter 346 in the DSP formats rendering instructions for the tiler. This block converts floating point color components into integer and packs them into the tiler specific data structures. It also buffers up a complete command and DMAs it directly to a memory buffer in shared memory. These rendering instructions are later read by the tiler when it is ready to perform the operations.
Among its formatting tasks, the data formatter and converter 346 formats triangle command data for the tiler. R G B .varies. (alpha) data which is calculated by the DSP (336) in floating point is converted to 8 bit integer. Coordinate information is converted from floating point to 12.4 fixed point. The data is packed into 64 bit words and transferred in a contiguous block to the shared memory to optimize bandwidth.
The display memory management unit (MMU) 344 is used for desktop display memory. It traps PCI accesses within a linear address range that is allocated as the desktop display memory. It then maps these accesses to image blocks stored in shared memory.
The architecture of the image processing board (FIG. 4A, 174) is relatively independent of the specific DSP. However, the DSP should preferably have significant floating point performance. Suitable DSPs include the MSP-1 from Samsung Semiconductor and TriMedia from Phillips Semiconductor. These specific DSPs are two examples of DSPs that provide sufficient floating point performance.
FIG. 9A is a block diagram of the tiler 200 on the image processing board 174. The tiler is responsible for 2-D and 3-D graphics acceleration, and for shared memory control. As shown in the block diagram of the image procession board, the tiler connects directly to the DSP (176, FIG. 4), the gsprite engine 204, and the shared memory system 216.
The functional blocks shown in the block diagram above are described in this section.
The tiler 378 includes a number of components for primitive rendering. The command and memory control 380 includes an interface to shared memory 216, the gsprite engine 204, and the DSP 176. Accesses to memory from the tiler, DSP, and gsprite engine are arbitrated by this block. A queue is provided to buffer read accesses.
The setup block 382 calculates the linear equations which determine the edge, color, and texture coordinate interpolation across the surface of the triangle. These equations are also used to determine which texture blocks will be required to render the triangle. The edge equations are also passed to the scan conversion block 394 and are stored in the primitive registers 396 until required by the scan convert engine 398.
The setup block 382 includes three components: the vertex input processor 384, vertex and control registers 386, and the setup engine 388. The vertex input processor 384 parses the command stream from the DSP. The vertex and control registers 386 store the information necessary for processing polygons or other geometric primitives. Triangle processing is used in this specific embodiment, and the tiler 200 includes registers for six vertices (three for each triangle) to allow double buffering of triangle processing. The setup engine 388 calculates the differentials for color, depth, edges, and texture coordinate interpolation across the surface of the triangle. These equations are also used to determine which texture blocks are used to render the triangle. The setup engine also pre-fetches texture chunks so that they are available when needed by the scan convert engine 398.
The setup engine 388 also communicates with the texture read queue 390, and a texture address generator 392. The texture read queue 390 buffers read requests for texture blocks from shared memory. While we use the term "texture" in referring to the portions of the tiler used to retrieve image data blocks from memory, it should be understood that this term can refer to texture maps, shadow maps, and other image data used in multi-pass rendering operations. The texture address generator 392 determines the address in memory of the requested chunks and sends texture read requests to the command and memory control 380. The texture address generator 392 includes a memory management unit that controls the writing of image data to the texture cache.
The scan convert block 394 receives differentials and other vertex data from the setup block and generates pixel data. The scan convert block 394 includes primitive registers 396, and the scan convert engine 398. The primitive registers 396 store the equation parameters for each triangle parameter. The primitive registers include registers to store multiple sets of equations so that the scan convert engine does not stall waiting for texture data.
The scan convert engine 398 scan converts polygons, which in this case are triangles. The scan convert block 394 includes the interpolators for walking edges and evaluating colors, depths, etc. The pixel address along with color and depth, and anti-aliasing coverage information is passed to the pixel engine for processing.
The scan convert engine 398 passes texture addresses to the texture filter engine 400, which calculates the texture data. The texture filter engine 400 calculates pixel color and alpha data for polygons that are being rendered. The illustrated texture filter engine computes a filter kernel based on the Z-slope and orientation of the triangle being rendered, and on the center of the texture request (the S and T coordinates of a point mapped into the texture). Filtering is performed in two passes in a pipelined fashion so that a new pixel is generated every cycle. The filter kernel can be an anisotropic filter or an isotropic filter. Where anisotropy is not required, the filter kernel can use negative lobes allowing much sharper textures than is possible with tri-linear interpolation. The texture filter engine 400 also handles Z-comparison operations for computing effects on shadows.
The texture cache 402 stores blocks of decompressed image data. In one implementation, the texture cache 402 stores texture data for sixteen 8.times.8 pixel blocks. The data is organized so that 16 texture elements can be accessed every clock cycle.
The decompression engine 404 decompresses texture data and transfers it to the texture cache 402. In this embodiment, the decompression engine includes two decompressors, one which implements a discrete cosine transformation (DCT) based algorithm for continuous tone images such as textures, and the other which implements a lossless algorithm for desktop pixel data. The DCT based algorithm is implemented by two parallel decompression blocks, each of which can generate eight pixel elements (i.e. two pixels) per clock cycle.
The compressed cache 416 can be used to buffer compressed data before the decompression engine 404 decompresses and transfers it to the texture cache 402.
The scan convert engine 398 transfers pixel data to the pixel engine 406. The pixel engine 406 performs pixel level calculations including blending, and depth buffering. The pixel engine also handles Z-comparison operations required for shadows. To achieve optimal performance, the pixel engine should preferably operate at one pixel per clock cycle.
The pixel engine 406 controls transfers of pixel data to a rasterization buffer. The rasterization buffer includes pixel buffers 408, and fragment buffers 410 in the illustrated embodiment. The pixel buffers 408 include two buffers to support double buffering. In this implementation of the pixel buffers, each pixel entry stores eight bits per color component (R G B), eight bits for the alpha component, 24 bits for the Z-buffer, 8 bits for the stencil buffer, and a nine bit pointer into the fragment buffer. This is a total of 73 bits per pixel. One pixel buffer is used by the pixel engine 406 while the other is used by the anti-aliasing engine 412. The buffers are then swapped.
The fragment buffers 410 store fragments for partially covered pixels called pixel fragments, which result from pixels of polygons whose edges cross a given pixel, or are translucent. The fragment buffer is single buffered in the implementation shown in FIG. 9A. A free list of fragments is maintained, such that as fragments are resolved, they are added to the free list, and as fragments are generated, they use entries from the free list. Alternatively, the fragment buffer could be double buffered, so that one fragment buffer could be resolved by the anti-aliasing engine while the other was filled by the pixel engine in parallel.
In one embodiment, a fragment record includes the same data as in the pixel buffer entries plus a 4.times.4 mask. The nine bit pointer is used to form a linked list of entries, with a reserved value indicating the end of the list. In this embodiment, the fragment buffers 410 includes a total of 512 entries, but the size can vary.
The anti-aliasing engine 412 calculates the color and alpha component for pixels which are affected by more than one polygon, which occurs when polygons only partially cover the pixel area (i.e. the polygon edges cross the pixel) or when polygons have translucency. The anti-aliasing engine 412 transfers resolved pixel data to the compression engine 414. In this embodiment, the compression engine 414 includes two compressors, one DCT based for continuous tone images, and one lossless for desktop pixel data. The DCT based algorithm is implemented using a compressor capable of compressing eight pixel elements per clock cycle. The compression engine 414 compresses the resulting rendered gsprites and sends the compressed data to the command memory and control 380 for storage in shared memory 216 (FIG. 4). The tiler also has a compressed cache 416 for caching compressed data.
FIGS. 10 and 11 illustrate two alternative implementations for accessing image data from memory during the pixel generation process. There are a number of instances when image data has to be accessed from memory during pixel generation. These include for example, accessing a texture map during a texture mapping operation, accessing a shadow map during a shadowing operation, and accessing color and/or alpha data during multi-pass blending operations. For simplicity, we refer to the image data in memory as "textures" or "texture data". However, it should be understood that the methods and systems described here can also be applied to other types of image data accessed from memory during pixel generation.
The implementations illustrated in FIGS. 10 and 11 provide alternative approaches to efficiently load and utilize a texture cache on the tiler. A significant advantage of these approaches is that texture data can be stored in memories with high latency and even in a compressed format without unduly hampering performance. As a result, less specialized and lower cost memory can be used to implement high performance rendering hardware.
Texture data from the memory is accessed and cached in units called "blocks" which are typically a small rectangular region appropriate for efficient fetching and catching. A typical block size is about 8.times.8 samples in size. For instance, for texture maps, a typical block is 8.times.8 texels.
FIG. 10 is a functional block diagram illustrating one embodiment for accessing these blocks of texture data. This embodiment solves the latency problem by buffering pixel data from the rasterizer 417, including texture data requests, in a texture reference data queue 418. The queue includes enough entries to absorb the latency which would otherwise be incurred in accessing (and possibly decompressing) a texture block so that the rendering process can run at full speed. For example, if it takes 100 cycles to fetch a texture block, and the tiler is capable of producing one pixel per clock cycle, then the texture reference data queue includes at least 100 entries.
Data flow in the system illustrated in FIG. 10 proceeds as follows. First, geometric primitives are set-up for rasterization as shown in block 416. Set-up processing includes, for example, reading vertices for a geometric primitive such as a triangle, and calculating the differentials for color, depth, and edges across the surface of the triangle. The parameters resulting from these computations are then fed to the rasterizer 417.
The rasterizer 417 reads the equation parameter data for each primitive and generates pixel data. The rasterizer generates pixel data, including texture coordinates and filter data, and buffers this data in the texture reference data queue 418. The texture fetch block 420 reads texture reference data stored in the queue 418 and fetches the appropriate texture blocks from memory 419.
The pixel data stored in the texture reference data queue 418 in this implementation includes: an address of destination for the pixel (X, Y) being computed; depth data (Z); a coverage mask; color and translucency data; the coordinates of the center for the texture request (S, T); and texture filter data. The depth and coverage data is only needed in the texture reference data queue if high-quality anti-aliasing of pixels is desired. Alternatively, hidden surface removal and antialiasing can be performed in the rasterizer 417. If hidden surface removal and anti-aliasing are performed in the rasterizer, depth data and coverage data does not need to be stored in the data queue 418. The texture filter data may include a level of detail parameter for MIP-mapping, for example, or may include anisotropic filter data for higher quality texture filtering.
The texture block fetch 420 reads the texture reference data buffered in the data queue and retrieves the corresponding texture data from memory 419. In the case of texture map accesses, the texture block fetch unit converts the (S, T) center of the texture request and the texture filter data into the addresses of the blocks required to satisfy the texture filtering operation. The blocks identified in this process are then fetched into the cache, replacing other blocks as needed. Image data blocks can be fetched using a least recently used (LRU) or other suitable cache replacement algorithm. To reduce memory accesses, the texture block fetch unit keeps track of the texture blocks already stored in the texture cache 421 and avoids requesting the same block more than once. This capability significantly reduces the memory bandwidth required to perform high quality texture filtering because the latency in retrieving a texture block is incurred only once in computing an image.
The texture block fetch unit includes a hold-off mechanism to prevent from overwriting texture blocks still needed in the texture filter unit in the tiler. One way to implement such a hold-off mechanism is to associate a reference count with each texture block to keep track of whether the texture filter has used a particular texture block. This reference count is incremented on receipt of a texture request to a block by the texture fetch unit, and decremented in response to its use by the texture filter unit. The texture block fetch unit then only replaces blocks that have a corresponding reference count of zero.
An alternative way to implement the hold-off mechanism is to allocate a buffer for temporary storage of texture blocks output by the texture fetch unit. In this approach, the image block is first written to temporary storage buffer. After the texture fetch unit has completed writing the image block to the temporary storage buffer, it can then be transferred to the texture cache. Image blocks are swapped to the texture cache when first needed by the texture filter unit 422.
In the case of texture mapping operations, the texture filter block 422 reads texture samples from the texture cache 421 and the pixel data stored in the texture reference data queue 418, and computes pixel color and possibly alpha values from the texture sample data.
In addition to texture mapping operations, this approach can also be applied to shadowing and multi-pass blending operations as well. For instance, texture reference data queue can be used to retrieve a shadow depth map residing in memory. Alternatively, the texture reference data queue can be used to retrieve color and/or alpha data used in multi-pass lighting and shading operations. More detail regarding texture mapping, shadowing, and multi-pass operations is provided below.
There are a number of advantages to buffering pixel data in the manner described above. One significant advantage is that the image data can be stored in less specialized memory (with higher access time), which reduces the cost of the overall system. In addition, image data including textures can be stored in compressed format and can still be accessed at fast enough rates to perform sophisticated pixel operation such as texture filtering. As a result, the system is able to achieve improved performance at a lower cost relative to known methods for accessing texture data.
Another advantage to this approach is that the texture reference data queue is able to predict accurately which image blocks need to be accessed from memory. As a result, the system incurs latency for memory accesses no more than necessary. Once the image data blocks are in the texture cache, the texture filter unit can run at the full speed of the rasterizer, as long as there is sufficient memory bandwidth and texture fetch throughput to write the requested image blocks to the texture cache.
Queuing texture references with the texture request center and filtering the data allows the queue to be much smaller than if texels with their corresponding texture filter weights were queued.
FIG. 11 is a functional block diagram illustrating an alternative embodiment for accessing image data from memory. In this approach, geometric primitives are queued and then processed in a pre-rasterizer to hide the latency of the texture block fetch during the pixel generation process. An example will help illustrate the concept. If an average primitive takes 25 cycles to rasterize, and it requires 100 clock cycles to fetch a texture block from memory, the primitive queue should be at least four primitives long. A simplified version of the post-rasterizer, the pre-rasterizer includes circuitry to determine the image data blocks that need to be accessed from memory. Once the texture data is fetched, the post-rasterizer can generate 5 pixel data using texture data without being exposed to the delay involved in fetching blocks from memory.
The data flow through this implementation occurs as follows. As in the implementation described above, geometric primitives are processed in a set-up block 425 for rasterization. In this particular implementation, however, the set-up block 425 includes a larger primitive queue to buffer more primitives. The pre-rasterizer 426 quickly converts the primitives into a list of texture blocks needed to satisfy the texture filtering needs for all of the pixels covered by the primitive in the order that the blocks will be needed by the post-rasterizer 427. The pre-rasterizer is a simplified version of the post-rasterizer 427, or the rasterizer 417 in the alternative implementation. In this approach, the pre-rasterizer only needs to compute texture data addresses and determine texture requests.
The pre-rasterizer also keeps a model of the texture block cache and performs the cache replacement algorithm, such as least recently used (LRU) to keep from exceeding the size of the texture block cache. As part of the cache replacement algorithm, the pre-rasterizer compresses repetitive requests to a single texture block to only one request to the texture block fetch unit 429.
The texture block fetch queue 428 includes entries for storing texture block requests. The texture block fetch unit 429 reads texture requests from the texture block fetch queue and retrieves the appropriate blocks from memory 430.
The post-rasterizer rasterizes primitives queued in the set-up block 425 to generate pixel data for a pixel location. If image data needs to be accessed from memory during the pixel generation process, the post-rasterizer rasterizes the primitives as quickly as the necessary texture blocks can be transferred to the texture block cache 431. When the post-rasterizer completes rasterizing a primitive queued in the set-up block, the primitive is removed and replaced with another primitive from the input data stream. The set-up block is responsible for keeping the queue filled with primitives so that the pre-rasterizer and post-rasterizer are not stalled in the pixel generation process.
Like the alternative embodiment described above, the texture block fetch should preferably include a hold-off mechanism to prevent it from overriding the texture blocks that are still needed by the post-rasterizer. The two hold-off mechanisms described above can also be used in this implementation. Specifically, a reference count can be used to keep track of when an image block has been requested and then used. In this case, the reference account would be incremented on receipt of a texture request for a block by the pre-rasterizer, and decremented upon use by the post-rasterizer. The texture block fetch unit then only replaces blocks in the texture cache when their corresponding reference count is zero.
Alternatively, a buffer can be allocated for temporary storage of texture blocks output by the texture fetch block. When the texture fetch block has completed writing a block to this temporary buffer, it can then be transferred to the texture block cache 431 when requested by the post-rasterizer 427. When the post-rasterizer 427 first request data in a texture block in the temporary buffer, the block is then transferred to the texture block cache 431.
There are a number of advantages to this approach. First, texture data can be stored in less specialized memory and can still be accessed at rates required to support sophisticated texture filtering. An important related advantage is that texture data can be stored in a compressed format and then decompressed for use in the pixel generation process.
Another advantage of this approach is that requests to memory can be predicted so that the latency for memory access is incurred only once for each texture block to render a scene. Once the initial texture blocks are in the texture cache, the post-rasterizer can run at full speed, as long as there is memory bandwidth and texture fetch throughput to keep the cache current.
FIG. 9B illustrates a more detailed implementation of the system illustrated in FIG. 10. The set-up block 381 in FIG. 9B corresponds to the set-up block 416 in FIG. 10. Unlike the set-up block 382 of FIG. 9A, the set-up block 381 in this alternative implementation does not generate texture read requests. Instead, the scan convert block 395 generates pixel data, including texture reference data, which is buffered in the texture reference data queue 399.
The scan convert block 395 of FIG. 9B is a specific implementation of the rasterizer 417 in FIG. 10. It computes a Z-value, a coverage mask, color and translucency data, and the center of the texture request in texture coordinates. For some texture mapping operations, it also computes level detail data or anisotropic filter data. The texture filter engine 401 reads the texture request and possibly texture filter data buffered in the texture reference data queue 399 and accesses the appropriate texture samples in the texture cache. From this texture data, the texture filter engine computes the contribution of the texture to the pixel color and alpha values. The texture filter engine combines the color and alpha in the texture reference data queue 399 with the contribution from the texture to generate pixel values sent to the pixel engine 406.
The texture cache control 391, texture read queue 393, command and memory control 380 are specific implementations of the texture block fetch 420 in FIG. 10. In addition, for compressed texture blocks, the compressed cache 416 and the decompression engine 404 are also part of the texture block fetch 420.
FIG. 9C illustrates a more detailed implementation of the system illustrated in FIG. 11. In this implementation, the functionality described in connection with blocks 425 and 426 of FIG. 11 is implemented within the set-up block 383. Specifically, the set-up block 383 includes the pre-rasterizer 426. The set-up block 383 also includes additional vertex control registers 387 to buffer additional primitives so that the pre-rasterizer can quickly convert the primitives to initiate texture data requests. The set-up engine and pre-rasterizer 383 sends requests for texture blocks to the texture cache control 391 shown in FIG. 9C.
The texture cache control 391 ensures that the required texture blocks will be in the texture cache 402 when needed. The texture read queue buffers read requests for texture data blocks to the shared memory system. The command and memory control 380 arbitrates access to the shared memory system, and it includes a buffer for buffering data from memory. The texture cache control 391, texture read queue 393, and the command and memory control 380 are specific implementations of the texture block fetch 429 in FIG. 11. For compressed texture blocks, the compressed cache 416 and the decompression engine 404 are also part of the texture block fetch 429. The texture cache control 391 manages the flow of texture blocks from the compressed cache 416, through the decompression engine 404, into the texture cache 402.
The scan convert block 397 and the texture filter engine 403 are a specific implementation of the post-rasterizer 427 in FIG. 11. The scanconvert block 397 and the texture filter engine 403 operate similarly to their counterparts illustrated in FIG. 9A and described above.
Texture Cache Control
Above, we described two approaches for rasterizing in environments with high latency for texture fetch operations. We now describe aspects of the texture cache control in more detail.
The texture cache control scheme allows a rasterizer to function at full speed during texture mapping in spite of a high latency for texture map fetch operations. In the tiler, this latency is the result of the time required to read uncompressed texture data from shared memory (e.g., RAMBUS) plus the time required to decompress blocks of the texture map. The scheme also applies to the gsprite engine, which fetches gsprite blocks from shared memory, possibly decompresses them, and converts pixel data in gsprite space to view space (or more specifically, to screen coordinates).
The basic premise of the texture cache control scheme is to produce two identical streams of texel (or gsprite pixel) requests which are offset in time. The first (earlier) stream is a pre-fetch request for which no texture data is returned, while the second (later) stream is an actual request which does return texel data. The time difference between these two streams is used to hide the latency of reading and decompressing texture data.
Two approaches for generating these time-separated requests described above are: (1) duplicate rasterizers which both read from a single primitive FIFO (FIG. 11 and 9C); and (2) a single rasterizer followed by a pixel FIFO (FIG. 10 and 9B).
In approach (1), the first rasterizer peeks at primitives from positions at or near the input side of the primitive FIFO and rasterizes the primitives, making texture requests but not receiving any texels back and not producing any pixels. The second rasterizer removes primitives from the FIFO output and makes the identical requests at a later time, receives the texels from the texture cache controller, and produces the pixels. The depth of the primitive queue combined with the number of pixels per primitive determines the potential time difference between the two request streams.
In approach (2), the single rasterizer processes primitives and makes texture requests and outputs partially complete pixel data into a pixel FIFO. This partial pixel data includes all data that is necessary to finish computing the pixel once the texture requests are honored. At the output side of the pixel FIFO, the partial pixel is completed, which produces the identical stream of texture requests, receives the texels, and produces completed pixels. The depth of the pixel queue determines the potential time difference between the two request streams.
The Texture Cache Control
The texture cache control has two conceptual caches: the virtual cache, and the physical cache. The virtual cache is associated with the first (pre-fetch) request stream, and has no data directly accompanying the cache entries (requests to this cache do not return any data). The physical cache is associated with the second (actual) request stream, and has real texture data accompanying each cache entry (and thus returns data to the requester). These caches have the same number of entries.
The virtual cache controls and tracks the future contents of the physical cache, thus at any position in its request stream it has a set of cache key and entry associations which the physical cache will have at the same relative position in its request stream (at a future time).
Upon receiving a request (a new `key`), the virtual cache performs the comparison against its current set of keys. If the requested key is not in the virtual cache, then a cache replacement operation is performed. The virtual cache replacement includes 1) selecting an entry for replacement (via LRU or some other algorithm), 2) replacing the key for that entry, and 3) invoking the (memory and) decompression subsystem to begin the process of fetching and decompressing the data associated with that key. The particular implementations shown in FIGS. 9B and 9C, the decompression subsystem includes the command and memory control 380, compressed cache 416, and decompression engine 404.
The output of the decompression subsystem is a block of texture data which is then placed into an entry in the physical cache (the texture cache 402, for example). In the tiler shown in FIGS. 9B and C, processing performed by the decompression subsystem is performed in a multi-entry pipeline in which serial order is maintained.
Note that if the requested key was already in the virtual cache, then no action is required because the associated data will be in the physical cache at the time it is requested from the second request stream.
Requests to the physical cache result in a similar key comparison to see if the requested data is already in the cache. If a matching key is found, then the associated data is returned. If a match is not found, then the next data output by the decompression subsystem is guaranteed to be the desired data. Note that the physical cache does not perform any replacement entry selection processing--the entry in the physical cache replaced by this new data is dictated by the virtual cache via a cache entry `target` index computed by the virtual cache controller and passed through the decompression subsystem with the requested data.
Correct functioning of the scheme requires that flow control be applied to the interface between the decompression subsystem and the physical cache. If decompressed data is allowed to overwrite its targeted entry in the physical cache immediately upon being available, it is possible that all of the references to the previous contents of that cache entry may not have been completed. (Note that the physical cache controller also may have to wait for data to be output by the decompression subsystem.)
This flow control is accomplished by waiting until the new entry is requested before overwriting the previous entry's contents. Placing new data into the texture cache is thus always deferred until the last moment until it is needed.
Since this replacement is deferred until it is needed, any time required to place the data into the physical cache can introduce latency into the process driving the second request stream. Two schemes for alleviating this latency are as follows.
The first scheme is to double buffer data in the physical cache. This allows the decompression subsystem to immediately write each entry's data into its side of the double buffer, and the physical cache controller can do a (presumably fast) buffer swap to map the data into its side of the cache. The decompression subsystem only has to wait if the entry to be filled is already full and has not been swapped yet. Note that the cache replacement algorithm used by the virtual cache controller will tend to not repeatedly overwrite the same entry, thus `spreading out` the writes to the cache entries.
The second scheme is for the physical cache to have one or more `extra` entries in addition to the number of `keyed` entries. The number of keyed entries is the number for which cache keys exist, and matches the number of entries in the virtual cache. The number of extra entries represents the number of entries which are unmapped (i.e. not currently keyed). The sum of these is the total number of data entries in the physical cache.
In the second scheme, all cache entries can transition between unmapped to mapped (associated with a key). The set of unmapped entries forms a FIFO of entries into which the decompression subsystem writes completed blocks of data. A separate FIFO structure is maintained for the target indices associated with these unmapped entries. When a request to the physical cache is made for which a matching key is not present, the first entry in the queue of unmapped of entries is mapped in to the targeted index and associated with that key. The replaced entry is unmapped and placed (empty) at the end of the unmapped queue.
Cache Key Generation
The basic premise of the scheme is that two identical streams of requests are generated. It is not a requirement, however, that the specific keys which are associated with these requests be identical.
The cache keys which form the first (early) stream of requests are used to control the reading and subsequent decompression of texture data. These keys must have some direct relevance to the requested data (such as a memory address).
The cache keys which form the second (later) stream of requests do not need to precisely match the content of the first stream--it is only a requirement that there be a unique one-to-one mapping between the two. This is due to the fact that the keys for the second stream are used only for matching existing cache entries, not for any data fetching operation. The critical fact here is that the association between the physical cache's key and a cache entry is made when the new data is mapped in to the physical cache, and the index of the associated entry is computed by the virtual cache and passed through the decompression subsystem.
This fact can be exploited to simplify the controls for the process which is generating the keys for the second request stream, since the keys for the stream need only be unique and not precisely `correct`.
FIG. 12A is a block diagram illustrating the gsprite engine 436 on the image processing board 174. The gsprite engine 436 is responsible for generating the graphics output from a collection of gsprites. It interfaces with the tiler memory interface unit to access the gsprite data structures in shared memory. Gsprites are transformed (rotated, scaled, etc.) by the gsprite engine and passed to the compositing buffer where they are composited with pixels covered by other gsprites.
Interface control 438 is used to interface the gsprite engine with the shared memory system via the tiler. This block includes a FIFO to buffer accesses from the memory before they are distributed through the gsprite engine.
The display control 440 processor is used to control the video display updates. It includes a video timing generator which controls video display refresh, and generates the timing signals necessary to control gsprite accesses. This block also traverses the gsprite display data structures to determine which gsprites need to be read for any given 32-scanline band.
The gsprite header 442 registers store gsprite header data which is used by the image processor address generator 454 and gsprite filter engine 456 to determine the transformations on each gsprite. It is also used by the gsprite header decoder 444 to determine the blocks (in this case, the 8.times.8 compression blocks) required to render the gsprite in each band.
The gsprite header decoder 444 determines which blocks from each gsprite are visible in the 32-scanline band and generates block read requests which are transferred to the gsprite read queue 446. This block also clips the gsprite to the current band using the gsprite edge equation parameters. This process is described in more detail below.
The gsprite read queue 446 buffers read requests for gsprite blocks. This queue stores requests for sixteen blocks, in this embodiment.
The gsprite data address generator determines the address in memory of the requested gsprite blocks and sends gsprite read requests to the interface control block. The gsprite data address generator 448 includes a memory management unit.
Compressed data retrieved from shared memory 216 (FIG. 4A) can be temporarily stored in the compressed cache 458.
The decompression engine 450 includes two decompressors, one which implements a DCT based algorithm for continuous tone images such as 3-D gsprites and images, and the other which implements a lossless algorithm for desktop pixel data. The DCT based algorithm is implemented by two parallel decompression blocks, each of which can generate eight pixel elements (i.e. 2 pixels) per clock cycle.
The gsprite cache 452 stores decompressed, gsprite data (R G B.varies.) for sixteen 8.times.8 blocks. The data is organized so that 16 gsprite pixels can be accessed every clock cycle.
The image processor address generator 454 is used to scan across each gsprite based on the specified affine transformation and calculate the filter parameters for each pixel. Gsprite cache addresses are generated to access gsprite data in the gsprite cache 452 and feed it to the gsprite filter engine 456. The image processor address generator 454 also controls the compositing buffer.
The gsprite filter engine 456 calculates the pixel color and alpha for pixel locations based on the filter parameters. This data is transferred to the compositing buffers for compositing. This block 456 computes a 4 or 16 pixel filter kernel based on the gsprite s and t coordinates at a pixel location. The filter may, for example, either be bilinear or a more sophisticated sum-of-cosines function. The 16 pixel filter kernel can have negative lobes allowing much sharper filtering than is possible with bi-linear interpolation. The gsprite filter engine 456 generates four new pixels to be composited every clock cycle. These pixels are aligned in a two by two pattern.
The gsprite engine 436 interfaces to the tiler 200 and the compositing buffer 210. Control signals control video timing and data transfer to the DAC 212.
FIG. 12B is a block diagram of an alternative implementation of the gsprite engine 437. This particular implementation includes both a pre-rasterizer 449 and rasterizer 454 so that the gsprite engine can convert gsprite pixel data from gsprite space to screen space without incurring the latency in retrieving and decompressing blocks of gsprite pixel data. The dual rasterizer approach used in this implementation is described above in connection with FIG. 11 and 9C.
The operation of the blocks in the gsprite engine 437 is generally the same as described above for FIG. 12A except that this implementation uses the dual rasterizer method for fetching blocks of texture data. In this implementation (FIG. 12B), the gsprite header decoder 444 reads the gsprite header register 442, clips the gsprite to the current display band, and places the gsprite in the gsprite queue 447 for rasterization. The data address generator or "pre-rasterizer" 449 scans each gsprite based on the specified affine transform in the gsprite header and generates read requests to the gsprite cache control 451. Using a method described above in connection with the texture cache control, the sprite cache control 451 ensures that the required gsprite data blocks are in the gsprite engine 437 and specifically in the gsprite cache 452 when the image processor block 455 needs them. It manages the flow of gsprite data blocks from the compressed cache 458, through the decompression engine 450, and into the gsprite cache 452. The read queue 453 buffers requests for gsprite data blocks to the shared memory system, and the interface control 438 reads the requests in the read queue 453, controls accesses to shared memory, and places blocks of gsprite data in the compressed cache 458.
The decompression subsystem in the gsprite engine includes the compressed cache 458 and decompression engine 450. The cache control 451 controls the flow of gsprite blocks through this decompression subsystem as described above in connection with the texture cache control.
The image processor address generator (rasterizer) 454 scans each gsprite based on the specified affine transform in the gsprite header and calculates the filter parameters for each pixel. It also generates gsprite cache addresses of gsprite data, which it sends to a cache address map in the gsprite cache for use by the gsprite filter engine 456. In one specific implementation of the cache, the cache address map selects which 14 pixel blocks are active and which two blocks are filled from the decompression engine.
The gsprite filter engine 456 maps color and alpha data at pixel locations in gsprite space to screen space. In this implementation, it applies either a 2.times.2 or 4 by 4 filter kernel to compute pixel values (color or both color and alpha) at pixel locations in screen space. The compositing buffer control 457 passes pixel values, in this case four pixels per clock cycle, to the compositing buffer. The compositing buffer control 457 monitors the ready line from the compositing buffer to ensure that the gsprite engine 437 does not overrun the compositing buffer. The rasterizer 454 controls the compositing buffer control 457.
FIG. 13 is a block diagram illustrating the compositing buffer 480 on the image processing board 174. The compositing buffer 480 is a specialized memory device that is used to composite gsprite data from the gsprite engine and generate digital video data to transfer to the DAC 212. The compositing buffer operates on 32 scanlines at a time--compositing gsprites for one 32 scanline band while the previous 32 scanlines are displayed.
The compositing logic 482 is responsible for calculating the pixel values as they are written into the scanline buffer. This is accomplished by performing a blending operation between the pixel value that is currently stored in the scanline buffer and the one that is being written to the compositing buffer. This operation is described in more detail below. In one implementation, the compositing logic performs four parallel pixel operations per clock cycle.
The memory control 484 is used to control the address and cycling of the memory banks. Address information is passed in a row column format as with normal DRAMs.
The alpha buffers 486 include an eight bit value for each of 1344.times.32 pixels. The memory is organized such that four contiguous pixels can be read and written each clock cycle. The alpha buffer also has a fast clear mechanism to quickly clear the buffer between 32-scanline band switching.
Two independent scanline buffers 488 are provided. The scanline buffers include three eight bit color values for each of 1344.times.32 pixels. The memory is organized such that four contiguous pixels can be read and written each clock cycle. One buffer is used to transfer the pixel data for a band to the DAC while the other is used to composite the pixels for the next band. Once the band has been completed, their functions swap.
A multiplexer is used to select data from one of the two scanline buffers 488 and sends the pixel display data to the DAC. The multiplexer switches between buffers every 32 scanlines.
The compositing buffer 480 interfaces to the gsprite engine 204, and transfers image data to the DAC 212.
FIG. 14 is a block diagram illustrating the DAC 514 on the image processing board 174. The DAC 514 implements the basic functions that are common to most RAMDACs on the market today. The DAC includes logic for reading and writing internal control registers, and for pipelining the video control signals. Additional functional blocks are described below.
The pixel data routing block 516 is used to control the routing of pixel data from the compositing buffers. In the normal operating mode, this data is passed at pixel rates to the Color LUTs 518 for each of the three channels. This block also allows the data to be read back to the DSP for diagnostic purposes.
The stereo image splitter 520 supports two separate video signals for stereoscopic display using a head mounted display system. In this mode, the two video channels (522, 524) are interleaved from the compositing buffer, and must be split out by the DAC 514. The stereo image splitter 520 performs this function on the DAC 514. In the normal single channel mode, the LUT data is passed directly to the Primary DACs.
Alternatively, the DAC 514 can be designed to generate a single video output. With a single video output, the DAC can generate a stereoscopic display using a line interleaved format, where one scanline for one eye is followed by the scanline for the other eye. The resulting video stream has a format such as 640.times.960, for example, which represents two 640.times.480 images.
The clock generator 526 is used to generate the video and audio clocks. These clocks are generated by two phase locked clock generators to eliminate synchronization drift. The clock generator can also be slaved to a control signal from the Media Channel, allowing the image processing board to sync to an external sync source.
Tiling
As outlined above, the image processor (FIG. 1) performs scan-conversion, hidden surface removal, antialiasing, translucency computation, texturing, and shading. In this section we describe scan conversion, hidden surface removal, antialiasing and translucency computation in detail.
FIG. 4B is a block diagram illustrating portions of the image processor 462 for producing rendered image data from geometric primitives. The image processor includes a rasterizer 464, a pixel engine 466, an anti-aliasing engine 468, and a rasterization buffer, which includes pixel buffers 470, and a fragment buffer 472 in this embodiment. The "rasterizer" refers to the part of the image processor that determines pixel values from the geometric primitives, i.e. polygons. The rasterizer 464 reads primitive data and produces pixel data associated with a pixel location. This pixel data includes color, alpha, and depth (distance from the viewpoint). When a pixel is not entirely covered by a polygon, the rasterizer generates pixel fragment data.
As it scan converts a polygon, the rasterizer passes pixel data to the pixel engine for processing. The pixel engine 468 reads the pixel data from the rasterizer and determines which pixel data to store in the pixel and fragment buffers. The pixel buffers 472 are two-dimensional arrays, where the elements in the arrays correspond to pixel locations and include memory for storing color, alpha and depth data. The fragment buffer 470 stores fragment data to represent partial coverage of a pixel.
The pixel engine 466 performs hidden surface removal using depth values generated by the rasterizer and also maintains pixel fragments and translucent pixels for antialiasing and translucency processing. For a given pixel location, the pixel engine retains the nearest fully covered opaque pixel, if any. In this context, "fully covered" means that the pixel is entirely covered by a polygon that is being scan converted in the rasterizer. The pixel engine also retains pixels with translucency (alpha less than 1) and pixel fragments in front of the nearest opaque pixel. The pixel engine stores the nearest opaque pixel for a pixel location in the pixel buffer, and stores in the fragment buffer any fragments or translucent pixels at this pixel location that are in front of the nearest opaque pixel.
After the pixel engine generates pixel data, the anti-aliasing engine 468 resolves the pixel data in the pixel and fragment buffers. The design of the image processor illustrated in FIG. 4B supports double buffering of pixel data and single buffering of fragment data. The pixel engine generates pixel data in one of the pixel buffers, and adds fragment information into the fragment buffer while the anti-aliasing engine resolves the pixel data from the other pixel buffer and fragment data from the fragment buffer. As each fragment is resolved, the fragment entry is added to the fragment free list for use by new pixel data.
Having provided an overview of the process of generating and resolving pixel data, we now describe an embodiment in more detail. Below we describe an embodiment with reference to the tiler, shown generally in FIG. 4 and illustrated in more detail in FIGS. 9A-9C. We provide more detail regarding the tiler, including the components pertaining to scan conversion and antialiasing, as well as the components referring to textures. We will describe components used in multi-pass rendering, shading, and textures now, and will elaborate on these concepts later in our description.
The components of FIG. 4B can implemented on the tiler. The tiler reads primitive data and rendering instructions from the shared memory system 216 (FIG. 4A), produces rendered image data, and stores compressed image data in shared memory. As described above, the basic 3-D graphics primitives in the system are triangles. Triangle rendering provides numerous simplifications in hardware used for graphics generation since the triangle is always planar and convex. However, alternatively n-sided polygons can also be used.
Above we explained the components of the tiler 200. Here we describe the data flow through the tiler in more detail.
Since the tiler receives inputs from the DSP, we begin with a recap of functions of the DSP 176 (FIG. 4). As described above, the DSP 176 can perform front end geometry and lighting calculations required for 3-D graphics. The DSP 176 calculates model and viewing transformations, clipping, lighting, etc. Rendering commands are stored in main memory buffers and DMAed (Direct Memory Accessed) to the image processing board over a PCI bus. The rendering commands are then buffered in the shared memory 216 (FIG. 4A) until needed by the DSP. The rendering commands are read by the tiler 200 (FIG. 4A) when it is ready to perform image processing operations.
As is shown in the flowchart in FIGS. 15A and 15B, the setup block processes primitive rendering instructions read from the shared memory. The vertex input processor parses the input stream (914) (FIG. 15A), and stores the information necessary for primitive triangle processing in the vertex control registers (916).
The two vertex control registers store six vertices, three for each triangle in each register. The two vertex control registers allow for double buffering of triangle information to assure that the setup engine always has triangle information to process.
The setup engine then calculates the linear equations (918) which determine the edge, color, and texture coordinate interpolation across the surface of the triangle. These linear equations are used to determine which texture blocks will be required to render the triangle. The edge equations are also passed to the scan convert block (920) and are stored in the primitive registers within the scan convert block until required by the scan convert engine. The primitive registers are capable of storing multiple sets of edge equations.
The setup engine also passes texture addresses to the texture read queue (922), which buffers requests for texture chunks. The texture address generator then determines the address in memory of the requested texture chunks (924) and sends the texture read requests to the command and memory control block (926) (FIG. 15B), which will fetch the texture data (928) used by the scan convert block.
Texture data is stored in the shared memory (216) (FIG. 4A) in a compressed image format which may be the same format as the image data. The compression format is performed on individual 8.times.8 pixel blocks. The 8.times.8 blocks are grouped together in 32.times.32 blocks for memory management purposes to reduce memory management overhead.
As texture blocks are needed, they are fetched into the tiler, decompressed by the decompression engine (930), and cached in an on-chip texture cache (932). A total of 32 8.times.8 pixel blocks can be cached, although each block stores only one color component. The texture data is cached in an R G B and Alpha format.
The scan convert engine then reads the edge equations from the primitive registers (934) to scan convert the triangle edge information. The scan convert engine includes interpolators for walking the edges of the triangles, interpolating colors, depths, translucency, etc.
The scan convert engine passes texture addresses to the texture filter engine (936). The texture filter engine calculates texture data for the polygons that are being rendered. The texture filter engine computes a filter kernel based on the Z-slope and orientation of the triangle, and on the s and t coordinates. The texture cache attached to the texture filter engine store texture data for sixteen 8.times.8 pixel blocks. The texture cache is also in communication with the decompression engine which will decompress texture data (which is stored in a compressed format) for use by the texture filter engine.
When the texture filtering is completed, the texture filter engine passes the information back to the scan convert engine (938), so it can be used by the scan convert engine for further processing. Along with texture processing, the scan convert engine scan converts the triangle edge data (940) and the individual pixel addresses along with color and depth information are passed to the pixel engine for processing (942).
The method illustrated in FIGS. 15A and 15B varies for the alternative methods described in connection with FIGS. 10 and 11. FIGS. 15C and 15D illustrate a method for accessing image data corresponding to FIG. 10 and 9B. Similarly, FIGS. 15E and 15F illustrate a method for accessing image data corresponding to FIG. 11 and 9C.
Referring first to FIGS. 15C and 15D, this implementation of the method begins in the set-up block 381 in FIG. 9B. The vertex input processor 384 processes the input data stream (947). Next, the vertex control registers 386 buffer triangle data from the input data stream (948). The set-up engine 388 then calculates the edge equations (949) and passes them to the scan convert block 395 (950).
The scan convert block 395 reads edge equations stored in the primitive registers (951) and scan converts triangle data (952). The scan convert engine 398 then writes pixel data including the pixel address, color and alpha data, and coverage data to an entry in the texture reference data queue 399 (953) (FIG. 15D). In the case of texture mapping operations, this entry also includes texture reference data, namely, the coordinates of the texture centerpoint. The entry may also include texture filter data such as level detail or anisotropic filter control data.
From the texture reference data, the texture cache control 391 determines which texture blocks to fetch and causes the appropriate texture block or blocks to be fetched from memory (954).
The texture address cache control 391 sends texture read requests to the command and memory control block 380 (955). The texture read queue 393 buffers read requests for texture blocks to the shared memory system. The memory control 380 fetches the texture data from shared memory, and if it is compressed, places the compressed block or blocks in the compressed cache 416 (956). The decompression engine 404 decompresses compressed image data and places it in the texture cache 402 (957, 958). As described above in connection with FIG. 10, the replacement of blocks in the texture cache proceeds according to a cache replacement algorithm.
To carry out texture mapping or other pixel operations requiring image data in the texture cache, the texture filter engine 401 reads texture addresses from the texture reference data queue 399 (959). The texture filter engine 401 accesses the image data in the texture cache 402, computes the contribution from texture, and combines this contribution with the color and possibly alpha data from the texture reference data queue 399.
The texture filter engine 401 passes pixel data to the pixel engine 406, which then performs hidden surface removal and controls storage of the pixel data to a rasterization buffer.
FIGS. 15E and 15F illustrate a method for accessing image data blocks from memory corresponding to the approach in FIG. 11. In this alternative implementation, the method begins by queuing primitives in the set-up block 383. The vertex input processor 384 parses the input data stream and queues triangle data in the vertex control registers 387 (961, 962). When image data blocks need to be accessed from memory, as in the case of a texture mapping operation, the pre-rasterizer 389 scan converts primitives queued in the vertex control registers 386 to generate read requests for texture data blocks in shared memory (963).
As the pre-rasterizer scans a primitive queued in the set-up block, it passes texture read requests to the texture cache control 391 (964). The texture cache control 391 determines the appropriate texture blocks (965) and transfers read requests to the command and memory control block 380 (989) (FIG. 15F) via the texture read queue 393. The memory control block fetches the requested texture data, and if it is compressed, stores it in the compressed cache 416 (990). The decompression engine decompresses texture blocks in the compressed cache 416 and writes the decompressed image data to the texture cache 402 (991, 992). The texture cache control manages the flow of texture blocks from the compressed cache 416, through the decompression engine 404, and into the texture cache 402
The scan convert block 397 reads the geometric primitives queued in the set-up block. The scan convert block 397 performs pixel generation operations as soon as requested texture data is available in the texture cache 402. In the process of performing these pixel operations, the scan convert engine 398 reads edge equations from the primitive registers (993) and passes texture addresses to the texture filter engine 403 (994). The texture filter engine accesses the appropriate image data stored in the texture cache 402 and then returns filtered data to the scan convert block 397 (995). The scan convert block 397 converts the triangle data and computes output pixel data from converted triangle data and the filtered data (996). It then passes this output pixel data to the pixel engine 406.
The pixel engine 406 performs pixel level calculations including hidden surface removal and blending operations. To perform hidden surface removal, the pixel engine 406 compares depth values for incoming pixels (fully covered pixels or pixel fragments) with pixels at corresponding locations in the pixel or fragment buffers. For shadowing operations, the pixel engine provides a Z-value to the texture filter engine 400 where it is compared with Z-values in a shadow Z map (stored in the texture cache). After performing the pixel level calculations, the pixel engine stores the appropriate data in the pixel or fragment buffers.
The tiler implements a high quality anti-aliasing algorithm for dealing with non-opaque pixels. The pixel buffer stores the pixel data for the front-most non-transparent pixel for pixel locations in a chunk. The fragment buffer stores pixel fragments for translucent pixels and for partially covered pixels closer to the viewpoint than the pixels in the pixel buffer for corresponding pixel locations. More than one fragment for a pixel location can be stored using a fragment list structure. In a process referred to as resolving, the anti-aliasing engine processes the fragment lists to compute color and alpha values for pixel locations.
To reduce the number of fragments that are generated, the pixel engine implements a method for merging pixel fragments which compares the fragment that is being generated with fragment(s) currently stored in the fragment buffer. If the new and previous fragment's attributes (color and depth) are similar to within a preset tolerance, the fragments are combined on the fly and no additional fragment is generated.
If a combined fragment is found to be fully covered (with a full coverage mask and opaque alpha), then the fragment is written into the color buffer and that fragment location is freed up to use for subsequent polygons within the current chunk.
Once all the polygons for the chunk are rendered, the pixel buffers are swapped. While the anti-aliasing engine resolves the pixel data in the fragment buffer and one of the pixel buffers, the pixel engine writes pixel data for the next chunk in the other pixel buffer and the remaining free locations in the fragment buffer. In general, pixel resolution comprises computing a single color (and possibly alpha) value for a pixel location based on the pixel data in the pixel and fragment buffers corresponding to the location. We provide additional detail addressing these issues below.
In the implementations of the tiler shown in FIGS. 9A-9C the pixel engine and anti-aliasing engine have access to a single fragment buffer and a pair of pixel buffers. The two 32.times.32 pixel buffers are provided for double buffering between the pixel engine and the anti-aliasing engine. The pixel buffer entry includes the following data: ##STR1## where R, G, B are the red, green, and blue color components respectively, .alpha. is the alpha component which represents the translucency of the pixel, and Z is the Z component which represents the depth of the pixel from the eye point. The x,y address is fixed and implicit in the pixel buffer addressing. Eight bits are used per color component (i.e. Red, Green, and Blue), eight bits are used for the a component, and twenty-six bits are used to store the Z-value, stencil value, and a priority value. Out of this 26 bits, up to 24 can be used as Z values, up to 3 can be used as stencil planes and up to three can be used as priority values. As described above with reference to FIG. 9, the buffer also includes a 9 bit fragment buffer pointer.
The priority value is fixed per primitive and is used to help resolve objects which are coplanar, such as roads on top of terrain, by using priority relationships which are used by the tiling engine to margin the incoming pixel Z-value, as compared to the stored Z-value, during the Z compare operation.
The fragment buffer is used to store information about pixel fragments for polygons whose edges cross a given pixel or for polygons with translucency. Each entry in the fragment buffer provides color, .alpha., Z and coverage data associated with the surface.
Multiple fragment buffer entries can be associated with a single pixel (via a linked list mechanism) for cases in which multiple polygons have partial coverage for the same pixel location. The fragment buffer is dual ported so that it can be operated on by the anti-aliasing engine and the pixel engine in parallel. In one possible implementation the fragment buffer is a one-dimensional array of fragment records and includes a total of 512 fragment record entries. The memory management of the fragment buffer is performed using a linked list structure. Each fragment buffer entry includes the following data: ##STR2## where R, G, B are the red, green, and blue color components respectively, .alpha. is the alpha value which represents the translucency of the pixel, and Z is the Z-value which represents the depth of the pixel from the eye point, M is a 4.times.4 pixel coverage bitmask for each pixel which is partially covered, P is a pointer to the next fragment buffer entry, and S is used to represent a fragment stencil. Eight bits are used per color component (i.e. Red, Green, and Blue), eight bits are used for the .alpha. component, twenty-six bits are used to store the Z-value plus stencil and priority, and nine bits are used for the fragment pointer P.
The pixel coverage mask is computed by determining a coverage mask value for each edge and bitwise ANDing them together. The computation of the coverage mask is a two step process. The first step is to determine how many of the subpixel bits in the coverage mask are to be turned on, and the second step is to determine which specific bits are to be enabled.
The first step uses the area of the pixel which is covered by the edge to determine how many of the coverage mask bits are to be switched on. This area is computed by a table lookup indexed by the edge slope and distance from the pixel center. The second step uses the edge slope to determine the order in which the sample bits are to be switched on. The set of bit orders is stored in a pre-computed tabled called the `Coverage Order` table. Each coverage order table entry consists of a specific ordering of the sample bits which is correct for a range of slope values. The edge slope is tested against the set of slope ranges, and the index associated with the range containing this slope value is used as the index into the coverage order table.
A method for computing the coverage mask is described in Schilling, A. "A New Simple and Efficient Anti-Aliasing with Subpixel Masks", Computer Graphics, Vol. 25, No. 4, Jul. 1991, pp. 133-141.
After the image processor generates fragment data for a pixel location, it then sorts and resolves this fragment data to compute color at that location. As described above, the image processor generates and maintain fragments for partially covered pixels. A pixel is partially covered by a polygon if one or more of the polygon's edges cross the pixel, or if the polygon has translucency. Maintaining fragment data to perform both antialiasing and translucency computations can require a significant amount of memory. As the number of rendered polygons increases, the amount of memory to store pixel data and fragments also increases.
In addition to the increased memory requirements, the amount of processing required to resolve fragments can be significant as well. In a Z-buffer approach, fragment data is depth sorted. In general, the primitive data is not sorted in depth order as it arrives for rendering. Since primitive data arrives in arbitrary depth order, the image processor has to sort the fragment data after generating it. The sorted data is then processed to determine the color and possibly the alpha at a pixel location. At each pixel location, several fragments can contribute to the color. If alpha is also computed the number of fragments and the complexity of processing increases as well.
For the reasons highlighted above, the memory and processing requirements to support advanced antialiasing and translucency can be substantial. There is a conflict between supporting sophisticated antialiasing and translucency computations, on one hand, and reducing memory requirements on the other. To reduce the cost of the system, the use of memory should be minimized, yet advanced antialiasing and translucency features usually require more memory. It is even more difficult to support these advanced features in a real time system while still minimizing memory requirements.
In one embodiment, our system renders primitives one chunk at a time, which reduces memory and allows for fragment resolution in a post processing step. While pixel data is generated for one chunk, pixel data of another chunk can be resolved. A number of benefits impacting fragment sorting and pixel resolution follow from the chunking concept. Memory requirements are significantly reduced because much of the data generated during the rasterizing process does not have to be retained after the image processor has resolved the pixels in a chunk. The image processor only needs to retain the resolved color portion after resolving a chunk.
Another advantage to rendering chunks is that the pixel and fragment memory can be implemented to reduce the overhead of memory accesses. Typical graphics systems use external memories to implement color, depth and fragment buffers. It is very difficult to organize this external memory to satisfy the rigorous bandwidth requirements of real time image processing. The pixel and fragment memory needed to support rendering of a chunk, such as a 32.times.32 pixel region, does not have to be located in external memory. Instead, it can be implemented on the same hardware that performs rasterizing and anti-aliasing functions. For example, in the implementation described above, the fragment and pixel buffers can be implemented on a single chip.
The use of on-chip memories simplifies the bandwidth problems associated with external memory. On-chip memories enable efficient use of multiple memory banks. For example, one bank can be used for the pixel buffer, and another bank can be used for fragment records.
Another advantage of on-chip memory is that it is less expensive and easier to implement multi-port memories. The performance of the pixel and fragment buffers can be enhanced through the use of multi-port memories, which allow simultaneous reads and/or writes to achieve one clock per pixel processing rate. Since the fragment buffer is much smaller when chunks are rendered separately, it can be implemented on chip. Both the smaller size of the memory and its presence on-chip make it feasible and cost effective to use multi-port memory. External multi-port memories on the other hand, are expensive due to the higher per bit cost and connections between chips.
Another important advantage related to chunking is that pixels for one portion of a frame can be generated while pixels for another portion are resolved. Thus, instead of generating pixels for an entire frame and then resolving those pixels, our approach can overlap the processes of generating and resolving pixels, reducing system transport delay.
In one embodiment of our system, the image processor resolves fragments in a post processing step. While the pixel engine generates pixel data for part of an image, the anti-aliasing engine resolves fragments for another part of an image. As noted above, the pixel data is double buffered: the pixel engine can access one buffer while the anti-aliasing engine accesses the other. After the pixel engine has generated pixels for a chunk, the tiler performs a buffer swap. The pixel engine then generates pixels for the next chunk, and the anti-aliasing engine resolves the pixels for the previous chunk.
Although it could also be double buffered, in the preferred embodiment, the fragment buffer is dual ported so that the pixel engine and anti-aliasing engine can access it simultaneously. The pixel engine can then write fragment data to the fragment buffer through one port while the anti-aliasing engine accesses fragment data through another port.
In this embodiment, the double buffered and dual-ported memory systems enable the image processor to overlap pixel data generation and pixel resolution. There are a number of alternative ways to implement a double buffering scheme as well.
The image processor sorts the fragment data in depth order before completing the resolve process. In general, the image processor can sort pixel data as it generates pixels, and after it has generated pixels for a portion of an image to be rendered. For instance, the pixel engine can perform an insertion sort as it writes fragment data to the fragment buffer. In addition, the pixel engine can sort fragment data after it has completed generating pixel data for all or part of an image. The pixel engine can also sort fragments in cases where it rejects incoming pixel data. Since the pixel engine does not have to write to the fragment buffer when the incoming pixel data is rejected, it can then perform a sort of fragments before the next incoming pixel arrives. We refer to this latter approach as "background sorting" of fragments.
An insertion sort refers to depth sorting an incoming fragment with other fragments in the fragment buffer. In a real time system, an insertion sort may not be preferred because it can potentially slow down the process of generating pixel data. Searching the fragment buffer to find the proper insertion point for an incoming fragment can cause undesirable overhead. Additionally, in hardware implementations, it requires additional hardware and complicates the design of the pixel engine.
As an alternative to an insertion sort, fragments can be sorted after the image processor has completed pixel generation for a portion of an image. Some systems render an entire frame of image data at once. In such systems, sorting fragments for every pixel location in the view space can require substantial processing time and add undesirable delay, especially for a real time system. The amount of time required to perform the sorting can vary depending on the number of fragments per pixel, and depending on the degree to which insertion sorting is already performed. The sorting operation, therefore, can hold up other pixel operations from occurring, thereby decreasing performance.
By rendering a portion of the view space at a time, the fragment sorting for one part of an image can occur while a next portion is being rasterized. In essence, the anti-aliasing engine can perform fragment sorting in a post-processing step. In one embodiment, the anti-aliasing engine sorts fragments for one chunk as fragments for the next chunk are being generated.
Even in cases where pixel generation and resolution are overlapped in this manner, it still may be advantageous to perform some sorting of fragments for part of an image as the pixel engine generates pixels for that part of the image. Background sorting of pixel fragments reduces the overhead of sorting fragments after the pixel engine completes generating pixels for a set of primitives.
In one embodiment, background sorting is performed concurrently with pixel operations being performed on the pixels to reduce, and in some cases eliminate the latency required for sorting of fragments. The design takes advantage of the fact that many of the pixels are not partially covered, and therefore do not make use of the fragment buffers The background sorting uses this spare bandwidth to perform a sort of a set of fragments in the fragment buffer.
One way to implement background sorting is to perform a bubble sort. The pixel engine performs a bubble sort of the fragments, by walking each chain of fragments (1210) and comparing the Z-values between two adjacent fragments. FIG. 16 is a flow diagram illustrating this approach.
If the current fragment has a larger Z (is further away) than the next fragment it points to in the fragment chain (1212), the two are swapped in order by readjusting their pointers (1214) accordingly. If the Z-values are already in sorted order, the sort logic continues marching down the chain comparing the previous next fragment with the new next fragment (1216). The sort logic continues walking the chain (1218) until it reaches the end of the current chain. If the sort logic has completely sorted the chain (1219), then the logic moves to the next chain. If not, the logic makes another pass through the chain. The sort logic continues passing through the chain until all of the fragments are in order for the current chain. The sort logic then moves to a next chain, if another exists and needs sorting (1220, 1222).
If a new fragment should come in that has the same address as one of the ones currently being sorted, the pipeline is stalled until the two fragments have been written. This is a rare case, and therefore is unlikely to hinder performance in a system employing background sorting.
An optimization can be employed whereby an extra n.times.1 bit RAM is used, where n is the total number of fragments allowed per chunked region. Whenever a new fragment is added to a fragment chain, the extra bit is set for the index to the first (foremost) fragment in the chain. This bit indicates a potentially unsorted fragment. When the fragment sort hardware gets ready to move to a new fragment chain, it clears the bit for that chain and proceeds to sort it. If in the meantime, a new fragment comes in that chain, then there is a chance that the fragment is unsorted again. Since the new fragment resets the new fragment bit, it means the sort operation will have to be performed again on the fragment chain. However, using this bit to tag the fragment chain that has received a new fragment eliminates the problem inherent in sorting a buffer that is being changed without the knowledge of the sort logic. The extra bit also prevents the background sort from spending time attempting to sort buffers that have already been sorted, are not the first in a chain, or which have not been allocated yet.
If there are less total fragments available than pixels, it maybe less costly in gates to use an individual RAM since there are fewer bits, and the sort is done based on the total number of fragments, not the total number of pixels.
A hardware implementation of the sort logic includes comparators for comparing Z information, data routing multiplexers for routing the pointers (used for swapping pointers in the sort process), a 1 bit.times.n RAM, and the logic for setting/clearing the bit in the RAM based on the offset. It also includes a state machine that controls the compare, routing, and fragment visited, as well as the sort process. This state machine is responsible for shutting down the incoming pipeline if the new fragment needs the same fragment as is currently being sorted. The fragment buffer and fragment index RAM should be multi-ported so the sort logic can read or write independent of pixel generation operations performed in the pixel engine. Alternatively, the fragment buffer is double buffered.
This implementation can be extended to alternative approaches using fewer ports on the RAM. This approach may require greater control for identifying when an incoming pixel is not a fragment so the same ports can be shared between incoming pixels and the sort logic.
After sorting, the image processor resolves the fragments for a pixel location to determine the color for that pixel location. If alpha is not considered, the image processor computes color accumulation based on the color and coverage data for fragments in a depth sorted list for a pixel location. If alpha is considered in addition to coverage data, the image processor computes color accumulation based on color, coverage, and alpha of the fragments in a depth sorted list for a pixel location.
In general, the image processor can resolve fragments for pixel locations corresponding to the entire view space or for only part of the view space at a time. In the embodiment described above, the image processor resolves pixel locations in a portion of the view space called a chunk. Fragment resolution occurs after fragments have been generated and sorted.
Fragment resolution is the process during which all of the fragments for a pixel are combined to compute a single color and alpha value. This single color and alpha are written into the color buffer (and then compressed and stored to a gsprite).
Computing the resolved color includes accumulating a correctly scaled color contribution from each layer while computing and maintaining coverage information with which to scale subsequent layers. This accumulation can be performed in front-to-back, or in back-to-front depth order. In a front-to-back approach, as opposed to back-to-front, spatial coverage data can be used to determine coverage for succeeding layers. Unlike coverage, alpha data applies equally to the entire pixel area.
For front to back, the equations for computing color and alpha for sorted fragment records are:
Alpha initialized to maximum value (inverse alpha). Color initialized to 0.
Anew=Aold-(Aold * Ain);
Cnew=Cold+(Cin * (Aold * Ain));
For back to front, the equations for computing color and alpha for sorted fragment records are:
Alpha and Color initialized to 0.
Anew=Ain+((1-Ain) * Aold);
Cnew=(Cin * Ain)+((1-Ain) * Cold);
For a hardware implementation, front to back is preferable because the resolve process is less hardware intensive.
A pseudocode example of accumulating fragments with depth, color, and coverage only (no alpha), is set-forth below:
Accumulating fragments with depth, color, coverage, and alpha requires that an alpha value be computed and maintained for each subsample. This is due to the combination of coverage masks and alpha values for each fragment. It is generally the case that the accumulated alpha at any layer during accumulation is a function of all of the alpha values of previous layers. With coverage masks, each subsample can potentially have a different set of `previous` alpha values, since a layer for which the coverage bit is clear does not contribute to that subsample.
One approach to resolving fragments with both alpha and coverage is to compute color for each subpixel in a layer separately, and then add the contribution from each subpixel location to determine the total color contribution. The alpha scale for each subpixel is determined from the alpha at that layer in addition to the alpha accumulated from other layers. This alpha scale is then multiplied by the color for the subpixel to determine the color contribution of the subpixel. The color for a layer is then determined by summing the color contributions from the subpixels.
One example of accumulating color and alpha for subpixels separately is:
An example using 4 sub-pixel locations will help illustrate fragment resolution. In this example, we consider three fragments, each having a coverage mask, alpha and color value. The initial state is illustrated in table below. In this example, we accumulate color and alpha using a front to back approach. The initial alpha is set to 1, meaning full transparency. The data for each layer is as follows: fragment 0, alpha=0.5, coverage mask (cm)=0011, and color=C.sub.0 ; fragment 1, alpha=0.3, cm=1000, color=C.sub.1 ; fragment 2, alpha=0.8, cm=0101, color=C.sub.2. The data for each fragment is provided in tables below.
With the alpha values initialized to one, the alpha coverage array is shown below.
To compute color, the color values for each subpixel location are multiplied by the new alpha and the alpha from the coverage array. The result for the subpixel locations is then divided by four (one divided by the number of subpixel locations). Finally, the contribution from all of the subpixel locations is summed to find the accumulated color.
Using the formula, Alpha'=Alpha * (Max.sub.-- alpha--new.sub.-- alpha), the image processor computes the new alpha separately for each pixel location and stores it in the alpha coverage array in the table below.
The contribution of fragment 1 is set forth in the table below.
The new alpha coverage array is as follows:
The contribution of fragment 2 is set forth in the table below.
The alpha coverage array for the fragments after fragment 2 is as follows:
This method requires 2 * NUM.sub.-- CVG.sub.-- BITS multiplies (2*16=48 in the 4.times.4 case) per fragment for the computation of alpha and the color contribution. Note that the (1/NUM.sub.-- CVG.sub.-- BITS) scaling can be done with a shift if the number of bits in the coverage mask is a 2**n size (which is typically the case).
FIG. 17 is a schematic diagram illustrating a hardware implementation of the approach described above for a pixel divided in 4.times.4 subpixel regions (1224). The resolve hardware includes a set of 16 identical processing and storage units called alpha and color accumulators (ACA) (1226), each ACA dedicated to one subpixel region of the pixel. During processing of the fragment list for each pixel location, the coverage masks of each fragment are used as a processing mask for the resolve hardware. The ACA performs a multiply for the alpha scale, color accumulation, and alpha accumulation. The (1/NUM.sub.-- CVG.sub.-- BITS) scaling is performed with a shift as set forth above. Once all fragments have been processed for a given pixel location, the output section combines the color and alpha values for all of the 16 subpixels in a hierarchical fashion (1228). The processors in the output combine the two incoming values and divide by 2. With hardware pipelining, the pixel resolve process uses only a single hardware clock per fragment entry.
An alternative technique reduces hardware requirements by treating subpixels having the same accumulated alpha similarly at each layer. This technique is based on the observation that the state in which subsamples have unique accumulated alpha values occurs gradually. Initially, all of the subsample alphas are set to zero (transparent). The first fragment accumulation can add at most one unique alpha value, resulting in one group of subsamples retaining the initial alpha value and the other group having the same new alpha value. The second fragment accumulation can result in no more than four unique alpha values. Overall, the number of unique subsample alpha values possible after `n` fragment accumulations is 2**n (or, more accurately, MIN(2**n,NUM.sub.-- CVG.sub.-- BITS)).
This alternate technique uses this characteristic to reduce the number of accumulations required by only performing the color scale and accumulation for each unique alpha value within the subsamples rather than for every subsample. With this technique, at most one accumulate needs to occur for the first fragment, two for the second fragment, four for the third fragment, and so on, up to the number of subsamples in the pixel (e.g., with a 4.times.4 subsample array the worst case is 16 accumulations per fragment).
The foundation of the technique is to maintain the set of unique alpha values and their associated coverage masks during fragment accumulation, the intent of which is to perform a minimum number of color accumulations.
The alpha and coverage masks are stored in NUM.sub.-- CVG.sub.-- BITS element arrays of which some subset of these entries is actually valid (or `in-use`) at any time. The `in-use` entries are those which hold the current set of unique alpha values. The in-use entries are identified by a NUM.sub.-- CVG.sub.-- BITS bit mask where a set bit indicates that the array element at that bit index is in-use. A convention is used in which the first set bit in the coverage mask of a {unique alpha, coverage mask} pair defines which array element that pair is stored in. Consider the following example of how the array is initialized and updated with the accumulation of three fragments (using 4 subsamples):
Initial state (X implies a `don't care` value):
The initial alpha coverage array is set forth below:
The in use mask is 0001, which specifies the location where the array mask is stored. The corresponding array mask is as follows:
After fragment 0, the alpha coverage mask appears as follows:
The in use mask is 0101, and the array mask is as follows:
For elements in the in use mask that are set, the array mask is ANDed with the coverage mask for the new fragment to determine whether there is a change in alpha value. If there is a new alpha, the new value for the array mask is computed by: array mask AND NOT coverage mask. If there is a new value for the array mask, it is stored in the appropriate location.
After fragment 1, the alpha coverage mask appears as follows.
The in-use mask is 1101, and the array mask is as follows:
After fragment 2, the alpha coverage mask appears as follows.
The in-use mask is 1111, and the array mask is as follows:
The number of unique alpha values at any time is equal to the number of set bits in the in-use mask. The complete solution includes two steps. The first step is performing the necessary color accumulations, where one accumulation is required per `in-use` entry in the coverage/alpha array. The second step is to update the coverage/alpha array with the new fragment's values.
A complete implementation of this technique (for 4.times.4 subsamples) is as follows.
The core arithmetic operation is the color accumulation, which requires a total of three multiplies per unique alpha value:
ColorAccum+=color*(alpha*AlphaOld*(nCoverageBits/NUM.sub.-- CVG.sub.-- BITS));
Note that the third multiply may be somewhat simplified by the number of subsamples. For 16 subsamples, the third multiply involves 0.4 fixed point value, thus this multiplier can be a 8.times.4 (where the other multipliers are likely to be 8.times.8). Also note that, for 2**n sized coverage masks, the division shown above is merely a shift.
This technique requires a worst case total of: ##EQU1## accumulations. The typical case can be much less than this because the worst case occurs only when a new fragment's coverage has both set and unset values in each `in-use` array element.
One useful optimization is to track coverage mask locations which have fully opaque alpha value. This is useful in the case in which fragments are being generated due to partial geometric coverage and not due to non-opaque transparency values. These fragments will normally have a fully opaque transparency value. Implementing this optimization is done by maintaining an additional mask value, the OpaqueAlphaMask. The OpaqueAlphaMask is set by O-Ring in coverage masks of fragments for which the alpha is fully opaque (this is done after accumulating the fragment's contribution). This mask is then used to disregard bits in the masks of subsequent fragments, since there can be no further color contribution to the corresponding subsamples.
Another possible optimization is to consolidate locations with identical alpha values, but this is significantly more expensive to implement, and the occurrence of identical alpha values which are not either 0 or MAX.sub.-- ALPHA is not likely.
The example and pseudocode given above use a front-to-back depth sorting. It is equally possible to perform the same computations in a back-to-front depth sorting. Also, the computations given above use color components which have not been pre-multiplied by the alpha component. The same technique applies to pre-multiplied color components, with slightly different arithmetic computations (and identical control flow).
FIG. 18 is a block diagram illustrating an implementation of the hardware optimized fragment resolve sub-system in the anti-aliasing engine. The input to the sub-system is a stream of depth sorted fragment records. As shown, a fragment record includes RGB color values, an alpha value A, and a coverage mask (Cov mask). This particular fragment resolve sub-system processes fragment records in front to back order and accumulates color values for the pixel location as it processes each fragment layer. This sub-system minimizes the hardware necessary to accumulate color values because it keeps track of unique pixel regions having a common alpha. This enables the fragment resolve sub-system to scale and accumulate color once for each unique pixel region rather than separately for each sub-pixel region.
As set forth in the pseudo code above, the fragment resolve system initializes an in-use mask 1236, an array of coverage masks 1230, and an array of accumulated alpha values 1230 before resolving a list of fragment records. The elements in the in-use mask 1236 represent pixel regions, each including one or more sub-pixel regions having a common accumulated alpha. The coverage masks give the sub-pixel locations covered by a pixel region. The array of accumulated alpha stores the unique accumulated alpha values for corresponding pixel regions having a common alpha. This particular coverage array 1236 stores the accumulated alpha values and coverage masks.
After initializing the in-use mask, coverage array mask and coverage array alpha, the sub-system begins processing a fragment record, starting with the fragment record closest to the view point. In one implementation of the anti-aliasing engine 412 on the tiler, the anti-aliasing engine sorts the fragment lists in a post-processing stage after the scan convert block 395 and texture filter engine 401 have completed rasterizing a chunk. The anti-aliasing engine reads each fragment in a fragment list, starting with the head, and as it does so places entries in sorted array of indices and depths. Each index in this array points to a fragment buffer location storing the RGB, alpha and coverage data for a pixel fragment in the list. As the anti-aliasing engine reads pixel fragments, it performs an insertion sort such that the array entries comprise a depth sorted array of indices to pixel fragments and corresponding depth values. Once the list is sorted, the fragment resolve subsystem retrieves depth sorted fragments by reading each entry in the sorted array in the order that these entries are stored in the array. This enables the fragment resolve system to retrieve the RGB color values, alpha and coverage masks for the pixel fragments in a list in a depth sorted order.
As it processes each fragment record in the list, the sub-system keeps track of the pixel regions having a common alpha. The sub-system determines whether each fragment record in the list overlaps each pixel region having a common alpha. If so, the sub-system computes the accumulated color for the portion of the current pixel region that overlaps with the current fragment. If there is an overlap with the current pixel region, the sub-system also determines the new pixel region or regions caused by this overlap and keeps track of them.
For a current fragment (1232), the sub-system loops through each element in the in-use mask. The coverage array loop control 1234 maintains the in-use mask (1236) and updates it as necessary as it processes each fragment record. As it loops through the entries in the in-use mask, the coverage array loop control communicates with and controls the operation of the new coverage control 1238. The new coverage control 1238 updates the coverage array mask and alpha 1230 as necessary when the current fragment overlaps the current pixel region.
The new coverage control 1238 reads the stored accumulated alpha (Aold) from the coverage array alpha associated with the current entry in the in-use mask and computes the alpha scale factor (A * Aold) used for scaling color and used to compute alpha for subsequent fragment layers, Anext (1-A*Aold). The new coverage control 1238 transfers the alpha scale factor (A*Aold) to the scale and accumulation control 1246 for use in scaling the color data of the current fragment. The new coverage control 1238 also computes the alpha for subsequent layers, Anext (1-A*Aold), and stores it in along with its corresponding coverage array mask in the coverage array 1230.
For each pixel region with a common accumulated alpha, the fragment resolve sub-system determines whether the current fragment overlaps the current pixel region by finding the intersection of the coverage masks of the fragment and pixel region.
If the current fragment overlaps the current pixel region, the sub-system 1) computes the accumulated color for the overlapped portion of the pixel region 2) updates the in-use element and corresponding coverage array mask and alpha (coverage array alpha) for this inuse element.
The scale and accumulation control 1246 computes the accumulated color for each unique pixel region covered by the current fragment. The scale and accumulation control includes a coverage scaler 1240, a color scaler 1242, and a color accumulator 1244. The coverage scaler 1240 computes a coverage scale factor (number of sub-pixel locations in current pixel region overlapped by current fragment/ total sub-pixel locations * A * Aold). The color scaler 1242 then reads the color values (RGB) for the current fragment (1232) and multiplies them by the coverage scale factor from the coverage scaler 1240. Finally, the color accumulator 1244 adds the scaled colors with the accumulated colors to compute updated accumulated color values.
When the current fragment overlaps the current pixel region, the coverage array loop control 1234 updates the in-use mask 1236 so that it includes an entry corresponding to the new pixel region. This may merely overwrite the existing in-use element or create a new one. The coverage array loop control also instructs the new coverage control 1238 to update the coverage array mask 1230 to the coverage of the new pixel region, and to set the accumulated alpha for this new pixel region. The new coverage control 1238 sets a new alpha coverage array entry corresponding to the new pixel region to Anext.
When the current fragment only covers a portion of a pixel region (rather than overlapping it entirely), then the new coverage control 1238 creates two new pixel regions: 1) a portion of the pixel region that the current fragment overlaps; and 2) a portion of the pixel region un-obscured by the current fragment. In this case, the sub-system computes the coverage for the un-obscured portion and sets the alpha for it, which remains the same as the original pixel region. To accomplish this, the coverage array loop control 1234 updates the in-use mask 1236, and instructs the new coverage control 1238 to update the coverage array mask 1230. The coverage array alpha entry corresponding to this second pixel region remains the same as the current pixel region (Aold) because it is unchanged by the current fragment.
Repeating the approach described above, the sub-system loops through each in-use entry for the current fragment, and computes the effect, if any, of the current fragment on each pixel region. It then repeats the process for subsequent fragments in the list until the list is empty.
The clamp and adjust block 1248 performs the clamping of the accumulated color to the proper range (this is needed due to rounding in the Coverage Scaler block which can result in colors or alphas which exceed the 8 bit range) and an adjustment for errors introduced by scaling a value by an 8 bit binary number representing 1. An adjustment for this type of error may be necessary in some circumstances because a value of 1 is actually represented by the hex value "FF." In other words, an alpha range of 0 to 1 is represented by a range of 8 bit numbers from 00 to FF. Therefore, when multiplying a number x by FF, the result must by x. The adjustment ensures that the result of multiplying by FF is properly rounded to x.
The feedback path 1250 to the pixel buffers exists to support a mode where resolved pixel values are stored back into the pixel buffers. This enables multi-pass rendering on resolved pixel data without transfering a chunk of resolved data to the shared memory off the tiler.
If the fragment resolve subsystem is not in the feedback mode, then the clamp and adjust block 1248 transfers the resolved pixel data to block staging buffers via the data path 1252 shown in FIG. 18. These block staging buffers are used to buffer resolved pixel data before it is compressed in 8.times.8 pixel blocks.
Multi-Pass Rendering
The image processor supports sophisticated multi-pass shading and lighting functions, including for example, reflection maps and multi-light source shadows. In one embodiment, the image processor supports two forms of multi-pass rendering. The first form of multi-pass rendering includes rendering geometry to generate a rendered image, storing the rendered image, and then using the rendered image in a subsequent rendering pass to render the same geometry or different geometry in the same scene. In one embodiment, these functions are carried out using the tiler and the shared memory. The tiler renders geometry to a gsprite, transfers the gsprite to shared memory, and then retrieves the gsprite from shared memory for use in a subsequent rendering pass.
The second form of multi-pass rendering includes rasterizing the same geometry in multiple passes, and performing pixel compositing operations into a rasterization buffer. In one embodiment, the tiler supports compositing functions into a rasterization buffer. The pixel engine within the tiler supports blending of pixel fragments generated during more than one rendering pass on the same geometry in a scene. The first and second form of multi-pass rendering can be used separately or combined to support advanced lighting and shading operations.
Shadows can be created using a version of the multi-pass rendering approaches outlined above. In one embodiment, shadows are created using multiple rendering passes. First, the tiler renders the scene from the perspective of a light source to generate a shadow depth map, which is then stored in gsprite memory. In a second pass, the geometry is rasterized from the perspective of the viewpoint, and each pixel is transformed back into light source coordinates. The depth of the pixels relative to the light source are compared against depth values accessed from the depth map to determine whether and to what extent the pixel is in shadow. To support this functionality, the image processor supports the following rendering modes:
Render Normal: This is the default rendering mode used for all non-shadowed geometry.
Render for Z-Map: Render to create a depth map for a light source point of view to be used as a texture in shadow luminance rendering.
Render for Shadow Luminance: Render using the shadow depth map.
Because of its support for multi-pass rendering operations as outlined above, the image processor can support a wide variety of lighting and shading operations to create many different effects. These effects include combinations of shadows, possibly from multiple light sources, reflections, and texture mapping of various lighting parameters, etc. General lighting functions are computed using a series of passes. During each pass, the tiler makes a single texture map access for each pixel rasterized. The results of each rendering pass can be combined in the rasterization buffer.
The ability to render geometry to a gsprite enables the tiler to overcome the limitations of existing systems which cannot store intermediate results. This is a major advantage because it enables the system to support a broader range of lighting and shading operations. Another advantage is that a gsprite can be mapped to other geometry in the scene or used in rendering other scenes for subsequent image frames.
An example will illustrate the concept. Consider the lighting model representing a diffuse material illuminated by two shadowing light sources, given by
where D is the texture-mapped diffuse color, N.multidot.L.sub.i is the dot product of the polygon normal with the light direction (L.sub.1 for light 1, or L.sub.2 for light 2), and .sub.si is the shadow modulation factor for light I (i.e. i=1 or 2) computed using light depth maps. Computing the shadow modulation factor with graphics hardware can be accomplished using the three pass shadowing technique introduced above. This shadowing technique requires a table lookup very similar to standard texture mapping, but accesses depths from the point of view of the light rather than colors. The depths are compared with a depth in light space interpolated over the polygon to determine whether a given point is illuminated or in shadow.
This lighting expression may be decomposed into 4 passes:
where the result of each pass must be added or multiplied with previously computed terms in the lighting expression to yield the final result. The problem is that the result of pass 3 can not be blended with the result from passes 1 and 2: it must first be multiplied by the result of pass 4 before being added to the result of pass 2.
The above problem is solved in one embodiment by using gsprites to store intermediate results. For the above example of the diffuse material illuminated by two shadowing light sources, the tiler makes the four passes shown in the following table:
In pass 1, the polygon is rendered interpolating N.multidot.L.sub.1 and using D as the texture map. In pass 2, the product of pass 1 is multiplied (*) by s.sub.1, the shadow modulation factor for light 1, and stored to gsprite S. In pass 3, the polygon is rendered interpolating N.multidot.L.sub.2 and using D as the texture map. In pass 4, the product of pass 3 is multiplied by s.sub.2, the shadow modulation factor for light 2. The expression D N.multidot.L.sub.2 s.sub.2 is in the accumulator, and the expression D N.multidot.L.sub.1 s.sub.1 is stored in gsprite S.
The addition of the current buffer contents and the gsprite S after pass 4 is performed in a fifth pass. A texture-mapped square covering the entire image is rendered, texture-mapped by gsprite S. The blend function is set to add, effectively adding the two images. Thus, the decomposition of lighting expressions with one accumulator is solved by using one accumulator along with gsprites.
The structure and operation of the tiler as well as its interaction with shared memory are described in detail above.
Another aspect of multi-pass rendering introduced above is the capability to perform pixel compositing operations in the rasterization buffer. Above, we described aspects of the tiler relating to pixel generating and resolving in detail (See FIGS. 9A-C. for example). The tiler supports high quality antialiasing by generating fragment lists, and then resolving depth sorted fragment lists to compute final pixel values. One significant advantage of the tiler is its capability to combine fragments generated during rendering passes into the pixel and fragment buffers.
The process of blending fragments proceeds generally as follows. In a first pass, geometry in a scene is rendered to create fragments, which are stored in the fragment buffer. In a subsequent pass, the same geometry is rendered, and the fragments are blended with those in the fragment buffer.
FIG. 19 is a flow diagram illustrating fragment blending in one embodiment of the invention. When a fragment is generated which needs to be blended (1190), the pixel engine in the tiler attempts to blend the current fragment to a previously created fragment that represents a matching piece of geometry inside the pixel. At the specified pixel location, the pixel engine searches a stored fragment list from the beginning (1192) to find a fragment with the same Z-value as the current fragment (1194). If the stored fragment does not have the same Z-value as the current fragment, the next fragment in the stored fragment list is obtained (1196). If all fragments in the stored fragment list are exhausted (1198) without finding a fragment with a Z-value equal to the current fragment, then the blend process ends for the current fragment, and it is discarded.
In practice, a fragment should only be discarded in the case where the pixel engine previously merged the fragment that current fragment would otherwise be blended with. In this special case, the pixel engine has already blended to the merged fragment and has set a flag to prevent the pixel engine from merging to this merged fragment more than once. The current fragment is then discarded. We describe how to prevent more than one blend to a merged fragment below.
If more than one fragment exists with the same Z-value, the pixel engine attempts to find a stored fragment with similar coverage mask. The coverage mask of the incoming pixel data does not need to match the stored coverage mask exactly, but it preferably should be a subset of the stored coverage mask. For example, an AND operation of the two coverage masks should return the current coverage mask in order for the two fragments to be considered a match. If the result of the AND operation does not produce the current coverage mask, the current coverage mask does not "match" this particular stored coverage mask.
If the Z-value of the current fragment is equal to the stored fragment Z, and the coverage mask of the current fragment matches the stored fragment coverage mask (1200), the pixel engine checks a data bit called the "pass bit" in the stored fragment. In general, the pass bit is used to prevent blending in special cases even if the pixel engine identifies a matching fragment. The pass bit is described further below. If the coverage mask of the current fragment does not match, the next fragment in the fragment list is obtained (1196), and processing continues.
The pass bit addresses a complication caused by fragment merging. As described above, fragment merging is a technique to reduce the memory required for fragment storage. When a fragment arrives with a depth value and color value close to a fragment already inserted into the fragment list for a pixel, the fragment is merged into the existing fragment rather than allocated and inserted. The complication is that the merged fragment no longer corresponds to either of the merged fragments for blending purposes. As an example, consider two fragments, A and B, having the same depth value, that are merged in the first pass to create fragment C. In the second pass, the same geometry is rendered with the blending function set to add the colors. The fragments A and B are again generated, but without special testing, are blended twice with the merged fragment C. This causes an incorrectly large contribution to the color at fragment C.
To address this complication, the tiler blends to each fragment only once per pass, ignoring additional blending from other fragments which were merged in the initial pass. This is a reasonable approximation since the colors and opacities should have been very close in order for the fragments to have been merged. An additional bit field is added to each fragment to guarantee a single blending operation per fragment per pass, called the pass bit. The blending operation is performed only if the pass bit is not set (1200). In one implementation of this feature in the tiler, a stencil plane bit is used as the pass bit to block a blend operation on a merged fragment.
Referring again to FIG. 19, if the pass bit is not set in the matching fragment in the fragment buffer (1202), then the blending operation is performed using the generalized blending described previously, but only to the color and opacity of the matched fragment (1204). The pass bit is then set for the new merged fragment (1206) so that subsequent fragments that were merged initially are no longer blended. After blending, the current fragment is then discarded (1208), and no memory is allocated to store the current fragment.
Blending into the rasterization buffer includes 1) texture or shadow modulation to produce a composed pixel value; and 2) blending the composed pixel value with the existing contents of the rasterization buffer. In the tiler, the composed pixel value can either be a fully covered, opaque pixel (pixel record), a partially covered pixel (fragment record). Partially covered pixels include pixel data generated when a primitive partially covers a pixel location, or pixel data generated when a translucent pixel partially or fully covers a pixel location. The tiler supports blending of pixel records in the pixel buffer and fragment records in the fragment buffer. In a blend operation, the composed pixel value is blended with the existing contents of the pixel or fragment buffer.
In the implementations of the tiler shown in FIG. 9, the texture filter engine determines a filtered texture value for textures, or a filtered shadow depth map value for shadows. It composes this filter result with a pixel value from the rendered scene by modulating the color and/or alpha values of the pixel value. It then passes the composed pixel value to the pixel engine. For example, in the implementation of the tiler shown in FIG. 9B, the texture filter engine 401 takes an entry from the texture reference data queue 399 and composes the entry with a filtered texel value. The pixel engine 406 then combines the composed value with a corresponding entry in the pixel or fragment buffer 408, 410.
The following table lists the notational definitions used to describe blending operations in the tiler.
Texture or shadow modulation applies to both colors and opacity:
C.sub.c =C.sub.t C.sub.f
A.sub.c =A.sub.t A.sub.f
Several blending modes can combine the composed and existing buffer values. The new buffer value (designated with a prime) is:
C.sub.b '=C.sub.b C.sub.b +c.sub.c C.sub.c
A.sub.b '=a.sub.b A.sub.b +a.sub.c A.sub.c
The blending mode determines a set of factors (c.sub.b, c.sub.c, a.sub.b, a.sub.c). The c values contain three components--one for each color (R, G, and B).
The following table gives the values of the color factors in each color blending mode.
The following table gives the values of the alpha factor in each alpha blending mode.
A wide range of color and alpha combinations are possible by manipulating two factors:
1) The color blending and alpha blending modes; and
2) The constants C.sub.-- Constant and A.sub.-- Constant, which when set to either zero or one effect simple accumulation of passes.
In sum, the tiler supports a generalized blending function by combining multi-pass rendering with fragment list processing. While we have described a specific approach to blending fragments, this approach can be modified and used in different architectures without departing from the scope of the invention. The specific hardware used to implement fragment processing can vary. For example, the pixel engine and fragment buffers can be implemented using a variety of different hardware components. At a higher level, it is not necessary that the fragment processing hardware be implemented in a chunking architecture. Other architectures, such as architectures employing parallel processing engines, can be used in the alternative.
When rendering objects with different lighting models, some of which require decomposition to gsprites, it is sometimes necessary to render some of the geometry in black in order to perform antialiasing. This occurs because gsprites do not retain depth or fragment list information from the rendering, only a single color and opacity. If an object T requires multiple passes and is contained in a background scene requiring only a single pass (e.g. a spaceship occluded by a group of trees), then the background must be rendered in black for some of the passes required for T. The rendering is needed in order to properly occlude hidden parts of T so that the resulting image can be combined with previous results using purely 2-D operations.
In one embodiment, this "extraneous" rendering is eliminated with the addition of a color-clear operation. The color-clear operation clears color values for pixels in the pixel buffer to zero (black) while retaining the Z-values, and clears the color values for the corresponding fragments in the fragment buffer to zero (black) while retaining the Z-values, coverage masks, and opacity of the fragments.
Consider as an example, a scene containing an object T requiring four passes (e.g. a texture mapped object, a spaceship T, illuminated by two shadowing light sources) among a set of objects requiring a single pass (e.g. a forest of trees, some of which occlude the object). An approach including rendering some geometry to black occurs as follows:
1. Render the background and T fully illuminated by light 1.
2. Render T for light 1 shadow modulation and blend in using multiply blend mode.
3. Save the resulting image.
4. Render the background in black and T fully illuminated by light 2.
5. Render T for light 2 shadow modulation and blend in using multiply blend mode.
6. Add in the image saved from step 3.
The background is rendered to black in step 4 because proper antialiased hidden surface elimination in case T is occluded by the background. Since the background contribution was already added in step 1, the background contribution is drawn in black in step 4 to avoid increasing its contribution when the two images are added. In this example, the amount of duplicated work (i.e. the work of drawing the background again but in black) is a small fraction of the total work. However, if T requires many passes and the background geometry is complex with respect to T's geometry, the duplicated work becomes significant.
In one embodiment, the duplicated work is eliminated. A color-clear operation is added which clears the color values in every pixel fragment to zero without changing the fragments' Z-values, coverage masks, or opacity. Rendering is performed on all the geometry so that antialiased hidden surface removal is performed once. The color-clear passes do not insert any more fragments; they simple blend colors into existing fragments. The color-clear operation allows the state to be reset in order to begin accumulating another term in the lighting expression. This avoids computing duplicate renderings of geometry with the color set to black.
With the color-clear capability, the example graphics scene would be rendered with these steps:
1. Render the background and T fully illuminated by light 1.
2. Render T for light 1 shadow modulation and blend in using multiply blending mode.
*3. Save the resulting image and invoke color-clear.
*4. Render Tfully illuminated by light 2.
5. Render T for light 2 shadow modulation and blend in using multiply blend mode.
6. Add in the image save from step 3.
Note the difference in steps 3 and 4 in the new scheme from the prior example without color clear. As a result of the color clear operation, a significant improvement in processing is achieved by eliminating duplicated work for processing the background colors of complex graphics image.
To further optimize processing, an additional bit of memory at each pixel can be used to indicate whether any fragments in that pixel have been blended to. This makes both the color-clear and fragment resolution operations easier since only pixels that have been modified need to be cleared (e.g. by the color-clear operation) or computed (e.g. for fragment resolution). During fragment resolution, pixels that have not been blended to immediately output zero for their colors and opacities into the destination gsprite. This bit saves a significant amount of work if many pixels have not been blended to, regardless of how many fragments these untouched pixels contain.
In another embodiment of the invention, a color-opacity-clear operation is used instead of a color-clear operation. If objects have a static transparency, that is the transparency is not changing across illuminating passes, the color-clear operation leaves the fragment transparencies alone. If the geometry does not have static transparency across illumination passes, then a color-opacity operation is used instead. The color-opacity operation clears the modeling opacities in each fragment to one so that the multi-pass decomposition can happen on the opacities as well as the colors. That is, the color-opacity operation will clear the color values in every pixel fragment (by setting them to zero), while clearing the opacities in each fragment (by setting them to one). The opacities cleared are the modeling opacities rather than "transparency" due to partial coverage of the fragment. The blending modes described above allow the fragment opacity to be blended to as well as the fragment color. The coloropacity clear operation also significantly improves processing by eliminating duplicated work for processing the background opacity of a complex graphics image.
In the tiler shown in FIGS. 9A-9C, the pixel engine 406 performs the color and opacity clear operations. To perform the color clear, the pixel buffer sets the color values in the pixel buffer and corresponding fragment list in the fragment buffer to zero. Similarly, to perform an opacity clear, the pixel buffer sets the alpha values in the pixel buffer and corresponding fragment list to zero.
We have described various aspects of an graphics processing system, its architecture, and associated methods with references to several embodiments. While we have described several embodiments in detail, we do not intend to limit our invention to these specific embodiments. For example, multi-pass rendering techniques described above can be implemented in different graphics architectures. The specific components of the tiler (FIGS. 9A-C) can be modified without departing from the scope of the invention. Variation of our systems and methods can be implemented in hardware or software or a combination of both.
Image Compression
As was described above, the chunk size and sequential rendering is very valuable for image compression techniques since an entire 32.times.32 pixel chunk is completely rendered before the next chunk is computed, and thus can be compressed immediately. The tiler supports a lossy and lossless form of compression to compress chunks. Both the lossy and lossless form of compression compress chunks in independent blocks of 8.times.8 pixels, so each compressed 32.times.32 pixel chunk would consist of 16 such compressed blocks.
Compression of images allows much smaller memory size requirements and vastly reduced memory bandwidth requirements. The design uses a combination of caching, prefetch strategies, as well as chunking to reduce the latencies and overhead due to compression and block access. Since the entire image is computed in a 32.times.32 pixel buffer, gsprite image compression is achieved with minimal overhead. The overall conceptual design of the compression architecture is shown in FIG. 20.
The transformation engine 660 (FIG. 20) calculates model and viewing transformations, clipping, lighting, etc. and passes this information to the tiler 662. As the tiler processes transformation information, it reads texture data from texture memory 664. The texture data is stored in a compressed format, so as the texture blocks are needed, they are decompressed by the tiler decompression engine 666 and cached in an on-chip texture cache on the tiler. As the tiler resolves pixel data it transfers the resolved data to the tiler compression engine 668 which compresses the resolved data and stores the compressed data in gsprite memory 670. When the gsprite engine 672 needs the compressed gsprite data, it uses the gsprite decompression engine 674 to decompress the gsprite data from gsprite memory 664 and cache the data on an on-chip gsprite cache. In the actual hardware, the texture memory 664 and gsprite memory 670 are identical (i.e. the compressed data is stored in one memory shared by the various engines). Common shared memory is not required as long as the compression and decompression methods used are compatible. The gsprite data can also be taken from a data base or some other image source 676 and saved in the texture memory 664 and the gsprite memory 670.
One implementation of the invention supports both lossy and lossless compression and decompression of pixel blocks.
The lossy form of image compression has two stages: a lossy first stage, and a lossless second stage. The lossy form of compression begins with an optional color space conversion from red, green, blue (R, G, B) intensity values to luminance (Y) and chrominance (U and V, also referred to as Cr and Cb) values. The lossy stage includes a direct cosine transform (DCT) and a quantization that reduces the accuracy of certain frequency components.
The second stage is a lossless form of compression comprising Huffinan coding and run length encoding (RLE). Alternative coding methods such as arithmetic coding can be used in place of Huffinan coding.
Decompression for the lossy method includes a decoding stage, a dequantization of the compressed data, an inverse DCT, and an optional color space conversion from YUV to RGB.
The lossless form of compression includes an optional lossless color space conversion from RGB to YUV, a prediction stage, and a lossless encoding stage. This encoding stage can be identical to the entropy coding stage in the lossy form of compression. Decompression for this lossless method comprises a decoding stage, an inverse prediction step on each color component, and an optional color space conversion from YUV to RGB.
Lossy Compression/Decompression
One specific implementation of the lossy compression method in the compression engine 414 (FIGS. 9A-C) of the tiler occurs in four or five steps:
1. Convert the RGB data input to a YUV-like luminance-chrominance system (optional).
2. Perform a forward, two-dimensional discrete cosine transform (DCT) individually on each color component.
3. Order the two-dimensional DCT coefficients in approximately a monotonically increasing frequency order.
4. Quantize the DCT coefficients: Divide by either a uniform divisor or a frequency-dependent divisor.
5. Encode the resulting coefficients using Huffman encoding with fixed code tables.
Lossy decompression occurs in four or five steps:
1. Decode the compressed data input using Huffman decoding with fixed code tables.
2. Dequantize the compressed data: Multiply by the uniform multiplier or the frequency-dependent multiplier used in the quantization step of compression.
3. Reorder the linear array of data into the proper two-dimensional order for DCT coefficients.
4. Perform an inverse, two-dimensional DCT individually on each color component.
5. Convert the colors in the YUV-like luminance-chrominance system to RGB colors, if the compression process included the corresponding optional step.
Color Space Conversion
The color space conversion transforms the RGB colors to a brightness-color system with brightness coordinate Y and color coordinates U and V. This luminance-chrominance system is not a standard color space. Using this system improves the degree of compression because the color coordinates require only a small fraction of the bits needed to compress the brightness. The lossless, reversible conversion applies to each pixel independently and does not change the value of alpha.
RGB to YUV (for compression)
The conversion from integer RGB values to integer YUV values uses this transformation:
Y=(4R+4G+4B)/3-512
U=R-G
V=(4B-2R-2G)/3
YUV to RGB (for decompression)
The conversion from integer YUV values to integer RGB values uses this transformation:
R=(((Y+512)-V)/2+U+1)/2
G=(((Y+512)-V)/2-U+1)/2
B=((Y+512)/2+V+1)/2
Discrete Cosine Transform
Images and textures are pixels that contain the amplitudes for three colors and the amplitude for opacity. The pixel positions correspond to a spatial location in an image or texture map. An image or texture in this form is in the spatial domain. For images or textures, the discrete cosine transform (DCT) calculates coefficients that multiply the basis functions of the DCT. Applying the DCT to an image or texture yields a set of coefficients that equivalently represent the image or texture. An image or texture in this form is in the frequency domain.
The DCT maps the amplitude of the colors and opacity of an 8 by 8 pixel block between the spatial domain and the frequency domain. In the frequency domain, adjacent coefficients are less correlated, and the compression process can treat each coefficient independently without reducing the compression efficiency.
The forward DCT maps the spatial domain to the frequency domain, and conversely, the inverse DCT maps the frequency domain to the spatial domain. One suitable approach for the forward and inverse DCT is the approach described in FIGS. A. 1.1 and A. 1.2 in Discrete Cosine Transform. Rao, K. R., and P. Yip. San Diego: Academic Press, Inc., 1990.
The two-dimensional DCT produces a two-dimensional array of coefficients for the frequency domain representation of each color component. Zigzag ordering rearranges the coefficients so that low DCT frequencies tend to occur at low positions of a linear array. In this order, the probability of a coefficient being zero is approximately a monotonically increasing function of the position in the linear array (as given by the linear index). This ordering simplifies perceptual quantization and LOD filtering and also significantly improves the performance of the run-length encoding (RLE).
Quantization
Quantization reduces the number of different values that the zigzag-ordered DCT coefficients can have by dividing the coefficients by an integer. Depending on the value of the compression type parameter, quantization can be either uniform or perceptual. Neither case modifies the DC frequency coefficient (index=0), but instead passes it along unaltered.
The quantization process begins with the specification of the quantization factor for an image or portion of an image. In this implementation, a quantization factor is specified for a 32.times.32 pixel chunk. A quantization index (QIndex) specifies a corresponding quantization factor (QFactor) to use for the chunk. The following table shows the relationship between Qindex and Qfactor.
Each color plane has a different value for the chunk QIndex. A QIndex of 15 selects a QFactor of 4096, which produces zeros during quantization and inverse quantization. The quantization process divides each coefficient in a block by a QFactor and rounds it back to an integer. The inverse quantization process multiplies each coefficient by a QFactor. Quantization and inverse quantization do not change the DC frequency component.
Block Quantization Factor
The QIndex, and thus the QFactor, can vary from block to block (8.times.8 pixels). The QIndex for a block results from incrementing the QIndex for the chunk with a value embedded in the block compression type:
This increments the chunk QIndex by one, two, three, or four. Because the largest possible QIndex value is 15, any incremented value greater than 15 is set to 15.
The Qlndex, and thus the QFactor, can also vary from coefficient to coefficient (from array index to array index) if the quantization type is perceptual.
For uniform quantization, the coefficient QIndex is equal to the block QIndex, so the corresponding QFactor either multiplies (inverse quantization) or divides (quantization) each coefficient in the block.
For perceptual quantization, the coefficient QIndex depends on the value (0 . . . 63) of the index in the linear array. The following table gives the resulting coefficient QIndex as a function of the array index value.
Entropy Coding
Huffman/RLE coding processes the linear array of quantized DCT coefficients by:
1. Independently encoding non-zero coefficients with the fewest possible bits (because the DCT coefficients are uncorrelated).
2. Optimally encoding continuous "runs" of coefficients with zero values--especially at the end of the linear array (because of the zigzag ordering).
One suitable approach for the Huffman/RLE coding process is the Huffman/RLE coding process used for the AC coefficients in the well known JPEG still image compression standard.
To enable random access of blocks, this particular approach does not encode the DC frequency coefficient (index=0), but instead passes it on unaltered.
The algorithm computes a series of variable-length code words, each of which describes:
1. The length, from zero to 15, of a run of zeros that precedes the next non-zero coefficient.
2. The number of additional bits required to specify the sign and mantissa of the next non-zero coefficient.
The sign and mantissa of the non-zero coefficient follows the code word. One reserved code word signifies that the remaining coefficients in a block are all zeros.
Encoding
The encoding of all blocks uses the typical Huffman tables for AC coefficients from Annex K, section K.3.2 of ISO International Standard 10918. This includes Table K.5 for the luminance (Y) AC coefficients and Table K.6 for the chrominance (U and V) AC coefficients.
Decoding
The decoding of all blocks uses the same fixed tables as the encoding process. Therefore, it is never necessary to store or to convey the Huffinan tables with the data.
Lossless Compression.backslash.Decompression
In the compression engine 414 in the tiler, lossless compression occurs in two or three steps:
1. Convert incoming RGB data to a YUV-like luminance-chrominance system (optional).
2. Perform a differential prediction calculation on each color component. Encode the resulting coefficients using Huffinan encoding with fixed code tables.
Lossless decompression in the decompression engines 404, 450 in the tiler and gsprite engine occurs in two or three steps:
1. Decode the incoming compressed data using Huffman decoding with fixed code tables.
2. Perform an inverse, differential prediction (reconstruction) on each color component.
3. Convert the colors in the YUV-like luminance-chrominance system to RGB colors if the compression process included this corresponding optional step.
Color Space Conversion
The color space conversion reversibly transforms the RGB colors to a brightness-color system with brightness coordinate Y and color coordinates U and V. This is a unique color space that improves the degree of compression even more than the YUV system above because the numbers entering the Huffman/RLE encoder are smaller, and hence more compressible. The color space conversion applies to each pixel independently and does not change the value of alpha.
RGB to YUV for compression)
The conversion from integer RGB values to integer YUV values uses this transformation:
Y=G
U=R-G
V=B-G
YUV to RGB for decompression)
The conversion from integer YUV values to integer RGB values uses this transformation:
R=Y+U
G=Y
B=Y+V
Alpha information is not altered during the color space transform.
The color space transform can be bypassed. The decompressor is notified in cases where the color transform is bypassed by a flag in a gsprite control data structure.
The prediction stage occurs after the color space transform. Prediction is a losslessly invertible step that reduces the entropy of most source images, particularly images with lots of blank space and horizontal and vertical lines.
In the prediction stage of compression and the inverse prediction stage of decompression:
1. p(x, y) are the pixel values input to the compressor and output from the decompression engine; and
2. d(x, y) are the difference values input to the coder in the next stage of the compression engine and output from the inverse of the coder in the decompression engine.
Prediction is computed as follows:
d(x, y)=p(x, y) for x=0, y=0
d(x, y)=p(x, y)-p(x, y-1) for x=0, y>0
d(x, y)=p(x, y)-p(x-1,y) for x>0
Inverse prediction in the decompression engine is computed as follows:
p(x, y)=d(x, y) for x=0, y=0
p(x, y)=p(x, y-1)+d(x, y) for x=0, y>0
p(x, y)=p(x-1,y)+d(x, y) for x>0
The Huffman/RLE coding and decoding is the same as for the lossy form of decompression/decompression in this implementation.
The compression methods described above compress images in independent blocks of 8.times.8 pixels. Therefore, in the chunking architecture described above, each compressed 32.times.32 pixel chunk consists of 16 such blocks. To facilitate compression of a 32.times.32 pixel chunk, the anti-aliasing engine 412 resolves pixel data into 8.times.8 pixel blocks. The 8.times.8 pixel blocks are buffered such that a first buffer is filled while a second buffer is compressed.
Controls and Parameters
As introduced above, the tiler (FIGS. 9A-9C) renders gsprites one chunk at a time. These chunks are comprised of pixel blocks (in this case, 16 8.times.8 pixel blocks). For texture mapping, shadowing, and some multi-pass rendering operations, the tiler fetches gsprite or texture blocks from memory. To compose a frame, the gsprite engine (FIG. 12A-B) fetches gsprite blocks, transforms pixels to screen space, and composites pixels in a compositing buffer.
There are a number of control parameters that govern processing of gsprites, chunks, and blocks. A gsprite display list stores a list of gsprites comprising a display image. This display list includes pointers to gsprites, and more specifically, gsprite header blocks. As described further below, the gsprite header block stores a number of attributes of a gsprite including gsprite width, height, and an affine transform defined in terms of a screen space parallelogram. The gsprite header block also includes a list of its member chunks. In one implementation, this list is in the form of pointers or handles to chunk control blocks.
Chunk control blocks include per chunk and per block parameters. The per chunk parameters include a YUV color converter bypass, default Q factors, a perceptual quantization flag, pixel format, and whether the pixel data resides in memory managed in Memory Allocation Units (MAU) in linear memory. An MAU is a piece of shared memory used to allocate chunk memory. MAU managed memory includes a list of MAUs (124 bytes for example), each MAU having a pointer to the next MAU. In one specific implementation for example, the chunk control blocks are stored in sequential MAUs for each gsprite.
The per block parameters include compression type, number of MAUs the block spans, and a block pointer pointing to the first byte of pixel data for the block. The specific block format is an 8.times.8.times.4 array of pixels that encode 32 bit pixels (8 bits for RGB and Alpha).
The steps for retrieving a pixel given (X,Y) coordinates in a gsprite using the above control parameters include:
1) Divide Y and X by 32 to derive the chunk row and column, respectively.
2) Form the chunk number by: (chunk row) * (width of sprite in chunks)+chunk column.
3) Form the Chunk Control Block offset by: (chunk number) * (size of chunk header block))
4) Form the Block offset within the Chunk Control Block by: (Y<4:3>*4+X<4:3>)*3.
5) Send the Block pointer to the Decompressed cache logic, receive a Block.
6) Form the pixel offset within the Block by (Y<2:0>*8)+X<2:0>
Here, a chunk offset is used to select a chunk. A block offset is then used to select a block pointer. The block pointer selects a block containing the pixel, and the pixel offset selects the pixel.
To access the block for a given pixel among compressed blocks of pixel data, the cache controls on the tiler and gsprite engine perform the following steps:
1) Form the MAU address by looking up the Block pointer value in the Chunk Control Block, and dividing by the size of the MAU.
2) Look up the number of MAUs allocated in the Chunk Control Block for this block.
3) Look up the next Block pointer address in the Chunk Control Block.
4) Form the length of the compressed block by: MAUs allocated * MAU size+2's complement of ((Block pointer) mod MAU size)+(next Block pointer) mod (MAU size)
5) Send the block address and the length of the compressed block to the Compressed Cache logic.
The compressed cache will read the first MAU, and if the length of the transfer has not been satisfied, then the pointer contained in the MAU will be used to access the start of the next MAU. This process continues, until the transfer length has been met.
To support MIP map texture operations, the tiler supports another level of indexing. One method for indexing a MIP map level includes the following steps:
1) For a given sprite, form a table of mip chunk level offsets by:
mipChunkOffset0!=0.backslash. Offset for level of detail 0
For each level of mip map:
mipChunkOffsetlevel+1!=width of sprite/(20level) * height of sprite/(20level)+mipChunkOffsetlevel!
2) Use the LOD parameter to get the mip chunk offset.
At this point, the mip chunk offset, width of sprite/(20level), and height of sprite/(20level) can be used to find any desired chunk within the chosen level of detail for the current gsprite.
Texture and Shadow Filtering
FIG. 21 is a block diagram illustrating one implementation of the texture filter engine (401, FIG. 9B). The texture filter engine reads instances of texture reference data from a pixel queue (texture reference data queue 399 in FIG. 9B) and computes alpha and color values (alpha, and RGB color factors) or shadow coefficients for these instances. This implementation supports both texture and shadow filtering. For texture mapping operations, the texture filter engine computes texture colors and alpha, and filters the texture colors to compute alpha and color factors. For shadowing operations, the texture filter engine performs depth compares and filters the resulting values to compute shadow attenuation coefficients (s).
The pixel queue receives texture reference data from a rasterizer (such as the scan convert block 395 in FIG. 9B) and acts as a FIFO buffer to the texture filter engine 401. The "sample valid" data specifies which samples in a set of texture or shadow map elements fetched from the texture cache are valid for the current filtering operation.
For a texture mapping operation, the texture reference data includes the coordinates of a pixel location mapped into the texture, (s,t). To support tri-linear MIP-mapping, the inputs include the (s,t) coordinates for the two closest MIP map levels (hi, lo) and the level of detail (LOD). The "accumulate scale" data is used to control weighting factors applied to the output of the color component interpolators. The "extend control" data are data bits that control texture extend modes. The texture extend modes instruct the texture filter engine to perform either a clamp, wrap, or reflect operation when a texture request is outside the texture map area.
For shadowing operations, the inputs include a sample index, (s,t) coordinates of a pixel location mapped into the shadow map, and a beta, which represents the depth of the geometric primitive from the light source for a given pixel location. The sample index relates to the specific manner in which the shadow filter operates on shadow map elements or "samples." In this specific implementation, the texture filter engine operates on 8 samples per clock cycle. In the case of shadow filtering, these samples correspond to a 4.times.2 grid. For example, the shadow filter operates on a total of 2 sets of samples for 4.times.4 mode (4.times.2+4.times.2=4.times.4) and 8 sets for the 8.times.8 mode. In the case of 4.times.4 mode, the shadow filter applies a 3.times.3 filter four times, one each to the upper left, upper right, lower left, and lower right 3.times.3 blocks in the 4.times.4 overall footprint. In the first clock cycle, it processes the upper 4.times.2 grid and in the second clock it processes the lower 4.times.2 grid in the 4.times.4 block. The sample index is an index used to identify the set of 8 samples currently being processed. The sample index steps through 2 clock cycles for the 4.times.4 case and 8 clock cycles for the 8.times.8 case and identifies which 4.times.2 subset is currently being processed.
As shown in FIG. 21, the texture filter engine includes a key generator 1310, fraction control 1312, color component interpolator 1314, shadow filter accumulator 1316, and accumulator and post-processor 1318.
In a texture mapping operation, the key generator 1310 reads the (s,t) coordinates and LOD and generates the cache keys to fetch corresponding texture data from the texture cache. The texture cache returns alpha and the RGB components in response to the texture requests. The fraction control 1312 receives the (s,t) coordinates as input and controls the operation of bi-linear and/or tri-linear interpolators in the color component interpolator 1314. The color component interpolator 1314 interpolates the texel samples to compute interpolated alpha and RGB components. The accumulator and post-post processor 1318 then scales the alpha and RGB components, accumulates the scaled components, and outputs alpha and color factors corresponding to a pixel location currently being processed. These alpha and color factors are color and alpha values input to the pixel engine, as input to the texture modulation process.
In anisotropic texture mapping, the color component interpolators 1314 walk along the line of anisotropy and perform tri-linear interpolation at each step. The accumulator 1318 acts as a one dimensional filter, scaling the alpha and color components and then accumulating the scaled components. In one specific embodiment, the accumulator 1318 scales the alpha and color components using trapezoidal or triangle filtering based on the ratio of anisotropy. In either case, the accumulator scales components at the far edges of the resampling filter to approximate a roll-off at the filter edges. To achieve trapezoidal filtering, the scale factor corresponds to a linear roll-off at the filter edges and is a constant at steps between the filter edges.
In one specific implementation, the scale factors for steps along the line of anisotropy are computed as follows. For an anisotropy ratio from 1 to 1 up to 2 to 1, the accumulator applies a weighting factor of 0.5 at each step of the anisotropic walker. For an anisotropy ratio of 2 to 1 and greater: the accumulator weights components by 1./anisotropy for steps n<(anisotropy-1)/2; and weights components by 0.5(anisotropy-2n)/anisotropy for n greater than or equal to (anisotropy-1)/2. The anisotropy ratio in this specific example is the ratio of the long to the short side of the best fit rectangle for an inverse Jacobian matrix. The inverse Jacobian matrix is a matrix of partial derivatives of the geometric transform from view space coordinates to texture coordinates (i.e., from (x,y) to (s,t) coordinates). The line of anisotropy is a line through the (s,t) coordinates in the direction of the longer column vector of the inverse Jacobian matrix.
For shadowing operations, the key generator 1310 reads the (s,t) coordinates of the pixel location mapped into the shadow map and generates cache keys. The texture cache returns shadow map elements (shadels) to the shadow filter accumulator 1316. The shadow filter receives the shadow index and beta as input, and compares the depth of the current instance of pixel data in light space with the depth values in the filter footprint to generate a shadow mask. The shadow filter accumulator sums elements in the shadow mask and divides the sum by the number of samples. In this implementation, the texture filter engine achieves the smooth roll off at the edges of the filter footprint by applying a trapezoidal filter to the result of the depth compare step. To implement the trapezoidal filter, the shadow accumulation filter computes four preliminary shadow coefficients by applying a 3.times.3, or 7.times.7 box filter four times to a 4.times.4 or 8.times.8 filter footprint, respectively and passes the four preliminary coefficients to one of the color interpolators 1314. This color interpolator 1314 performs bilinear interpolation on the preliminary coefficients to compute a final shadow coefficient.
As introduced above, the key generator 1310 reads (s,t) coordinates from the pixel queue and generates cache keys to fetch texture data from the texture cache. FIG. 22 is a block diagram illustrating the key generator in more detail. Based on the (s,t) coordinates in the hi and lo MIP maps (the two closest MIP maps), the key generator computes the texture sample locations in the hi and lo MIP maps (1340). The key generator then computes the cache keys from these samples (1342). The key generator transfers the cache keys, (s,t) coordinates and LOD for the hi and lo MIP map levels to the texture cache, which returns the requested texture samples. Of course, if only one texture map level of detail is used, the key generator only generates keys for one texture map.
The fraction control 1312 in FIG. 21 controls the interpolation between samples in a texture or shadow map, and between MIP map levels for tri-linear interpolation. To support bi-linear interpolation, the fraction control controls weighting between samples in a texture or shadow map. To support tri-linear interpolation, the fraction control instructs the interpolators to interpolate between the four nearest samples to a point mapped into the two closest MIP map levels (bi-linear interpolation) and then instructs a linear interpolator to blend the result from the two MIP map levels. The fraction control receives the LOD and (s,t) coordinates for the hi and lo MIP map levels as input and controls interpolation between samples at each MIP level and between MIP map levels.
The color component interpolator 1314 includes interpolators for alpha and RGB color components. FIG. 23 is a block diagram illustrating one of the four interpolators in more detail. This interpolator handles color component interpolation for one component and performs bi-linear interpolation on shadow coefficients. The other color component interpolators handle only a color component.
The color component interpolator receives texels or shadow map elements from the texture cache and applies them to a bank of multiplexers 1350. When input to the bank of multiplexers 1350, the sample valid data specifies which of the samples are valid, i.e. those that should be used for the current texture or shadowing operation. Based on the sample valid control signals, the multiplexers select either the incoming sample or a texture background color 1352. For shadowing operations, the color component interpolator 1314 passes shadow elements to the shadow filter accumulator 1316. The three color channels are used to form a single 24 bit wide shadow map element, and the alpha channel is ignored in shadowing operations. For texture mapping operations, the color component interpolator transfers texture samples to the stages of linear interpolators 1354, 1356 and 1358.
In tri-linear interpolation, the color component interpolator uses three stages of linear interpolators, two to interpolate between samples at each MIP map level (1354 and 1356), and another to blend the result from each MIP level (1358). The color component interpolator performs bi-linear interpolation to combine shadow coefficients computed from 4 filter footprints. As shown in FIG. 23, it uses the last two stages (1356 and 1358) to perform this bi-linear interpolation. A second bank of multiplexers 1360 selects between four shadow coefficients and the output of the first stage of linear interpolators 1354. In both texture mapping and shadowing operations, the color component interpolator transfers the output of the interpolator stages to the accumulator and post-processor 1318.
The shadow filter accumulator 1316 receives a sample index and light depth value (beta) from the pixel queue, compares the light depth value with shadow map elements returned from the texture cache to generate shadow masks, and filters the shadow masks to compute preliminary shadow coefficients. FIG. 24. is a block diagram illustrating the shadow filter accumulator in more detail. Depth comparators in the shadow filter accumulator compare the depth of the shadow elements in the filter footprint and generate a shadow mask. In this particular case, the shadow mask is 8 bits with boolean values corresponding to a 4.times.2 section of the filter footprint.
The footprint control 1372 selects the current 4.times.2 section of the overall footprint based on the sample index value from the pixel queue. The footprint control transfers a footprint mask to each of four shadow contribution blocks based on the clock cycle and the filtering mode (2.times.2, 4.times.4 or 8.times.8). The footprint mask indicates which of the 8 shadow mask elements are valid at the current clock cycle for each of four box filters, in the 4.times.4 and 8.times.8 modes. In the two by two mode, the shadow filter accumulator outputs four booleans indicating whether each of the four nearest samples are in shadow or not.
As noted above, the shadow filter accumulator applies four box filters (3.times.3 or 7.times.7, e.g.) to the samples in the filter footprint. Each of the shadow contribution blocks combine the footprint mask and the shadow mask to determine which elements of the shadow mask are valid for the current clock cycle and then sum the valid elements. After accumulating the valid elements in the shadow mask for the entire filter footprint, the shadow contribution blocks divide the sum by the number of samples to compute preliminary shadow coefficients, which are transferred to a bi-linear interpolation stage in the color interpolator. The color interpolator then interpolates between the four preliminary shadow coefficients to compute a final shadow coefficient.
The accumulator and post-processor 1318 receives alpha and color components from the color component interpolator 1314 and computes color and alpha factors for each instance of texture reference data. For shadowing operations, the texture filter engine uses one channel (alpha or RGB) to compute a shadow attenuation coefficient. The shadow filtering logic can also be implemented separately. FIG. 25 is a block diagram illustrating the accumulator and post-processor in more detail. As shown, each color component (alpha and RGB) has a scale and accumulator. The scale and accumulator 1380 for each component receives the accumulation scale and a color component as input, and in response, scales the color component and adds it to an accumulated component value in the component sum block 1382. For example, in anisotropic filtering, the scale and accumulate blocks 1380 weight the output of the reconstruction filter (tri-linear interpolator), as the texture filter engine walks along the line of anisotropy. After the last step, the scale and accumulators for alpha and RGB components output the final color component factors.
For shadowing operations, the scale and accumulate block bypasses the multiply operation but adds an ambient offset. The ambient offset ensures that even objects totally in shadow will still be visible. For example, a shadow coefficient of 1 means totally illuminated, a shadow coefficient of 0 means totally in shadow. If colors were multiplied by a coefficient of zero, the object would not be visible at that pixel location. Thus, an offset is added and the shadow coefficients are clamped to 1 such that the offset shadow coefficients range from the offset value to 1.
The shadow post processor 1384 does the replication of the scalar shadow attenuation `s` to all 3 color channels and (conditionally) to the alpha channel. There is also a conditional complimenting (s=1-s) of the shadow attenuation for to compute a shadow image. A shadow image is an array of shadow coefficients or an array of the compliments of shadow coefficients which may be used to shadow a gsprite.
Finally, the multiplexer stage 1386 selects either the shadow coefficients, for a shadowing operations, or RGB and alpha components for texture mapping operations. In sum, the texture filter engine 401 performs both shadowing and texturing operations. It passes the result of texture mapping operations to a texture modulation stage. Texture modulation typically includes multiplying the RGB color values from the texture filter by an interpolated color or color values computed in the scan convert block. In addition for graphical objects with translucency, texture modulation can also include multiplying the alpha value from the texture filter by an interpolated alpha value from the scan convert block. Depending on the implementation, texture modulation can be implemented in the texture filter engine (element 401 in FIG. 9B) or the pixel engine (element 406 in FIG. 9B). It may also be implemented in the scan convert block (element 394 in FIG. 9A or element 397 in FIG. 9C). In one implementation, the texture filter engine 401 combines an interpolated value with the filtered value to compute a composed value. The pixel engine 406 then determines whether to store or combine a composed value with a corresponding RGB component or alpha component stored in the pixel or fragment buffers for a corresponding pixel location.
In the case of shadowing operations, the shadow coefficients can be applied to the RGB and alpha values at corresponding pixel locations in the pixel or fragment buffers, or to interpolated RGB or alpha values generated during the current pass and buffered in a queue. For example, if an object does not have a texture associated with it, the texture modulator in the texture filter engine 401 can multiply interpolated and un-resolved RGB and alpha values representing the lit image and stored in the texture reference data queue 391 (FIG. 9B) by the shadow attenuation coefficients from the accumulator and post processor.
While we have explained the invention in terms of specific embodiments, it should be understood the implementation of the invention can vary without departing from the scope of the invention.
In view of the many possible embodiments to which the principles of our invention may be put, we emphasize that the detailed embodiments described above are illustrative only and should not be taken as limiting the scope of our invention. Rather, we claim as our invention all such embodiments as may come within the scope and spirit of the following claims and equivalents to these claims.
Claims
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We claim:
1. A tiler for receiving geometric primitives representing three dimensional objects and rendering commands and for generating rendered image data to a two-dimensional image comprising a two dimensional array of pixel locations subdivided into contiguous sub-regions, the tiler comprising: a memory interface controller for reading the geometric primitives and the rendering commands; a set-up processor in communication with the memory interface controller for receiving a subset of the geometric primitives for each of the sub-regions of the image, parsing the rendering commands, and computing edge equation parameters; a scan-convert processor in communication with the set-up processor for receiving the equation parameters for the geometric primitives, and for scan converting the geometric primitives to produce pixel data including color, depth, and coverage data for pixel locations in each sub-region of the image, where the scan-convert processor is capable of generating two or more fragments including color, depth, and coverage data for each pixel location in the the sub-regions; a rasterization buffer for storing pixel data only for the pixel locations in the a sub-region currently being rasterized; a pixel engine for receiving the pixel data, for controlling the transfer of the pixel data to the rasterization buffer such that potentially visible fragments are stored for each of a plurality of pixel locations of the sub-region in the rasterization buffer; and an anti-aliasing engine for resolving pixel data stored in the rasterization buffer, including the potentially visible fragments, such that the potentially visible fragments are combined into a single set of color values per pixel location in the sub-region and the anti-aliased sub-region is transferred to a memory device, wherein the sub-regions of the image are rendered serially and fragments are stored for only one sub-region at a time in the rasterization buffer.
2. The tiler of claim 1 wherein the set-up processor includes a vertex input processor for parsing the rendering commands.
3. The tiler of claim 1 wherein the set-up processor includes vertex registers for storing vertex data for a geometric primitive.
4. The tiler of claim 1 further including a texture read queue for storing read requests for texture data and a texture address generator in communication with the texture read queue, wherein the set-up processor is in communication with the texture read queue for issuing the texture read requests, and the texture address generator is in communication with the texture read queue for determining memory addresses of blocks of the texture data, which are distributed in a memory device in non-contiguous blocks of memory.
5. The tiler of claim 1 wherein the scan-convert processor includes primitive registers for storing the equation parameters.
6. The tiler of claim 1 further including: a texture cache in communication with the memory control interface for storing texture data, and a texture filter in communication with the texture cache for processing texture data to compute texture color data for pixel locations; wherein the set-up processor is communication with the memory control interface for issuing requests for the texture data, the scan-convert processor is in communication with a texture filter for receiving the texture color data and producing the pixel data from the texture color data, and the set-up processor is capable of retrieving previously rendered sub-regions of the image as the texture data.
7. The tiler of claim 6 further including: a decompression engine in communication with the memory control interface for decompressing independently accessible blocks of compressed texture data.
8. The tiler of claim 1 wherein the rasterization buffer includes a pixel buffer for storing color depth data for pixel locations in the chunk, and a fragment buffer for storing color, coverage, and depth data for partially covered pixel locations corresponding to the pixel locations in the chunk.
9. The tiler of claim 8 wherein the fragment buffer stores fragment records for a pixel location in a linked list.
10. The tiler of claim 1 firther including a compression engine in communication with the anti-aliasing engine for compressing the resolved pixel data, wherein the compression engine is capable of compressing each of the sub-regions such that the anti-aliased pixel data for each of the compressed sub-regions is independently accessible in the memory device.
11. The tiler of claim 1 wherein the tiler stores the rendered pixel data for each of the sub-regions in non-contiguous memory blocks distributed among memory locations in the memory device and updates a data structure for the image indicating where the pixel data for each sub-region is stored.
12. A tiler for rendering sets of geometric primitives to image chunks, the tiler comprising: a set-up engine for receiving geometric primitives and rendering commands for a chunk, parsing the rendering commands, and queuing the geometric primitives in primitive registers; a scan convert engine in communication with the set-up engine for receiving the geometric primitives, and for scan converting the geometric primitives to produce pixel data including color, depth, texture coordinates, and coverage data for pixel locations in the chunk; a FIFO pixel queue in communication with the rasterizer for storing the color, depth, texture coordinates and coverage data for the pixel locations in the chunk; a texture cache; a texture cache control in communication with the scan convert engine for receiving the texture coordinates from the scan convert engine and in communication with a texture memory and the texture cache for fetching texture blocks from the texture memory and storing the texture blocks in the texture cache; a texture filter engine in communication with the FIFO pixel queue and the texture cache for receiving color data and texture coordinates from the FIFO pixel queue, for filtering the texture samples in a corresponding texture block stored in the texture cache to compute filtered pixel values for the pixel locations in the chunk, and for modulating the color data with the filtered pixel values to compute composed pixel values; a pixel buffer; a fragment buffer; a pixel engine in communication with the texture filter engine, and the FIFO pixel queue, for receiving generated pixels including the composed pixel values, coverage data, and depth data for pixel locations in the chunk, and in communication with the pixel and fragment buffers for performing depth compare operations between the depth data of the generated pixels with depth data of previously generated pixels stored in the pixel and fragment buffers, and for controlling storage of the generated pixels in the pixel and fragment buffers; and an anti-aliasing engine in communication with the fragment and pixel buffers for receiving the stored pixel data in the pixel and fragment buffers and for resolving the pixel data to compute final pixel values for pixel locations in the chunk after the scan convert engine and the texture filter engine have converted the geometric primitives for the chunk into the pixel data.
13. The tiler of claim 12 wherein the pixel buffer includes two buffers, each sized to store color, depth, and alpha data and a pointer to a fragment list in the fragment buffer for each pixel location in the chunk; and wherein the anti-aliasing engine is operable to resolve pixel data stored in one of the two buffers and corresponding fragment lists while the pixel engine stores generated pixel data for a subsequent chunk in the other pixel buffer and the fragment buffer.
14. The tiler of claim 12 further including a decompression engine in communication with the texture memory for receiving compressed texture blocks from texture memory, for decompressing the compressed texture blocks, and for transferring the decompressed texture blocks to the texture cache under control of the texture cache control.
15. The tiler of claim 14 wherein the texture memory stores a gsprite in compressed form, the gsprite comprises chunks and associated chunk control blocks, the chunk control blocks comprise pointers to the compressed texture blocks, and the texture cache control is communication with the texture memory for reading the chunk control blocks and fetching the compressed texture blocks using the pointers to locate the compressed texture blocks in the texture memory.
16. The tiler of claim 15 wherein the decompression engine includes a Huffinan/RLE decoder for decoding compressed texture data, and an inverse quantizer for multiplying frequency components of each texture block by quantization factors.
17. The tiler of claim 15 wherein the chunk control blocks each store indices to quantization factors used to decompress compressed texture blocks in corresponding chunks in the gsprite.
18. The tiler of claim 12 further including a compression engine in communication with the anti-aliasing engine for receiving the final pixel values and for compressing blocks of the final pixel values.
19. The tiler of claim 18 wherein the decompression engine is operable to perform both lossless and lossy forms of compression.
20. The tiler of claim 19 wherein the lossy form of compression includes a discrete cosine transform to generate coefficients and a quantization of the coefficients for each block.
21. The tiler of claim 19 wherein the lossless form of compression includes Huffinan and run length encoding.
22. A method for rendering objects for a scene to generate a display image at a frame rate, the method comprising: assigning geometric primitives of the objects among the two or more chunks representing 2D arrays of image samples; serially rendering the two or more chunks for at least two objects in the scene to produce a rendered image, the serial rendering step including the step of scan converting geometric primitives associated with a first chunk to produce per-sample subpixel data for image samples in the first chunk, and then resolving pixel data including the per-sample subpixel data from the first chunk, and repeating the scan converting and resolving steps for subsequent chunks of the two or more chunks such that per-sample subpixel data is used to perform antialiasing and is maintained for only one chunk at a time; storing the resolved pixel data for the at least two objects; and transferring the rendered image to the physical output device at the frame rate.
23. A method for compressing image data in a real-time graphics rendering pipeline in which geometric primitives in a view volume are rendered to generate a display image for a view space at a computational rate, the method comprising: assigning the geometric primitives in the view volume to two or more corresponding chunks in the view space; serially rendering the geometric primitives to the two or more corresponding chunks in a computational period including: rasterizing a first set of geometric primitives corresponding to a first chunk to generate pixel data including pixel fragments having color, coverage, and depth data for pixel locations in the first chunk, resolving the pixel data for the first chunk to compute a color value for the pixel location in the first chunk, and storing resolved pixel data for the first chunk, and repeating the rasterizing, resolving and storing steps for one or more subsequent chunks such that pixel fragments used to perform antialiasing are maintained for only one chunk at a time; and combining the resolved pixel data to generate a display image.
24. A graphics rendering system for serially rendering object geometry in a scene to a view space, the system comprising: a memory for storing rendered image data; an image pre-processor operable to transform the object geometry to the view space, and operable for sorting the transformed object geometry among plural chunks of the view space corresponding to 2D arrays of image samples; an image processor communicative with the image pre-processor for receiving the transformed object geometry for the plural chunks, operable to serially render the transformed object geometry for the plural chunks to compute pixel values and per sample subpixel data for pixel locations in one chunk at a time, and operable to perform antialiasing by resolving the per sample subpixel data for the chunk such that per sample subpixel data is maintained for only one chunk at a time, and communicative with the memory to store the pixel values for the plural chunks in the memory.
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