Coherent Signal Detector for AM-compatible Digital Audio Broadcast Waveform Recovery

1. Field of the Invention

This invention relates to radio broadcasting and, more particularly, to a method of and apparatus for recovering an underlying digital broadcast signal from an amplitude-modulated broadcast carrier.

2. Description of the Related Art

There has been increasing interest in the possibility of broadcasting digitally encoded audio signals to provide improved audio fidelity. Several approaches have been suggested. One such approach, set forth in U.S. Pat. No. 5,588,022, and incorporated herein by reference, teaches a method for simultaneously broadcasting analog and digital signals in a standard AM broadcasting channel. An amplitude-modulated (AM) radio frequency (RF) signal having a first frequency spectrum is broadcast. The amplitude-modulated radio frequency signal includes a first carrier modulated by an analog program signal. Simultaneously, a plurality of digitally-modulated carrier signals are broadcast within a bandwidth which encompasses the first frequency spectrum. Each of the digitally-modulated carrier signals is modulated by a portion of a digital program signal. A first group of the digitally-modulated carrier signals lies within the first frequency spectrum and is modulated in quadrature with the first carrier signal. Second and third groups of the digitally-modulated carrier signals lie outside of the first frequency spectrum and are modulated both in-phase and in-quadrature with the first carrier signal. Both transmitters and receivers are provided in accordance with that method.

The waveform in the AM compatible digital audio broadcasting system described in U.S. Pat. No. 5,588,022, has been formulated to provide optimal data throughput for the digital signal while avoiding cross talk into the analog AM channel. Multiple carriers are employed by means of orthogonal frequency division multiplexing (OFDM) to bear the communicated information.

The invention provides a coherent signal detector for extracting analog and digital information from a received broadcast waveform, which can be an intermediate or RF frequency waveform. The waveform can have an in-phase component and a quadrature component. The detector can include a down converter for frequency and phase shifting the in-phase and quadrature components, thereby providing a recovered in-phase output and a recovered quadrature output. The recovered in-phase output generally has both analog and digital information therein, whereas the recovered quadrature output generally has digital information therein. The down converter can be responsive to a phase word for correction of recovered output phase. In addition, the phase word can include a frequency control word for compensating for frequency shifting in the down converter. Therefore, the phase word can be used to compensate for phase, frequency, or both. The signal detector also includes an integration circuit for integrating a portion of the recovered quadrature output over a first preselected time interval, thereby producing the phase word. It is preferred that the first preselected time interval be at least one digital time frame.

The signal detector also can include a signal conditioner. The signal conditioner can include an analog quadrature mixer that frequency shifts or phase shifts, or both, the received signal to produce outputs that are in phase quadrature to each other. In general, because the received signal is an analog signal, and the recovered in-phase and quadrature outputs are digital signals, the signal conditioner also includes an analog-to-digital converter for converting the analog signals into digital signals. The signal conditioner also can provide a low-pass filter coupled with the analog-to-digital converter for the filtering of the analog signals prior to digitization. The signal conditioner also can include an I/Q compensator which compensates for DC offsets, amplitude imbalances, phase mismatches, and combinations thereof.

The signal detector can have a received signal power detector for detecting a signal level representative of the received broadcast waveform power, thereby producing a power error signal. The received signal power detector can employ a square-law device for sensing the signal level. In general, the square-law device arithmetically squares the signal level, thereby producing a power value. The power detector also includes a power integrator for integrating the power value over a second preselected time interval, thereby producing the power error signal. The second preselected time interval is preferred to be at least one digital time frame. A gain control circuit can be used to maintain a gain control power signal within a predefined power range, in response to the power error signal.

In another embodiment according to the present invention herein, the coherent signal detector is similar in all respects to the first embodiment with the exception of the signal conditioner. The signal conditioner can optionally have a single analog mixer. The mixer receives the signal from the gain control circuit and frequency shifts or phase shifts, or both, to produce a signal output. The output is processed by a lowpass or bandpass (if undersampling is used) filter prior to conversion to a digital signal by an analog-to-digital converter. The digital signal is input to a quadrature digital down converter.

In another embodiment according to the invention herein, the coherent signal detector can include two serially-connected down converters. A signal conditioner similar to the previous embodiment also may be used. The first down converter can frequency shift the received waveform and produce in-phase and quadrature outputs. The second down converter can frequency and phase shift the in-phase and quadrature outputs, responsive to a phase word, thereby producing recovered in-phase and quadrature outputs. In this embodiment, an integration circuit can be connected to the second down converter for integrating a portion of the converted quadrature output over a first preselected time interval, thereby producing the phase word.

The invention will be more readily apparent to those skilled in the art by reference to the accompanying drawings wherein:

FIG. 1 is a diagram of an embodiment of the coherent signal detector according to the invention herein.

FIG. 2 is a diagram of a second embodiment of the coherent signal detector according to the invention herein.

FIG. 3 is a diagram of a third embodiment of the coherent signal detector according to the invention herein.

FIG. 4 is a diagram of a fourth embodiment of the coherent signal detector according to the invention herein.

This invention provides a coherent signal detector for extracting analog audio and digital information from a received broadcast waveform, which can be an intermediate or RF frequency waveform. In general, an AM-compatible digital audio broadcast (AM DAB) signal is sensed by a suitable radio-frequency receiver. The receiver converts the received AM DAB signal into a received broadcast waveform in which analog audio and digital information components are embedded, and provides this signal to a coherent signal detector according to the invention herein.

FIG. 1 is a block diagram of coherent signal detector 1 wherein receiver 2 detects received broadcast signal 4, having an AM carrier signal therein, and applies signal 4 to automatic gain control (AGC) circuit 6. Broadcast signal 4 can include an AM-compatible digital audio broadcasting signal which uses, for example, OFDM. AGC circuit 6 adjusts the power at AGC output 8 such that the power at AGC output 8 is maintained within a predefined power range. AGC circuit 6 is generally controlled by power error signal 7 from received power detector 12 that measures the power in the received broadcast signal 4.

AGC output 8 is received by I/Q signal conditioner 10. Within conditioner 10, in-phase (I') and quadrature (Q') signals are extracted from AGC output 8. Conditioner 10 can also compensate for DC offsets, amplitude imbalances, and phase mismatches that occur in the circuits that generate signals I' and Q'. Conditioner 10 also digitizes the aforementioned I' and Q' signals. As a result, conditioner 10 can produce conditioned in-phase (I') output 14 and conditioned quadrature (Q') output 16. However, conditioner 10 does not provide compensation to phase and frequency in order to lock them to the received AM carrier in received broadcast signal 4. Also conditioner 10 can provide at least one feedback signal 25 to detector 12 in order to give AGC circuit 6 a reference signal for gain control. Outputs 14 and 16 are input to quadrature digital down converter (QDDC) 18.

In general, QDDC 18 frequency and phase shifts I' output 14 and Q' output 16 from a first predetermined frequency to a second predetermined frequency thus resulting in recovered in-phase output signal 28 and recovered quadrature output signal 30. Although a frequency shift also can be performed for frequency alignment, the I' and Q' inputs to QDDC 18 may be very close to the desired frequency, in which case QDDC 18 may shift only phase so that in-phase and quadrature signals are in proper phase alignment with respect to the AM carrier signal. Although the first predetermined frequency can be an intermediate frequency, instead it may be an RF-band frequency. It is preferred that the second predetermined frequency be a baseband frequency. Q output signal 30 can be supplied to integration circuit 20 which integrates signal 30 over a first preselected time interval, which can be one digital time frame. Also, the preselected time interval can be an integral multiple of one digital time frame.

Integration circuit 20 can produce error signal 32 so that detector 1 can lock on to the phase and frequency of the AM carrier in received broadcast signal 4. If detector 1 has achieved both phase and frequency lock on the received AM carrier, the results of the integration should be approximately zero, because Q signal 30 contains primarily digital carriers whose frequencies are selected such that each carrier ideally integrates to zero over the duration of a preselected time interval of integration. It is preferred that the preselected interval be one data frame time, although an integral multiple thereof can be used.

If detector 1 is not in lock, some of the AM carrier signal and some of the transmitted I signal will be present in Q output signal 30. When these signals are integrated over the duration of the first preselected time interval, they may not integrate to zero and can be used to generate an error signal 32, which can be added in summer 26 with frequency control word 24, to produce phase word 34. Phase word 34 can be fed back to QDDC 18 and used to drive detector 1 into phase and frequency lock with the received AM carrier signal in signal 4. Frequency control word 24 is preferred to be a fixed value that represents the nominal frequency shift applied by QDDC 18.

In FIG. 2, coherent signal detector 51 illustrates another embodiment of the invention herein. Receiver 52 detects received broadcast signal 54, having an AM carrier signal therein, which is input into AGC circuit 56. Broadcast signal 54 can include an AM-compatible digital audio broadcasting signal which uses, for example, OFDM. AGC circuit 56 maintains AGC output 58 generally within a predefined power range using power error feedback which is preferred to be gain error signal 126. Signal conditioner 60 can receive AGC output 58 and generate at least one feedback signal 125a,b which is used by received power detector 62 to control AGC circuit 56.

In one embodiment of the present invention, received power detector 62 can include square-law device 122 and power integrator 124. However, any component that measures power in received signal 54 may also be employed. Device 122 squares and then sums each of signals 125a,b and provides the result to power integrator 124 for low-pass filtering. Integrator 124 produces gain error signal 126 which is used by AGC circuit 56 to maintain the power at AGC output 58 within the predefined power range. It is preferred that power integrator 124 integrate the output of device 122 for a second preselected time interval, which is preferred to be one digital time frame. Although signals 125a,b are shown as the input signals to power detector 62, input signals to detector 62 can also include AGC output 58; mixer outputs 95, 97; filter outputs 101, 103; I/Q compensator outputs 64, 66; QDDC outputs 78, 80; or a combination of these signals.

Similar to signal conditioner 10 in FIG. 1, signal conditioner 60 in FIG. 2 can extract I and Q signals from AGC output 58, and compensate for DC offsets, amplitude imbalances, and phase mismatches. However, conditioner 60 does not provide compensation to phase and frequency in order to lock them to the received AM carrier signal in received broadcast signal 54.

Conditioner 60 converts AGC output 58 into conditioned in-phase (I') output 64 and conditioned quadrature (Q') output 66. AGC output 58 can be received by first signal mixer 90 and second signal mixer 92 for signal separation into in-phase (I) and quadrature (Q) components, respectively. Mixers 90 and 92 can be used in conjunction with first cosine signal generator 86 and first sine signal generator 88, respectively, to convert the frequency of the respective I and Q signals to an intermediate frequency. Local oscillator 91 controls the frequency of generators 86, 88 but is not used to phase or frequency lock detector 51 to the AM carrier signal in received signal 54. In general, the frequency of local oscillator 91 is offset from the frequency of the received AM carrier in signal 54. Oscillator 91 can be a general purpose analog oscillator that may not produce a suitably stable signal. In the embodiment exemplified in FIG. 2, phase and frequency lock can be performed by QDDC 68 and proportional-and-integral (P-I) circuit 70.

The outputs of mixers 90, 92 can be received by low pass filters 94, 96, respectively, so that undesired frequency components produced by mixers 90, 92 can be minimized. In addition, low pass filters 94, 96 may also act as anti-aliasing filters for signal conditioning prior to signal conversion by analog-to-digital (A/D) converters 98, 100, respectively.

In one embodiment of the present invention, it is preferred that the output of A/D converters 98, 100 provide feedback signal 125 to received signal power detector 62. In addition, signals 64, 66 from I/Q compensator 102 could be used as inputs to detector 62, in place of inputs 125a,b. The outputs of A/D converters 98, 100 are received by I/Q compensator 102 which compensates for DC offsets, amplitude imbalances, and phase mismatches which may arise from other components associated therewith.

I' output 64 and Q' output 66 can be received by QDDC 68 to produce in-phase output 78 and quadrature output 80 by frequency shifting outputs 64 and 66 from a first preselected frequency range, which may be an intermediate or RF-band frequency range to a second preselected frequency range which is preferred to be a baseband frequency range. QDDC 68 also can rotate the phase of outputs 64 and 66, by a process commonly called carrier rotation. In general, the signals 64, 66 are represented as (I'+jQ'). In order to shift signals 64, 66 in frequency by .omega..sub.0 and in phase by .phi., to produce output S(.omega..sub.0,.phi.) where S=I+jQ, QDDC 68 implements:

Signal 84 can be representative of (.omega..sub.0 t+.phi.).

Q output signal 80 can be supplied to frame interval integrator 128 for integration of the Q signal 80 over the first preselected time interval, which is preferred to be one digital time frame.

Similar to the error generation section of integration circuit 20 in FIG. 1, an error generation circuit, which can be P-I circuit 70, can produce error signal 84, so that detector 51 can lock on to the phase and frequency of the AM carrier signal. If detector 51 has achieved phase and frequency lock with the AM carrier, the output of integrator 128 generally should be zero, because Q output 80 contains only digital carriers, the frequency of which are such that each carrier integrates to essentially zero over the duration of one preselected time interval. The first preselected time interval is preferred to be one digital time frame. If detector 51 is not in phase and frequency lock, signal 80 will not integrate to zero over the duration of one digital time frame.

Error signal 129 can be applied to first proportional gain generator 130 which produces first proportional error signal 82. Similarly, signal 129 is supplied to integral gain generator consisting of signal summer 134 and gain circuit 132, the output of which is error signal 83. Gain circuits 130, 132 can be used to select the bandwidth of the loop that locks onto the phase and frequency of the AM carrier signal in received signal 54. First signal summer 76 sums frequency control word 74, first integral error 82, and second integral error signal 83 to produce phase word 84. Frequency control word 74 can be a fixed value that represents the nominal frequency shift applied by QDDC 68. Phase word 84 can be applied to signal generators 104, 106, 108 for the demodulation of signals 64, 66, and can be used to provide phase and frequency lock of detector 51 with the AM carrier signal in signal 54. Generators 104 and 108 can be the same device, and are shown as two devices in FIG. 2 for ease of drawing. Generators 104, 106, and 108 may be table look-up type of circuits that generate the cosine and sine signals.

In another embodiment of detector 251 according to the invention herein, as shown in FIG. 3, mixer 252 has one input signal 253 from AGC 255 and one output 256 to A/D converter 257. A low-pass filter 258 can be interposed between mixer 252 and A/D converter 257. Signal 253 is converted in frequency to an IF frequency which may be higher or lower than the desired carrier. The frequency conversion by mixer 252 can be used to, for example, reduce the frequency of the received signal 253 so that A/D converter 257 can sample signal 256 at an appropriate rate. The digitized output 265 from A/D converter 257 can be provided to QDDC 266, which can extract the desired in-phase component 259 and quadrature component 260. In yet another embodiment of detector 251, mixer 252 would not be used. Instead, signal 253 from AGC 255 could be provided directly to A/D converter 257, or if used, to filter 258, which may be a bandpass filter, prior to digitization by A/D converter 257. Although signal 265 is shown as the input signal to power detector 262, input signals to detector 262 can also include AGC output 253, mixer output 256, A/D converter output 265, and QDDC outputs 259, 260, or a combination of these signals. QDDC 266 can be configured to accept the single digitized signal 265 and extract signals 259, 260 therefrom. Phase word 275 is used to drive QDDC 266 into phase and frequency lock with received signal 253. Signal 276, circuit 268, signal 269, circuit 277, frequency control word 278, and phase word 275 in FIG. 3 are similar to signal 80, circuit 128, signal 129, circuit 70, frequency control word 74, and phase word 84, respectively in FIG. 2.

In FIG. 4, yet another embodiment of detector 400 is disclosed. Received signal 401 can be input into mixer 402 and then into filter 430 followed by A/D converter 403. Alternatively, mixer 402 may be eliminated and received signal 401 may be input to filter 430 (which in this case may be a bandpass filter), and digitized directly by A/D converter 403. From converter 403, digitized program signal 404 can be received by QDDC1 405 where signal 404 is shifted in frequency to produce intermediate in-phase (I') and quadrature (Q') signal component 406 and 407, respectively. QDDC2 408 receives signals 406 and 407, and performs a frequency shift and a carrier rotation, or phase shift, on each of signals 406, 407 to produce respective desired in-phase and quadrature components 409, 410. QDDC2 408 may perform only a phase shift if signals 406, 407 are at the desired frequency.

Alternatively QDDC1 405 could be implemented using analog components and instead would be a "quadrature down converter" (QDC). Here, at least one A/D converter such as A/D converter 403 can be interposed between QDC 405 and QDDC2 408. Similar to circuits 268, 277 and 278 in FIG. 3, circuits 428, 420 and 422 maintain phase and frequency lock as desired values for signals 409, 410.

While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limited to the scope of the invention which is to be given the full breadth of the following claims and any and all embodiments thereof.