Method and Apparatus for Frequency Generation in a Synchronous System

The invention relates generally to clock circuits and more specifically to circuits for interfacing subsystems having different timing characteristics and tolerances.

In communications systems, such as those for broadcasting, teleconferencing, computer networking, etc., various kinds of modulation techniques are used. Use of these modulation techniques typically requires the availability of precise and accurate modulation frequencies. With the advances of integrated circuit technology, it is increasingly popular for communication systems to apply digital techniques for data/signal processing and data transmission. Therefore, the ability to generate accurate frequencies in synchronous digital systems is essential.

Different modulation standards stipulate greatly different accuracies for modulation frequencies. For example, in telecommunication systems, the frequency of system clocks is typically constrained by international organizations such as CCITT to have errors of no more than 0.01 percent, whereas system clocks of, for example, graphics systems for Personal Computers (PCs) may be in error by as much as 0.25 percent without violating relevant specifications.

With regard to terminology, an "accurate" clock is one that possesses a specified, nominal frequency, and a "stable" clock is one that does not vary in frequency over time, for example, despite temperature fluctuations in a circuit. The terms "accurate" and "stable" will sometimes be used in a relative sense to mean "more nearly accurate" and "more nearly stable," respectively.

There are applications in which a synchronous system with inaccurate clock frequency needs to communicate to another system that requires a predefined accurate and stable signal frequency. An example of such an application is the display of computer graphics onto standard television sets. As mentioned above, in a PC graphics system, the system clock need not be very accurate (system clocks can be off by as much as 0.25 percent). In contrast, a standard television set typically expects a subcarrier frequency that is accurate and stable to better than 100 parts per million (i.e., 0.01 percent). Hence, it is desirable to have a technique that can generate an accurate and stable signal frequency in a system with an inaccurate system clock frequency while maintaining system synchronization. In particular, it is desirable that the generated signal be synchronous with the system clock.

It is apparent that it would be impractical to try to derive any accurate signal frequency directly from an inaccurate system clock. However, if an accurate and stable reference frequency is available, then techniques and systems exist which can derive an accurate and stable frequency based on the reference clock while remaining synchronous with the inaccurate system clock. One such system is found in the "Chrontel CH7001 VGA to NTSC/PAL Encoder" integrated circuit product (CH7001), Chrontel, Inc., San Jose, Calif.

FIG. 1 illustrates at a high level the clock generator of prior art systems similar to the system in the Chrontel CH7001 product. The clock generator includes a clock measuring circuit 10 that produces a system clock measurement Nr 15. The system clock measurement Nr 15 is a digital value, and is provided to a P:Q ratio counter 20 that generates, in response to Nr 15 and a system clock 25, an output clock signal 30 of output frequency Fo. The output frequency Fo is related to the system clock frequency Fs by the equation:

wherein Q is a constant parameter of the P:Q ratio counter 20 and:

As Equation 1 shows, the P:Q ratio counter produces an output clock whose frequency Fo is a function of the system clock frequency Fs and the parameter P, where P is the system clock measurement Nr. The P:Q ratio counter is explained in more detail below in the detailed Description of Specific embodiments.

The clock measuring circuit 10 includes a system counter 35, which receives the system clock signal 25 and counts a predetermined number Ns 40 of transitions therein to delimit a test time period using a timing signal 45. A reference counter 50 receives and counts transitions in an accurate, stable reference clock signal 55 (typically, a crystal-based clock signal) of frequency Fr during the test time period. At the end of the test time period, the output 60 of the reference counter 55 is latched into a buffer 65 to be provided as the system clock measurement Nr 15 to the P:Q ratio counter 20. A controller 70 is coupled to control operation of the system counter 35, the reference counter 50, and the buffer 65. The controller 70 may be coupled (not shown) to receive the system clock signal 25 or the reference clock signal 55, depending on its design.

The relationship between Ns, Nr, Fs, and Fr of the clock measuring circuit 10 is given by:

which represents the test time period, Ns*(1/Fs), multiplied by Fr, the number of reference clock periods per second. Combining Equations 1, 2, and 3 gives: ##EQU1## Equation 4 shows that, since Ns, Q, and Fr are well-defined, accurate and stable values, an accurate and stable Fo is generated. Furthermore, a desired Fo can be realized simply by choosing appropriate values of Ns and Q, given Fr. Note that typically, Fr >Fo. Note also that the value of Ns may be switched during operation to cause a new output frequency Fo to be produced by the system, even though the system has but a single reference clock frequency Fr.

Most importantly, the output clock frequency Fo can be realized regardless of the system clock frequency Fs. If the system clock signal is inaccurate but stable, then the system works well. Even if the system clock frequency Fs slowly drifts over time, the clock measuring circuit 10 will update the system clock measurement 15 to maintain a generally correct output frequency Fo (provided that the drift is slow in relation to the test time period).

It is important to note that the system clock measurement Nr 15 should change only in response to actual drifts in the system frequency Fs or to a change in the value of system parameter Ns. Fluctuation in the value of Nr caused by any other reason translates into an undesired shift in the value of the output frequency Fo, and therefore constitutes a type of instability in the output clock signal 30. For example, if within a stream of successive test time periods, the system clock measurement Nr were to fluctuate for one test time period, then, referring to FIG. 2, the actual output clock frequency 200 would also fluctuate by an amount .DELTA.Fo 210 for one test time period 220 from the steady, nominal frequency Fo(nom) 230. In consequence, if Fo is used as the modulation signal frequency of a communication system, a fluctuating output clock frequency Fo would be interpreted as "noise" in the receiver.

Unfortunately, Fs and Fr are not synchronous, and there will be some finite but small errors between the counts of the system counter 35 and the reference counter 50. The result of this error will introduce a fluctuation in Nr.

The present invention provides apparatus and method for deriving an accurate clock frequency from an accurate reference clock in a synchronous system driven by an inaccurate system clock in a way that greatly reduces noise caused by the asynchronicity between the reference clock and the system clock.

A system according to the in invention comprises a measuring circuit and a ratio counter. The measuring circuit receives and processes the system clock signal and produces a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. In one embodiment of the invention, the system further includes a lock-on unit for inhibiting jitter in the system clock measurement, thereby inhibiting noise in the output clock signal. Rather than always updating the system clock measurement, the lock-on unit receives and compares portions of the system clock measurement and a latest system clock measurement and selectively causes the measuring circuit to update the system clock measurement only if certain jitter-inhibiting criteria are met.

In another embodiment of the invention, the system comprises a system counter, a reference counter, a ratio counter, and a synchronizing controller. The system counter receives the system clock signal and counts a predetermined number of signal transitions therein to delimit a test time period. The reference counter receives a reference clock signal and counts transitions therein during the test time period to produce a measurement, referred to as the system clock measurement, that is indicative of the system clock period. The ratio counter receives the system clock signal and the system clock measurement and generates the output clock signal. The synchronizing controller, in enabling the system counter and the reference counter, enables them within a time window of each other, wherein the time window is half of a clock period of a higher-frequency one of the system clock signal and the reference clock signal. In this way, jitter is inhibited in the system clock measurement, and noise is thereby inhibited in the output clock signal.

In a preferred embodiment of the invention, both a synchronizing controller and a lock-on unit are used. In this embodiment, if the system clock frequency Fs is stable, though perhaps inaccurate, then noise due to the asynchronicity between the system clock and the reference clock will be completely eliminated.

A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.

FIG. 1 illustrates a prior art system for producing an output clock signal in a system driven by a system clock;

FIG. 2 illustrates noise in an output clock signal caused by a fluctuation in the system clock measurement;

FIG. 3 is a block diagram of one embodiment of the present invention, which embodiment includes a synchronizing controller;

FIG. 4 illustrates the output clock signal generated by a P:Q ratio counter, which is a component of the prior art of FIG. 1 and of the present invention of FIGS. 3 and 6;

FIG. 5A is a timing diagram illustrating the function of the synchronizing controller of FIG. 3;

FIG. 5B is a block diagram of an example implementation of the synchronizing controller;

FIG. 6 is a block diagram of a second embodiment of the present invention, which embodiment includes a lock-on unit; and

FIG. 7 is a flow chart illustrating the logic implemented in the lock-on unit of FIG. 6.

FIG. 8 is a block diagram which illustrates the clock generator as part of a system which converts VGA computer display signals into NTSC or PAL video signals.

FIG. 3 is a block diagram of a clock generator 300 according to one embodiment of the present invention. The clock generator 300 includes a clock measuring circuit 310 that produces a system clock measurement Nr 315 which is provided to a P:Q ratio counter 320 for use in generating, in response to a system clock 325, an output clock signal 330 of output frequency Fo.

The P:Q ratio counter 320 is a circuit known in the art for realizing Equation 1. The implementation shown in FIG. 3 comprises an adder 335 whose multi-bit output 340 is applied to its input through modulo-Q registers 345, which are clocked with the system clock 325. The adder's other input is the multibit system clock measurement Nr 315, also called P. At each system clock period the previous content of the modulo-Q registers 345 is incremented by P until overflow occurs at the value Q. The next value will then be the previous value plus P modulo Q. Therefore, the output clock signal 330 resembles, as shown in FIG. 4, a time discrete quantized sawtooth signal 400 whose period 1/Fo 405 is determined by parameter P 410 according to Equation 1, repeated herein:

Referring to Equation 1, if the system clock were accurate and therefore its frequency Fs known, then constant values for P and Q could simply be chosen by hand to generate a desired output frequency Fo. However, in situations in which the system clock Fs is inaccurate and therefore its frequency not precisely known in advance, circuitry such as the clock measuring circuit 310 of FIG. 3 is used to produce a value for P which is proportional to 1/Fs, the system clock period. As discussed in the Background section, a well-defined and accurate output frequency can thereby be assured, according to Equation 4 (Fo=Ns*Fr/Q), regardless of the actual system clock frequency Fs.

One final note about the P:Q ratio counter is that in a specific application, the contents of modulo-Q register 345 can be used to address a Read Only Memory (ROM) (not shown) containing a predefined wave characteristic, thereby producing a numerical representation of a sampled (at Fs) predefined waveform. Sine and cosine ROMs are exemplary.

Still referring to FIG. 3, the clock measuring circuit 310, as in the prior art, includes a system counter 360 which receives the system clock signal 325 and counts a predetermined number Ns 355 of transitions therein to delimit a test time period. The clock measuring circuit is shown as a digital counter 360 coupled to a digital comparator 365, which produces a timing signal 367 after Ns transitions are counted. However, those of ordinary skill in the art understand that other circuits could be used to implement the same functionality of delimiting the test time period.

A reference counter 370 gives a measurement of the test time period according to an accurate, stable reference clock of frequency Fr. The reference counter 370 of FIG. 3 may be a counter which receives and counts transitions in a reference clock signal 375, which is an oscillating clock signal (e.g., from a crystal oscillator). However, those of ordinary skill in the art understand that there are other circuits for implementing a measurement-giving reference counter. To cite a nonlimiting example, the reference counter 370 may be a subtraction circuit which takes the difference of digital reference clock readings from the end and the start of the test time period, thereby counting the transitions. In any case, at the end of the test time period, the output 380 of the reference counter 370 is provided as the system clock measurement Nr 315 to the P:Q ratio counter 320. In the implementation of FIG. 3, a buffer 385 is used to provide the system clock measurement NR 315. For other implementations of the reference counter, a buffer may be part of the reference counter itself. The clock measurement Nr 315 may be provided to the P:Q ratio counter 320 with all digits at once, or in stages via circuitry such as a multiplexor (not shown). The output of the reference counter may be referred to as the "latest" or the "new" system clock measurement.

Unlike the prior art, the invention shown in FIG. 3 uses a controller which is a synchronizing controller 390, which is coupled to receive the system clock signal 325 and the reference clock signal 375. One way in which the synchronizing controller 390 differs from the prior art is that the synchronizing controller 390 will start the test time period, by enabling the system counter 350 and the reference counter 370, only when the system counter 350 and the reference counter 370 can be started within a certain time window of each other. Starting the two counters closely in time in this way limits spurious differences in the system clock measurement Nr 315 from one test time period to the next. In particular, differences caused by ordinary fluctuation of the phase relationship between the system clock signal 325 and the reference clock signal 375 are limited. The particular way in which the synchronizing controller 390 enables the two counters is described below.

FIG. 5A is a timing diagram illustrating the function of the synchronizing controller of FIG. 3. In FIG. 5A, a "slow clock" signal 510 depicts whichever one of the system clock signal and the reference clock signal has lower frequency. A "fast clock" signal 512 depicts the other, higher-frequency, clock signal. The system counter and the reference counter are individually referred to as the "fast counter" or the "slow counter" based on their corresponding clocks' frequencies. A timing signal 514 indicates the end of a test time period and causes the synchronizing controller to enter a disable cycle 516. During the disable cycle, the synchronizing controller disables the slow counter synchronously 518 (i.e., on an edge) with the slow clock signal and disables the fast counter synchronously 520 with the fast clock signal. Then, the synchronizing controller enters an update cycle 522 in which it updates 524 the system clock measurement with the output of the reference counter. Next, the synchronizing controller enters a reset cycle 526, as indicated in FIG. 5A by a reset signal 528, to reset both fast and slow counters to zero. Because the counters have been disabled, they may be reset asynchronously. Finally, the synchronizing controller enters an enable cycle 530 in which it enables both fast and slow counters according to the algorithm below.

In the enable cycle, prior to which both counters have been disabled, the synchronizing controller first enables the slow counter, but only when the fast clock signal is low 532 and the slow clock signal has a rising edge 534. The synchronizing controller will ignore any earlier rising edge(s) 536 in the slow clock signal which do not have the correct phase relationship with the fast clock--i.e., rising slow-clock edge(s) which occur when the fast clock is high 538. After the slow counter has been enabled, the synchronizing controller will enable the fast counter on the next rising edge of the fast clock signal 540. Therefore, each counter is enabled on its clock's rising edge, and each counter is enabled within 1/2 Fs time 542 of the other.

The above counter-enabling algorithm results in a maximum time difference of 1/2 Fs period between the enablement of the two counters and ensures that the two counters 350 and 370 receive clock signal pulses that are of constant widths. In this way, the synchronizing controller prevents timing violations and glitching of the clocks. This is important because, otherwise, timing violation or glitches could cause miscounts which either increase or decrease the proper system or reference counter values, resulting in unstable Fo.

Those of ordinary skill in the art will be able to build the synchronizing controller as described by FIGS. 3 and 5A and the above description. One implementation of the synchronizing controller 390 is depicted in FIG. 5B as a nonlimiting example. A synchronizer circuit A 550 is coupled to receive the timing signal 514 and in response disable the slow counter synchronously 518 with the slow clock signal 510. The synchronizer circuit A 550 next instructs a synchronizer circuit B 554 to disable the fast counter synchronously 520 with the fast clock signal 512. The synchronizer circuit A 550 also enables a cycle counter 552. The cycle counter 552 causes a synchronizer circuit C 556 to update 524 the system clock measurement. The cycle counter 552 next instructs a synchronizer circuit D 558 to reset 528 both fast and slow counters to zero. The cycle counter 552 next waits for the desired phase relationship to arise between the slow clock signal 510 and the fast clock signal 512, as described earlier in connection with FIG. 5A. At the proper time, the cycle counter 552 causes synchronizer circuits A 550 and B 554 to enable the slow and fast counters, respectively.

The synchronizing controller reduces sources of "Nr noise" in the system. Unfortunately, Fs and Fr are not synchronous, and in consequence there will still be some finite but small errors between the counts of the system and reference counters. The result of these errors will introduce a fluctuation in Nr. If the synchronizing controller is employed, Nr will fluctuate at most by one count from its steady-state value during periods when Fs is stable--i.e., not drifting.

FIG. 6 shows an embodiment 600 of the present invention which includes a lock-on unit 610 that further suppresses "Nr noise." The system of FIG. 6 is substantially similar to the system of FIG. 3, except for the lock-on unit. The lock-on unit suppresses "Nr noise" by introducing a hysteresis in the update of a system clock measurement Nr 615. If, at the end of a test time period, the absolute value of the difference between the content 620 of a reference counter 625 and the system clock measurement Nr 615 is one (1) or less, then the system clock measurement Nr will not be updated and will retain its current value. If the absolute value of the difference is greater than 1, then the lock-on unit 610 generates an update signal 635. If the absolute value of the difference is zero, then it does not matter whether the update signal is generated. In summary, the update signal is suppressed if the absolute value of the difference is no more than a window size, (e.g., one) and no less than a minimum suppression value (e.g., one or zero, depending on whether the update is generated if the difference is zero). Of course, if the minimum suppression value is zero, then the lock-on unit need not actually check the absolute value of the difference (nonnegative) against the minimum suppression value.

In a preferred embodiment of the present invention, the controller 650 is a synchronizing controller as described above in relation to FIG. 3. Note that if a synchronizing controller is used, then the (synchronizing) controller 650 should be coupled (not shown) to receive the system clock signal 655 and the reference clock signal 660. However, the lock-on unit is useful even with a controller according to the prior art (FIG. 1) which lacks the features of the synchronizing controller.

In applications for which Fs is not only inaccurate, but also fluctuates (e.g., Fs is generated from a phase-locked-loop that is jittery), it is possible that the hysteresis window would need to be set wider, e.g., to a value of two (2) instead of one (1) as discussed above.

Furthermore, by taking advantage of the fact that spurious fluctuations in Nr are bounded to a value of 1 once Nr reaches its "steady-state" value (assuming a synchronizing controller), only a number m of least significant bits of the content of the reference counter 625 and the m least significant bits of the system clock measurement 615 need to be compared. Setting m to be less than the full word length of the reference counter 625 would introduce only a minor penalty in the length of the time required for Nr to reach its steady-state value. In exchange, there could be a significant hardware savings because the word length of the reference counter 625 and the buffer 640 which holds the system clock measurement Nr 615 tends to be quite long in practice (typically 20 bits or longer). Allowing an update to occur if the contents of the two counters are equal will help to reduce the time for Nr to reach its steady-state value. In short, a portion of the content of the reference counter 625 and the system clock measurement 615 are compared, wherein the portion may be all or less than all available bits. In practice, setting m equal to two gives good results. The above hysteresis lock-on technique allows Fo to be not only accurate but also stable without fluctuations.

FIG. 7 is a flowchart which illustrates the lock-on logic described above. Those of ordinary skill in the art will have no trouble building a lock-on unit to implement the above lock-on logic. For example, a lock-on unit might be built using a digital comparator, a buffer to hold the hysteresis window size, and simple control logic. The hysteresis window size could be a programmable parameter, set for example, by a computer program, dip switches, user input, etc.

FIG. 8 is a block diagram which illustrates the clock generator as part of a system 800 which converts computer video signals into television signals. The depicted system is similar to Chrontel's CH7001 product, and uses the present invention's clock generator. The datasheet "CH7001 VGA to NTSC/PAL Encoder," Rev. 1.4, Mar. 26, 1996, from Chrontel Inc., is hereby incorporated by reference. In FIG. 8, the system 800 accepts analog RGB (Red/Green/Blue) signals 810 and synchronization signals 811 from a standard VGA computer display source, such as a Personal Computer (not shown), and converts them into NTSC or PAL video signals. Three analog-to-digital converters 812 receive and digitize the analog RGB inputs 810 on a pixel-by-pixel basis. A programmable vertical filter 814 then receives the digitized RGB inputs and performs 3-line vertical filtering to eliminate vertical flicker. Next, a scan rate converter 816 transforms the VGA horizontal scan-rate to either NTSC or PAL scan-rates. A color space converter 818 encodes the processed RGB signal into luminance (Y) and color difference (U, V) signals. The resulting YUV signals are filtered through digital filters 820 to minimize aliasing problems. A digital encoder, described below, then receives the filtered signals and transforms them into composite and S-video signals 822. Three digital-to-analog convertors 824 convert the composite and S-video signals 822 into analog outputs Y 826 (luminence), C 828 (chrominance), and composite 830.

The digital encoder comprises a blanking horizontal and vertical synchronizing signal (H/V-sync) generator 832, a blanking color-burst controller 834, a phase-locked loop (PLL) 836, and a sine and cosine generator 840. The H/V-sync generator 832 produces and inserts horizontal and vertical synchronizing signals into the composite and S-video signals 822. The blanking color-burst controller 834 controls the timing of inserting color subcarrier signals into individual lines of the composite and S-video signals 822. The PLL 836 generates system clocks, including a VGA pixel clock which is generated internally, using the horizontal sync input H 842. The sine and cosine generator 840 includes the clock generator described above (not pictured). The clock generator takes as input one system clock signal 844 and produces an output clock signal (not pictured) of an output frequency which is suitable for NTSC or PAL. The output clock signal is then used, as described earlier, to address and thereby sample ROMs containing values of sine and cosine. The sampled sine and cosine values are used to form the subcarrier signals used in encoding the composite and S-video signals 822. The clock generator uses an oscillator 846 to provide a reference clock signal.

Although the foregoing has been a description of the preferred embodiment, this description is intended to be illustrative of the invention, not limiting of it. The scope of the invention is defined by the appended claims.