US 5,873,126 AGrant
Memory Array Based Data Reorganizer
Issue Date:1999-02-16
•8 Claims
•2 Drawing Sheets
Abstract
Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules. The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.
Metadata
Assignee
- International Business Machines Corporation
Inventor
- Shanker Singh
Application Information
Application Number:US 9024093
Filing Date:1997-07-29
Priority Date:1995-06-12
Art Unit:271
Classifications
IPC:
G06F 1202
Field of Search:
7115;207;202;220;115;165;153
Patent Drawings (2 sheets)
Description
Background and Summary of the Invention
This invention relates to memory devices, particularly to memory devices that can reorganize the data by permuting rows or columns or both. It may be composed of plural memory modules viewed by the processor as a single, nonseparable store. More particularly, it relates to addressing such memory devices such that the processor can selectively modify the address to each module.
The invention provides a memory capable of formatting data before returning it to a processor or writing it back into memory by rearranging rows and columns of data stored in the memory. This is performed faster than a processor can manipulate the same data. The invention can be viewed as altering table structures semantically. It is useful especially in relational database management and uses hardware logic that is independent from the processor so that database management operations can be efficaciously executed off-line, replacing the software that normally performs such operations. It also provides the capability to mask certain data for security reasons, e.g., does not supply data that a user is not authorized to access.
The available techniques for relational database management require several memory accesses to retrieve requested data. The more fields in a record and the more dispersed the requested fields, the more memory read cycles required.
The prior art shows memory arrangements that can modify the data inside the memory per se using logic operations that can be performed without first retrieving the data and then having to restore the result.
U.S. Pat. No. 3,157,778 shows a memory that transfers data from register to register within the memory device and is capable of operating on information within the memory device, e.g., read and increment and return to the same or several registers. Apparently, the memory capacity can be changed by increasing or decreasing the number of registers or the number of storage positions in each registers. The construction is directed to cryogenic techniques.
U.S. Pat. No. 3,247,489 show a memory in which logical operations are performed on data within the memory device without having to retrieve the data. The results can be transferred to external devices, returned to memory, or both. The circuits, disclosed as cryogenic, can simultaneously read, perform a logic operation, and write data by using more than one read and sense line per cell.
U.S. Pat. No. 3,500,341 teaches semiconductor memory stages that perform storage or logical functions. It uses transistor bistable circuits in monolithic arrays and is arranged so that one of the transistors will pass a signal if the other transistor is turned off.
U.S. Pat. No. 3,593,304 teaches a memory that performs logical operations by combining two or more words in a single memory location. Each byte position includes a gate connected to different pairs of adjacent byte lines and produces a signal on one conductor when the signal level on the other exceeds a predetermined value. The byte wires are arranged so the signals add linearly and create carries or propagates via threshold gates, i.e., majority logic gates for each bit position.
U.S. Pat. No. 3,699,534 discloses cellular arithmetic array memories acting as multiprocessors. The invention relates to logic circuits for operating on words while stored in the memory. The circuits can read out, write in, or increment, e.g., an address, during each clock cycle.
U.S. Pat. No. 4,823,257 teaches a processor coupled to several so-called smart memories, i.e., including small scale arithmetic-logic units, which act as coprocessors that prepare data for the processor. By performing such operations--different ALU operations from the host's--and being linked by common intermediate language codes, the number of accesses to a memory is reduced. The results are translated back to intermediate code for the processor. The common intermediate language appears to be the crux of the invention.
For performing simple, low level logical operations on stored data, the prior art is satisfactory. The prior art, however, does not teach the rearrangement of data, using dynamic memory modification under processor control so that a single read (or write) operation that can retrieve (or store) fields of different records from each module even though stored at different addresses.
The invention provides fast retrieval from relational database memories since the addresses can be modified to do in a single memory read that which presently requires several memory reads. It is especially useful in database systems as the systems increase in size and capability.
In accordance with the invention, a memory is made up of several modules addressed as a single unit. Each module has circuits to modify its address selectively. The data read or written at the addressed locations can be selectively rearranged.
Since the registers controlling the address modification logic can be set by the processor in order of magnitude or two faster than a memory cycle, a plurality of selected fields can be accessed in one memory cycle vice several accesses, one for each field at a different address.
Brief Description of the Drawing
The invention is described in detail by referring to the various figures which illustrate specific embodiments of the invention, and wherein like numerals refer to like elements.
FIG. 1 is a logic block diagram of a memory system employing the invention.
FIG. 2 is an illustration of the functional operation of a memory system according to the invention.
Description of the Preferred Embodiment
The invention is a memory system with a plurality of storage modules, each having an independent input address. The actual address to each memory module is a combination of the address supplied from a computer or other utilization device and preset address modification registers. The utilization device can rapidly set the address modification registers. The address modification can be separately controlled for each memory module.
The retrieved data can be supplied to a system bus or regenerated, i.e., written back into the memory. The retrieved data can also be rearranged before supplied to a system bus or being regenerated. The reading process rearranges both rows and columns of data.
In FIG. 1, a plurality of memory modules 101A, 101B, . . . , 101N (collectively 101) have address input terminals and data access terminals. In a read mode (controlled by a R/W signal), data accessed from addressed locations in each memory module is made available at the data access terminals. In a write mode, data at the data access terminals can be rewritten at addressed locations, either at the same address from which it was retrieved or at a different address. For illustrative purposes, the memory modules are shown as having four address input terminals which can address sixteen memory locations in each module. The illustrated embodiment can be expanded to any desired size of memory module and to any number of memory modules.
The input signals to the address terminals of the memory modules 101 are supplied by an address and control bus via Exclusive-OR (XOR) gate networks 109A, 109B, . . . , 109N (collectively 109).
The other input signal to each of this exclusive-OR gates 109 is supplied from address modification registers 105A, 105H, . . . , 105N (collectively 105). The contents of the address modification registers 105 are set from the address and control bus 103 and controlled by decoders 107A, 107B, . . . , 107N (collectively 107). A decoder may be an AND gate having as input signals a unique combination of signals and an activating signal from the address and control bus 103.
Prior to addressing the memory modules 101, the address modification registers are set by supplying the modification data and the control signals via the bus 103. The register groups 105 can be set individually or several at a time depending on the width (number of lines, each conducting the value of one bit) of the address and control bus 103.
When the memory modules 101 are addressed to access (read or write) data, addressing signals from a computer or other utilization device are supplied via the address and control bus 103 to the exclusive-OR gates 109 and gated or inverted by the contents of the address modification registers 105 to supply modified address signals to the memory modules 101.
Data retrieved from the memory modules can be written back into the memory from the data access terminals or from memory registers 117. An illustration of the usefulness of rewriting rearranged retrieved data is shown in FIG. 2. The operation is illustrated using letters to represent record fields.
In FIG. 2, each of four memory modules 201A, 201B, 201C, and 201D, have sixteen addressable locations specified by four address bits. Initially, the modules store the letters A through H in locations 0000 to 0111.
As an example, it is desired to store at address 1000 a sequence of records represented by the letters HEAD. Instead of eight memory cycles to read out and to rewrite each separate record, the invention permits setting the address modification registers 205A, 205B, 205C, and 205D (collectively 205) to values which will be exclusive-ORed with a supplied memory address.
The sequence of operations starts by setting the address modification registers 205. The address modification register 205A which modifies the address to the first memory module 201A is set to a value 1111. The second address modification register 2059, which modifies the address to the second memory module 205B, is set to 1100. The third and fourth address modification registers 205C and 205D are set to 1000 and 1011, respectively.
Next, the memory is addressed with a supplied address of 1000, which when exclusive-ORed with the contents of the address modification registers 205 results in an address input of 0111 to the first memory module 201A, 0100 to the second memory module 201B, 0000 to the third memory module 201C, and 0011 to the fourth memory module 201D.
From the first module, an H is retrieved since 1000 (the supplied address) exclusive-ORed with 1111 (contents of the first address modification register 205A) is 0111, the address of record H. From the second, third, and fourth memory modules, E, A, and D are retrieved, respectively. The data access terminals therefore register HIFAD.
The next step resets the address modification registers to 0000 which can be done with a special reset control line or by writing 0000 into each address modification register.
The memory is then addressed again with 1000, and the retrieved data is written to location 1000.
A second cycle of operations can be performed to read FADE into location 1001 by setting the address modification registers to 1100, 1001, 1010, and 1101 in order and supplying an address of 1001. The preceding sequence of operations is then executed to place FADE in location 1001.
As previously noted, the data can be written into the memory from data registers 117 (FIG. 1).
Data from the memory modules 101 can be coupled to a memory data bus 115 and gated to the data registers 117A, 117B, . . . , 117M (collectively 117) via demultiplexors 111A, 111B, . . . , 111M (collectively 111). Demultiplexors (a.k.a. selectors) have a plurality of inputs, one of which is gated to the output terminals depending on the value of control input signals. There are M demultiplexors (and data registers) illustrated in FIG. 1 to show that the number need not equal the number of memory modules, N. Practically, however, M would equal N. Several demultiplexors in parallel, having the same control input signals, are coupled to the data bus 115 to pass an entire record to a data register 117.
For example, if each storage location in the memory modules 101 contain eight bits (byte) and there are four memory modules (205A-205D in FIG. 2), the data bus would be 32 bits wide. Each of the data registers 117 would have eight latches. Eight parallel demultiplexors, each with four inputs and its output terminal coupled to one of the latches in a data register, would supply the data to the data register.
Each demultiplexor would have two control inputs to select which of its four input terminals would be coupled to its output terminal and gated into the data register latch.
The demultiplexors 111 are activated by signals on the address and control bus 103 to select the data read into the data registers 117 from the data bus 115.
By controlling the demultiplexors 111, the data of the example in FIG. 2 can be selectively rearranged. Setting the first demultiplexor to pass the third character (signals on the data bus 115 from a fourth memory module), the second demultiplexor to pass the fourth character, the third demultiplexor to pass the second character, and the fourth demultiplexor to pass the first character will set the data registers to DEAF. This has rearranged the rows. The data can then be rewritten into the memory or supplied to the system bus 135 for use by an external utilization device.
By precluding certain combinations of demultiplexor control signals, data can be masked.
The contents of the data registers 117 can be coupled via an interchange bus 119 to demultiplexors, one of which is a demultiplexor 121 that gates data into a shifter 129 from the interchange bus 119. Another is a demultiplexor 127 which couples data directly to a system bus 135. Others are a demultiplexor 123 and a demultiplexor 125 that couple data to an arithmetic-logic unit (ALU) 131 to manipulate retrieved data according to system operations and to output the result to the system bus 135. The data manipulation devices are those commonly utilized in a processing systems.
The system bus couples data between the memory system and a computer or other utilization device.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes and modifications in form and details may be made therein without departing from the spirit and scope of the invention according to the following claims.
Claims
What is claimed is:
1. A memory system comprising: a plurality of memory modules; an addressing means coupled to said plurality of memory modules, said addressing means supplying a separate address to each memory module for accessing a data element stored at said separate address; a plurality of modifier inputs, each modifier input corresponding to said each memory module; and a plurality of address modifying means, each address modifying means coupled between said each modifier input and said each memory module, and further coupled to said addressing means, said each address modifying means receiving said separate address from said addressing means, combining said separate address with said modifier input to generate a separate modified address, and supplying said separate modified address to said memory module for newly accessing a data element stored at said separate modified address, wherein said plurality of address modifying means subsequently receives a plurality of changed modifier inputs, generates a plurality of re-modified addresses, and provides each re-modified address to said each memory module for storing said each newly accessed data element at said each re-modified address.
2. The memory system in claim 1 further comprising a plurality of memory registers coupled to said plurality of memory modules, each memory register temporarily storing said newly accessed data element received from said each memory module at said modified address, said newly accessed data element subsequently written back to said each memory module at said re-modified address.
3. The memory system in claim 2 further comprising a data modifying means coupled to selectively receive data elements from said plurality of memory registers, said data modifying means selectively modifying said data elements and returning said selectively modified data elements to said plurality of memory modules to be stored at said re-modified addresses, thereby rearranging said data elements.
4. A memory system comprising: a plurality of memory modules; an address and control bus coupled to supply a separate address and a control signal to each memory module for accessing a data element stored at said separate address; a plurality of modifier registers, each modifier register corresponding to said each memory module and coupled to provide a modifier value; and a plurality of address modification circuits, each address modification circuit corresponding to said each memory module and coupled to receive said separate address from said address and control bus and to receive said modifier value from said modifier register, said each address modification circuit combining said separate address with said modifier value to generate a separate modified address, and supplying said separate modified address to said memory module for newly accessing a data element stored at said separate modified address, wherein said plurality of address modification circuits subsequently receives a plurality of changed modifier values from said modifier registers, generates a plurality of re-modified addresses, and provides each re-modified address to said each memory module for storing said each newly accessed data element at said each re-modified address.
5. The memory system in claim 4 further comprising: a data bus coupled to receive said data elements from and provide said data elements to said plurality of memory modules; and a plurality of memory registers coupled to store data elements selectively received from said data bus, each memory register corresponding to said each memory module and accessing said data element stored at said modified address.
6. The memory system in claim 5 further comprising a data modifier circuit coupled to selectively receive said data elements from said plurality of memory registers, said data modifier circuit selectively modifying said data elements and returning said selectively modified data elements to said plurality of memory modules to be stored at said re-modified addresses, thereby rearranging said data elements.
7. The memory system in claim 6 wherein said data modifier circuit further includes an arithmetic logic unit, a shifter, and a plurality of multiplexors, each multiplexor corresponding to said each memory register.
8. The memory system in claim 4 wherein said each address modification circuit further includes an address register coupled to said address and control bus through a decoder, and an exclusive-OR gate coupled to said address register and said modifier register.
Patent Citations (24)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3157778 | 1964-11-01 | Haynes | |
| US3247489 | 1966-04-01 | Sussenguth, Jr. | |
| US3500341 | 1970-03-01 | Proudman | |
| US3593304 | 1971-07-01 | Gardner et al. | |
| US3651475 | 1972-03-01 | Dunbar, Jr. et al. | |
| US3699534 | 1972-10-01 | Kautz | |
| US3812336 | 1974-05-01 | Bossen et al. | |
| US3897626 | 1975-08-01 | Beausoleil | |
| US4037215 | 1977-07-01 | Birney et al. | |
| US4408275 | 1983-10-01 | Kubo et al. | |
| US4461001 | 1984-07-01 | Bossen et al. | |
| US4511962 | 1985-04-01 | Machida et al. | |
| US4561072 | 1985-12-01 | Arakawa et al. | |
| US4773048 | 1988-09-01 | Kai | |
| US4823257 | 1989-04-01 | Tonomura | |
| US4835684 | 1989-05-01 | Kawai | |
| US4943947 | 1990-07-01 | Kobayashi | |
| US5086407 | 1992-02-01 | McGarity et al. | |
| US5138705 | 1992-08-01 | Lo et al. | |
| US5305443 | 1994-04-01 | Franzo | |
| US5317704 | 1994-05-01 | Izawa et al. | |
| US5479635 | 1995-12-01 | Kametani | |
| US5485588 | 1996-01-01 | Singh | |
| US5630097 | 1997-05-01 | Orbitz et al. |
Non-Patent Literature (1)
- Tong, "Memory Transfer at Arbitrary Byte Boundaries," IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6473-6475.