Uninterruptible Power Supply Providing Continuous Power Mainstore Function for a Computer System

The present invention relates to the data processing field, and more particularly, relates to an improved method for providing back-up power for system mainstore memory in a computer system and an uninterruptible power system (UPS) for a computer system providing a continuous power mainstore function.

Stand alone uninterruptible power systems (UPSs) have been used for a back-up solution on many known computer systems, such as some models of the IBM AS/400. As memory capacities of many computer systems grow, typical UPS hold-up times (around 15 minutes) can no longer support the time required to write the contents of the mainstore memory to a nonvolatile media, such as disk storage, for a controlled shut-down of many systems. The standard stand alone AC-to-AC UPS presently does not provide an effective power back-up solution for many computer systems with a large mainstore memory.

A need exists for an improved method for providing back-up power for system mainstore memory and an uninterruptible power system (UPS) for a computer system providing a continuous power mainstore function.

Important objects of the present invention are to provide an improved method for providing back-up power for a system mainstore memory and an uninterruptible power system (UPS) for a computer system providing a continuous power mainstore function; to provide such improved method and uninterruptible power system (UPS) substantially without negative effects and that overcome many disadvantages of prior art arrangements.

In brief, a method for providing back-up power for a system mainstore memory and an uninterruptible power system (UPS) for a computer or data processing system are provided. The computer or data processing system includes a system mainstore memory and a system power supply. The uninterruptible power supply (UPS) includes an AC output and a DC output, an inverter circuit, a battery and an interface to the system power supply. The inverter circuit supplies AC power to the AC output. The battery supplies DC power to the DC output and to the inverter circuit. The interface enables the inverter circuit to initially supply AC power to the system power supply via the AC output upon detection of a utility power loss and then, after a predetermined period of time, activates the DC output to supply DC power to the system memory via the system power supply, and disables the inverter circuit to stop the initial supply of AC power to the system power supply.

The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:

FIG. 1A and FIG. 1B are block diagram representations of a computer or data processing system of the preferred embodiment;

FIG. 2 is a functional block diagram illustrating state transitions of a power system including an uninterruptible power supply of the system of FIG. 1A and FIG. 1B;

FIG. 3 is a chart illustrating an exemplary connection definition for the uninterruptible power supply of the system of FIG. 1A and FIG. 1B;

FIG. 4A and 4B are charts illustrating an exemplary logical interface output definition for the uninterruptible power supply of the system of FIG. 1A and FIG. 1B; and

FIG. 5 is a chart illustrating an exemplary logical interface input definition for the uninterruptible power supply of the system of FIG. 1A and FIG. 1B.

Having reference now to the drawings, in FIGS. 1A and 1B, there is shown a computer or data processing system of the preferred embodiment generally designated by the reference character 100. As shown in FIG. 1A, computer system 100 includes a central processor unit (CPU) 101, a read only memory 102, a random access memory or system mainstore memory 104, a display adapter 106 coupled to a display 108. CPU 101 is connected to a user interface (UI) adapter 110 connected to a pointer device and keyboard 112. CPU 101 is connected to an input/output (IO) adapter 114 connected to a direct access storage device (DASD) 116 and a tape unit 118. CPU 101 is connected to a communications adapter 120 providing a communications function.

As shown in FIG. 1B, computer system 100 includes a power system generally designated by the reference character 148. The power system 148 includes an uninterruptible power supply (UPS) 150 connected to a system power control network (SPCN) interface 152 via a predetermined interface connector 154, such as a multiple pin connector or a 26 pin D-shell connector, and to a system power supply 156 that includes a continuously powered memory or mainstore (CPM) direct current (DC) voltage regulator 158.

The DC battery voltage output is fed into the power supply 156 via the 26-pin UPS external connector 154. The CPM voltage regulator 158 selectively receives a predetermined DC battery voltage output from the UPS 150, such as a +48 V or 24 V output of a UPS battery 162. The CPM voltage regulator 158 provides a set DC voltage output, such as +3.3 Volt output. The +3.3 V output of CPM voltage regulator 158 is used to keep the system memory 104 alive during the time CPM is required. The +3.3 V output of CPM voltage regulator 158 is applied to a first input of an OR function 160 connected to the system memory 104. A second 3.3 Volt input to the OR gate 160 is provided by the system power supply 156 typically supplying power to the system memory 104. Otherwise, the CPM voltage regulator 158 provides power to the system memory 104 in accordance with a feature of the preferred embodiment.

The uninterruptible power supply (UPS) 150 includes one or more batteries 162 selectively providing the predetermined DC battery voltage output to the CPM voltage regulator 158 via a switch 164 within the UPS 150. A DC-to-AC inverter circuit 166 and the switch 164 are operatively controlled by a control interface block 168 of the UPS 150. During normal operation, a utility AC input to the UPS 150 is coupled by an OR function 170 to an AC input of the system power supply 156. Upon detection of a utility power loss, the uninterruptible power supply (UPS) 150 for the data processing system 100 initially supplies AC power to the power supply 156 in the system 100 and then, after a predetermined period of time, stops supplying AC power, and instead supplies DC power to the system memory 104 via CPM voltage regulator 158 of the system power supply 156. Preferably, the system power control network (SPCN) 152 determines when the predetermined period of time of utility power loss has passed and then sends an Inverter Disable Command and a DC On Command to the UPS 150.

In accordance with the preferred embodiment of the power system 148, the 26-pin connector 154 has been defined with predetermined pin assignments as illustrated and described with respect to FIG. 3, and a signal interface to the UPS 150 has been defined to provide the CPM function as illustrated and described with respect to FIGS. 4A, 4B, and 5. The power system 148 is designed so that once the CPM control state is established by the system 100, all power can be removed from the system control circuitry. This makes all power from the UPS battery 162 available to memory 104. In addition, the power system 148 is designed so that its connecting cable connector 154 cannot be interrupted as a condition to turn on the DC output of UPS 150 via switch 164.

The external interface connector 154 is arranged to allow the use of the CPM voltage regulator 158 of the preferred embodiment with an external stand-alone uninterruptible power supply UPS configured for use with this interface. Various commercially available systems can be used for computer system 100, for example, an IBM personal computer or similar workstation can be used when provided with the power system 148 of the preferred embodiment.

Referring to FIG. 2, there is shown a functional block diagram illustrating state transitions of the uninterruptible power supply 150 and the system 100. As indicated at a block 201 in state 1, the system 100 and UPS 150 is completely unpowered and inverter 166 disabled, occurring at installation and any time utility power is removed after the system 100 is powered off. Restoration of utility power causes a transition to state 2 as indicated at a block 202.

In state 2 at block 202, the UPS 150 has applied AC power to the system 100 with the system 100 turned off and inverter 166 disabled. State 2 at block 202 is the normal powered off state of the system 100. If a utility power failure occurs at state 2 at block 202, the system 100 returns to state 1 at block 201 as shown at line UTILITY LOSS, the inverter 166 is not started, the DC output is not turned on, and the system 100 loses AC power. When the system is turned on in state 2 at block 202, a transition to state 3 as indicated at a block 203 is provided as shown at line SYSTEM ON.

State 3 at block 203 is the normal powered on state of the system 100 and the UPS 150 is on with the inverter AC and battery DC outputs of UPS 150 turned off with the inverter 166 enabled. When the system 100 is turned off in state 3, the transition to state 2 is provided as shown at line SYSTEM OFF DISABLED. When a utility power failure occurs at state 3 at block 203, which is signaled by a UPS utility failure signal, it causes a transition to state 4 as indicated at a block 204 shown at line UTILITY LOSS. In state 4, the system 100 is on and the UPS provides AC power to the system 100 with the inverter circuit 166 while the DC power from UPS 150 is off. If the utility power returns within a predetermined time period, for example within 30 seconds while in state 4 at block 204, the transition to state 3 is provided as shown at a line UTILITY RETURNS. If the utility power is not restored within the predetermined time period, the system 100 makes a transition to either state 1 at block 201 or a state 5 as indicated at a block 205. The system 100 makes a transition as shown at a line SYSTEM OFF DISABLED to the state 1 at block 201 when conditions require a power off disabled so that the DC output will not be started. Otherwise when conditions permit a power off enabled, the system 100 makes a transition as shown at a line SYSTEM OFF ENABLED to the state 5 at block 205 where the UPS DC power is turned on and applied to the CPM regulator 158 of the power supply 156.

In state 5 at block 205, the inverter circuit 166 is off so that no AC power is provided to the system 100 and the interface signals are controlled by pull down resistors as in state 1 at block 201. The UPS 150 shuts down its logic to maximize the energy available to the system 100 with the DC output providing power to maintain the contents of the system memory 104. Restoration of utility power in state 5 at block 205 causes a transition to state 6 as indicated at a block 206 shown at line UTILITY RETURNS. In state 6 at block 206, the UPS 150 powers on and applies AC power to the system 100. Since the system 100 may remain off indefinitely, state 6 may exist indefinitely. The DC output of UPS 150 is maintained active to keep the system memory 104 powered. In state 6, UPS 150 maintains the DC output by utilizing the restored utility power for charging the battery 162. No transition state exists between state 5 and state 6 because the system power control network interface 152 determines that CPM is enabled in state 6 and the DC on interface signal is maintained in its default active state so that the UPS 150 does not turn off the DC output to CPM regulator 158. If a utility power failure occurs in state 6 at block 206, system 100 makes a transition as shown at a line UTILITY LOSS to the state 5 at block 205.

The normal transition from state 6 to state 3 at block 203 results from a system power on operation as shown at a line SYSTEM ON. After the system 100 has successfully powered on and enabled the inverter circuit 166, the DC output is turned off and the memory 104 is powered by the normal operation of system power supply 156.

Referring to FIG. 3, connections for the 26-pin UPS external connector 154 are defined as follows in Table 1 below:

Referring to FIG. 4A, exemplary logical interface outputs 400 are shown as follows in Table 2:

Referring to FIG. 4A, exemplary logical interface status bit (1-3) outputs 410 providing encoded status to the system 100 are shown as follows in Table 3:

Referring to FIG. 500, exemplary logical interface status inputs 500 are shown as follows in table 4:

While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.