Global Parity Symbol for Interleaved Reed-Solomon Coded Data

1. Field of the Invention

This invention relates to electronic circuits for ensuring data integrity in data storage or data communication applications; in particular, this invention relates to minimizing the probability of miscorrection in applying error correction and error detection codes to data storage and data communication applications.

2. Discussion of the Related Art

Error correction and error detection codes have been used extensively in data communication and data storage applications. In a data communication application, data is encoded prior to transmission, and decoded at the receiver. In a data storage application, data is encoded when stored in a storage device, e.g. a disk drive, and decoded when retrieved from the storage device. For the present discussion, it is unnecessary to distinguish between these applications. Hence, although the remainder of this description describes a data storage-retrieval system, the principles discussed herein are equally applicable to a data communication application.

In a typical application of error detection and correction codes, data symbols are stored in blocks, which each include a selected number of special symbols, called check symbols. A symbol may consist of a single bit or multiple bits. The check symbols in each block represent redundant information concerning the data stored in the block. When decoding the blocked data, the check symbols are used to detect both the presence and the locations of errors and, in some instances, correct these errors. The theory and applications of error correction codes are described extensively in the literature. For example, the texts (i) "Error-Correcting Codes", Second Edition, by W. Wesley Peterson and E. J. Weldon, published by the MIT Press, Cambridge, Mass. (1972), and (ii) "Practical Error is Correction Design for Engineers", revised second edition, by N. Glover and T. Dudley, Cirrus Logic, Colorado, publisher (1991), are well-known to those skilled in the art.

In a typical application of error correction codes, the input data is divided into fixed-length blocks ("code words"). Each code word consists of n symbols, of which a fixed number k are data symbols, and the remaining (n-k) symbols are check symbols. (For convenience, in this description, such a code is referred to as an (n, k) code). As mentioned above, the check symbols represent redundant information about the code word and can be used to provide error correction and detection capabilities. Conceptually, each data or check symbol of such a code word represents a coefficient of a polynomial of order (n-1). In the error correcting and detecting codes of this application, the check symbols are the coefficients of the remainder polynomial generated by dividing the order (n-1) polynomial by an order (n-k) "generator" polynomial over a Galois field.sup.1. For an order (n-1) polynomial divided by an order (n-k) polynomial, the remainder polynomial is of order (n-k-1). Typically, in a data storage application, both the data symbols and the check symbols are stored.

During decoding, both data symbols and check symbols are read from the storage medium, and one or more "syndromes" are computed from the code word (i.e. the data and the check symbols) retrieved. A syndrome is a characteristic value computed from a remainder polynomial, which is obtained by dividing the code word retrieved by the generator polynomial. Ideally, if no error is encountered during the decoding process, all computed syndromes are zero..sup.2 A non-zero syndrome indicates that one or more errors exist in the code word. Depending on the nature of the generator polynomial, the encountered error may or may not be correctable. If the generator polynomial can be factorized, a syndrome computed from the remainder polynomial obtained by dividing the retrieved code word by one of the factors of the generator polynomial is called a "partial syndrome".

A useful measure for quantifying the difference between two binary words is the "Hamming distance", which is defined as the number of bit positions at which the two words differ. For example, the 4-bit words `0000` and `0010` have between them a Hamming distance of one since these words differ only at the second least significant bit. In the design of error correction codes or error detection codes, a measure "minimum distance" can be defined. The minimum distance is the minimum Hamming distance between valid code words. In such an error correction or detection code, if the valid code word and the retrieved code word have a Hamming distance between them which is less than the minimum distance, the probability is high that the retrieved code word results from errors occurring in the valid code word at the bit positions defining the Hamming distance between these words. Thus, in error correction codes, the decoder can resolve, with minimum risk of miscorrecting the retrieved code word, in favor of the valid code word having the smallest Hamming distance from the retrieved code word.sup.3. Of course, if the minimum distance is an even integer, ambiguity for error correction exists when a retrieved code word is the same Hamming distance from two or more valid code words. For an error correcting code with a minimum distance d, the numbers of errors which can be corrected and detected are ##EQU1## respectively. The concepts of the Hamming distance and the minimum distance can be extended to multi-bit symbols. In such an extension, the Hamming distance and the minimum distance are each expressed in symbol units. For example, if an error correction code using multi-bit symbols, the Hamming distance is defined as ##EQU2##

Here, the symbol .left brkt-bot.x.right brkt-bot. denotes the floor function of x. the number of symbol positions at which two code words differ. In such an error correction code, two code words differ by a distance of one, if they differ at one symbol position, regardless of the number of bit positions these code words differ within the corresponding symbols at that symbol position.

One goal in designing error correction and error detection codes is the selection of an appropriate minimum distance. In general, the minimum distance of an error correction code can be increased by increasing the number of check symbols in a code word. At the same time, however, increasing the number of check symbols in a code word increases both the complexity of the necessary decoding logic and the overhead cost (in terms of decoding time and storage space) associated with the additional check symbols. The capability of an error correction or detection code is sometimes characterized by the size of the maximum error burst the code can correct or detect. For example, a convenient capability measure is the "single error burst correction" capability, which characterizes the code by the maximum length of consecutive error bits the code can correct, as measured from the first error bit to the last error bit, if a single burst of error occurs within a code word. Another example of a capability measure would be the "double error burst detection" capability, which characterizes the error correction or error detection code by the maximum length of each error burst the error correction code can detect, given that two or less bursts of error occur within a code word.

A well-known class of error correcting codes is the Reed-Solomon codes, which are characterized by the generator polynomial G(X), given by:

where .alpha. is a primitive element of GF(2.sup.m) and, i and j are integers.

Because errors often occur in bursts, a technique, called "interleaving", is often used to spread the consecutive error bits or symbols into different "interleaves", which can each be corrected individually. Interleaving is achieved by creating a code word of length nw from w code words of length n. In one method for forming the new code word, the first w symbols of the new code word are provided by the first symbols of the w code words taken in a predetermined order. In the same predetermined order, the next symbol in each of the w code words is selected to be the next symbol in the new code word. This process is repeated until the last symbol of each of the w code words is selected in the predetermined order into the new code word. Another method to create a w-way interleaved code is to replace a generator polynomial G(X) of an (n, k) code by the generator polynomial G(X.sup.w). This technique is applicable, for example to the Reed-Solomon codes mentioned above. Using this new generator polynomial G(X.sup.w), the resulting (nw, kw) code has the error correcting and detecting capability of the original (n, k) code in each of the w interleaves so formed.

Another approach used in the prior art for error detection is the use of the cyclic redundancy check (CRC) symbols. Under this approach, a CRC checksum, which is the value of a polynomial function applied to the input data, is computed. This CRC checksum is transmitted or stored with the data and is recomputed at the receiver or when retrieved. If no error is encountered, the computed CRC checksum matches the retrieved or received CRC checksum. Otherwise, one or more errors exist in the data or the retrieved CRC checksum. Unlike error correction codes, the CRC checksum does not pin-point where the error or errors occur, and thus does not provide the capability for correcting errors.

In a practical implementation, the full error correction capability of an error correction code is often not fully exploited because the complexity of logic circuits required for error location and error correction can become prohibitive for a relatively small minimum distance. It is, however, desirable to exploit the full capability of error detection, even though the full capability of error correction is not exploited. Indeed, in some applications, the consequence of a miscorrection is extremely undesirable. In those applications, an error is merely flagged, so that some other error recovery procedures may take over. For example, in a disk drive application, during data read, noise may cause a transient error in the magnetic head mechanism. Such an error is best handled by re-reading the sector from which the error occurred, rather than by attempting to correct the faulty data. In such an application, the additional cost of exploiting the full capability of the error correction code may not be economically justified.

In accordance with the present invention, in an interleaved Reed-Solomon error correcting code, a method is provided for increasing the minimum distance in each interleave by including only a single global parity symbol. The method of the present invention includes the steps of: (a) receiving a plurality of data symbols; (b) computing, in each interleave, a code word including the data symbols and a plurality of check symbols, the check symbols being generated by a generator polynomial given by:

where .alpha. is a primitive element of GF(2.sup.m) and, i and j are integers; and (c) providing a global parity symbol GP associated with a syndrome S.sub.GP given by one of: ##EQU3## where .gamma..sub.0, .gamma..sub.1, . . . , .gamma..sub.w-1 are non-zero elements of a galois field GF(2.sup.m), and S.sub.(i+j+1)w.sbsb.0 and S.sub.(j-1)w.sbsb.0 are, respectively, the partial syndromes corresponding to (X+.alpha..sup.i+j+1) and (X+.alpha..sup.j-1) for interleave w.sub.0.

In accordance with one aspect of the present invention, the method provides check symbols of a Reed-Solomon code using a single generator polynomial:

In accordance with another aspect of the present invention, when the number w of interleaves divides (j+i+1), the global parity symbol GP can be computed over all interleaves using a single second generator function ##EQU4## Alternatively, when the number w of interleaves divides (j-1), the global parity symbol GP can be computed over all interleaves using a single second generator function ##EQU5## By computing the global parity symbol GP over all interleaves using a single second generator function, the amount of hardware used to generate global parity symbol GP is greatly reduced.

In one embodiment, the global parity symbol GP is computed as part of the Reed-Solomon error correction code word. For example, such a Reed-Solomon error correction code can be generator by the generator polynomial: ##EQU6##

When the global parity symbol GP is computed as part of the Reed-Solomon code word, if an error occurs with in the parity symbol GP, such error can be corrected using the error correction capability of the Reed-Solomon code.

The error correcting code of the present invention can be decoded by computing partial syndromes S.sub.j, S.sub.j+1, S.sub.j+2, . . . , S.sub.j+1, of the generator function and the syndrome S.sub.GP.

In one embodiment, the decoding circuit limits error correction to a single error burst of less than a predetermined number of symbols. In that embodiment, the Reed-Solomon error correcting code is 3-way interleaved. In accordance with the present invention, the Reed-Solomon error correcting code of that embodiment, estimates the syndrome S.sub.GP using the relation:

In another embodiment, a 3-way interleaved Reed-Solomon error correcting code generates a global parity symbol GP using a polynomial (X+.alpha..sup.v) , where v is an integer. In that embodiment, the syndrome S.sub.GP is estimated using the relation:

One advantage of the present invention over the prior art is that, in an interleaved implementation, the Hamming distance for each interleave is increased by one. In other words, the present invention increases the number of errors detectable in each interleave by one. The present invention achieves this increase in Hamming distance in each interleave by including a single global check symbol, rather than by including a check symbol in each interleave, as is required in the prior art.

The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.

1. Tables

Table 1 shows the 16 elements of the Galois field GF(2.sup.4) used in an embodiment of the present invention.

Table 2 shows the derivation of the logic equations for check symbol generation circuit 200 illustrated in FIG. 2.

Table 3 shows the logic equation for each of the bits in the results of multiplying a 4-bit data symbol .beta. to constants .alpha., .alpha..sup.2, and .alpha..sup.3, .alpha..sup.10, and .alpha..sup.11 respectively within the Galois field GF(2.sup.4) defined in Table 1.

Table 4 shows the logic equations for the next coefficients of syndromes S.sub.i (i=0, 1, and 2) in circuits 400, 430 and 460, as expressed in terms of input values d.sub.h and d.sub.1, and the previous values r.sub.ij (i,j=0, 1, and 2) of syndromes S.sub.i.

Tables 5a, 5b and 5c provide the physical locations of errors occurring in the respective one of interleaves 0, 1, and 2, in the present embodiment.

Table 6 shows the various error conditions in an interleave recognized by the present embodiment.

Table 7 shows the multiplicative inverses of the elements in the Galois field GF(2.sup.4) defined in Table 1.

2. Drawings

FIG. 1 shows an organization of a Reed-Solomon code used in one embodiment of the present invention.

FIG. 2 is a feedback shift register circuit 200 which is used for generating check symbols and which receives one data symbol per clock period.

FIG. 3 is a feedback shift register circuit 300 for generating check symbols and which receives two data symbols per clock period, in accordance with one embodiment of the present invention.

FIGS. 4a, 4b and 4c show respectively partial syndrome circuits 400, 430 and 433 for computing the coefficients of partial syndromes S.sub.0, S.sub.1, and S.sub.2 respectively.

FIG. 5 shows schematically a decoder 500 in accordance with the present invention.

FIG. 6 shows a burst limiter circuit 500 providing a 2-byte error pattern ERRPAT from the error patterns in each interleave and the error pattern corresponding to a global parity error.

FIG. 7 shows a schematic circuit for computing a global parity syndrome S.sub.GP2 based on an estimated global parity syndrome ES.sub.GP and a computed global parity syndrome S.sub.GP.

The present invention is illustrated by an implementation using 4-bit symbols in a Galois field GF(2.sup.4), which is defined by the following primitive polynomial over Galois field GF(2):

where x denotes a single bit.

Table 1 shows a zero and the 15 non-zero elements .alpha..sup.i of the Galois field GF(2.sup.4) so defined. In such a Galois field, the element .alpha. is known as a "primitive" element. Note that the Galois field GF (2.sup.4) generated by the above primitive polynomial is only one of the possible extended 4-bit Galois fields derivable from the Galois field GF(2), i.e. there is at least one other primitive polynomial that generates another extended Galois field GF(2.sup.4) different from the one shown in FIG. 1. However, in the remainder of this detailed description, any reference below to a GF(2.sup.4) Galois field is understood to refer to the GF(2.sup.4) Galois field tabulated in Table 1.

The present invention provides a global parity ("GP") symbol in conjunction with a w-way interleaved Reed-Solomon code. According to the present invention, the GP symbol is computed from a set of parity symbols which, in turn, are each computed from data and check symbols in a single interleave. In the present invention, the GP symbol is transmitted or stored with the Reed-Solomon code, either as part of the Reed-Solomon code or apart from the Reed-Solomon code. The parity symbols from which the GP symbol is calculated need not be transmitted or stored.

Conventionally, one example of a Reed-Solomon code having a minimum distance of 5 has a generator polynomial g(X), given by:

where X denotes a symbol.

As discussed above, based on the above generator function, a three-way interleave Reed-Solomon code having the same distance of 5 in each interleave can be obtained using a generator polynomial g'(X), which is given by:

Polynomial g'(X) would have a distance of 5 in each interleave, i.e. a maximum of two errors can be corrected and additional 3 errors can be detected in each interleave. Clearly, twelve check symbols are required under this approach to achieve the minimum distance of 5 in each interleave.

As will be demonstrated below, the present invention provides a single global parity symbol GP, in lieu of extra w check symbols of a w-way interleaved Reed-Solomon code, without reducing the minimum Hamming distance of each interleave in the resulting code word. Thus, for example, under the present embodiment, the total number of check symbols required to be stored or transmitted, including the GP symbol, would be reduced from twelve to ten, without affecting the minimum distance of 5 in each interleave. Equivalently, by incorporating only a single global parity symbol GP, rather than the number of check symbols equalling the number of interleaves, the present invention increases an interleaved Reed-Solomon code's Hamming distance in each interleave by one.

In general, for a w-way interleave implementation, in which the code word in each interleave is generated by the generator polynomial:

where .alpha. is a primitive element of GF(2.sup.m) and, i and j are integers, the global syndrome S.sub.GP can be provided by either: ##EQU7## where .gamma..sub.0, .gamma..sub.1, . . . , .gamma..sub.w-1 are non-zero elements of GF(2.sup.m) and S.sub.(i+j+1)w.sbsb.0 and S.sub.(j-1)w.sub.0 are, respectively, the partial syndromes for interleave w.sub.0 corresponding to (X+.alpha..sup.i+j+1) and (X+.alpha..sup.j-1). Further, the w-way interleaved code word can also be generated by a single generator polynomial:

In this instance, when the number of interleaves (i.e. w) divides either (j+i+1) or (j-1), one possible global parity syndrome S.sub.GP can be computed over all interleaves using a single second generator function ##EQU8## rather than a sum of individual syndromes from each interleave. Calculating S.sub.GP in this manner is possible because, according to remainder theorem, when w divides (i+j+1), then ##EQU9## is a factor of (X.sup.w +.alpha..sup.i+j+1). Likewise, if w divides (j-1), then ##EQU10## is a factor of (X.sup.w +.alpha..sup.j-1).

The global parity symbol GP may be computed as part of the code word, or outside of the code word. If the global parity symbol GP is computed as part of the code word, error occurring in the GP symbol can be corrected or detected, as in Reed-Solomon code word.

A three-way interleaved embodiment of the present invention is now described. In this embodiment, the check symbols and the GP symbol are computed using a generator polynomial g"(X), which is derived from generator polynomial g'(X) above.

g"(X) is defined as follows:

Polynomial g"(X) is obtained, in accordance with the present invention, by combining the generator polynomial:

with a second generator polynomial (X+.alpha.) over all interleaves. As discussed above, a global parity syndrome S.sub.GP can be computed from the second generator polynomial (X+.alpha.). This global parity syndrome S.sub.GP, as will be demonstrated below, can be used to estimate the coefficients of the partial syndrome related to (X.sup.3 +.alpha..sup.3). The expanded expression for polynomial g"(X) above is valid for the Galois field GF(2.sup.4) defined in Table 1 above. In the above GF(2.sup.4) Galois field, with 4-bit symbols and a three-way interleave, the number of symbols in each Reed-Solomon code word is provided by 3*(2.sup.4 -1)=45.

As discussed above, g"(X) can be viewed as a product of polynomials G.sub.1 (X) and G.sub.2 (X), which are defined as follows:

The present embodiment generates the global parity symbol GP outside of the Reed-Solomon code word. Using G.sub.1 (X) as the generator function for a Reed-Solomon error correcting code, the number of check symbols in the resulting error correcting code is 9, thereby leaving a maximum length data field of 36 data symbols, which fit into 18 bytes. Using G.sub.2 (X) to provide the global parity symbol GP, the check symbols corresponding to both polynomials G.sub.1 (X) and G.sub.2 (X) can simply be provided in 5 bytes (10 check symbols) following the 18 byte data field. In a computer having a byte-oriented memory organization, having the data, check and global parity symbols fit into an integral number of bytes is an advantageous arrangement because such arrangement minimizes the complexity due to byte alignment Of course, a shorter data field can also be used. For example, in one embodiment, only 16 bytes are provided in the data field.

In this embodiment, the global parity syndrome S.sub.GP (.alpha.) for polynomial G.sub.2 (X) is related to partial syndrome S.sub.3 (.alpha.) of polynomial g'(X) by:

where the syndromes S.sub.32, S.sub.31, and S.sub.30 are respectively the syndromes relating to factor polynomial (X+.alpha..sup.3) in each of interleaves 2, 1, and 0.

According to coding theory, in a w-way interleaved Reed-Solomon code, syndromes S.sub.jw.sbsb.o, S.sub.(j+1)w.sbsb.0, . . . ,

S.sub.(j+i)w.sbsb.0 in interleave w.sub.0 (w.sub.0 =0, 1, 2, . . . , w-1)

can be computed respectively from dividing the code word of each interleave by factor polynomials (X+.alpha..sup.j), (X+.alpha..sup.j+1), . . . , X+.alpha..sup.j+i). These syndromes are related, in a single error case, by the following equations:

Thus, in this embodiment, the values of S.sub.32, S.sub.31, and S.sub.30 can be estimated from partial syndromes S.sub.2w.sbsb.0 and S.sub.1w.sbsb.0, using the relation: ##EQU11## where E.sub.3w.sbsb.0 is the estimated value of S.sub.3w.sbsb.0. In fact, if any two of the quantities S.sub.32, S.sub.31, and S.sub.30 in partial syndrome S.sub.3 are found, the third quantity can be easily computed algebraically Because S.sub.GP (.alpha.) is related to S.sub.3 (.alpha.), by selecting as G.sub.2 (X) a factor of S.sub.3 (X) , further confidence in error detection is achieved by verifying the S.sub.GP (.alpha.) against an estimated ES.sub.i (.alpha.) which is computed from the ES.sub.iw.sbsb.0, according to the relation:

Of course, the global parity syndrome can also be computed as SGP(.alpha..sup.v), where v is any integer, S.sub.GP (.alpha..sup.v) and S.sub.3 (.alpha..sup.v) are related by:

In fact, the same data integrity assurance can be provided by a global parity symbol GP constructed such that it's syndrome S.sub.GP relates to S.sub.32, S.sub.31, and S.sub.30 through .alpha..sub.2, .alpha..sub.1 and .alpha..sub.0, where .alpha..sub.i (i=0, 1, 2) is any non-zero element of the same GF(2.sup.4):

Thus, polynomial g"(X) has a global distance of 5, representing a correction capability of one error in each interleave and the ability to detect two additional errors, using only ten check symbols. In this embodiment, since the global parity symbol GP is not included in the code word, the error correction code corresponding to generator polynomial g"(X) can be viewed as a concatenation of a Reed-Solomon code with 9 check symbols and a global parity symbol.

The error correcting code of the present invention, for example the error code corresponding to generator polynomial g"(X), maintains the same global distance as a corresponding Reed-Solomon code, while requiring less overhead storage and decoding than the corresponding Reed-Solomon code. The error correction code in this embodiment can correct a single burst error spanning four symbols (13 bits), and can detect a single burst error spanning six symbols (21 bits).

As discussed above, to achieve a predetermined level of performance, the full capability of an error correction code need not be implemented. Of course, to achieve a greater error correction capability, the decoding circuit necessary becomes increasingly complex. Thus, under the present invention, one is still free to apply engineering judgment to achieve varying degrees of error correction and detection capabilities, using circuits of commensurate complexities. For example, in the implementation to be described below, a burst limiting circuit limits the error correction span to three symbols (9 bits) and the error detection span to seven symbols (25 bits)..sup.5

FIG. 1 shows the organization a code unit 100 used in the present embodiment. Code unit 100 includes a 45 symbol combination of 4-bit data and check symbols of a three-way interleaved Reed-Solomon code 101, and a 4-bit "global parity symbol" 102. As shown in FIG. 1, three-way interleaved Reed-Solomon code 110 includes a data field 101 of 36 symbols, and nine check symbols labelled 111-119. In the present embodiment, only 16 bytes (i.e. 32 data symbols) of data field 101 are used. Code unit 100 can be used in numerous applications, e.g. as an ID block to identify a sector of a disk drive. In that application, an ID block is encoded in the format shown in FIG. 1 and written out to the disk drive. In a data retrieval operation, the ID block is read and decoded to verify that the intended sector is accessed. The check symbols in interleaved Reed-Solomon code 110 are computed over the 36 data symbols in data field 101. Global parity symbol 102 is appended to the end of interleaved Reed-Solomon code 101 and is computed over all 45 4-bit data symbols and check symbols of interleaved Reed-Solomon code 101. In this organization of Reed-Solomon code 110, interleave 2 is to the left of interleave 1, which is in turn left of interleave 0. Note that the last data symbol in data field 101 is always an interleave 0 data symbol.

In the present embodiment, to generate the check symbols in interleaved Reed-Solomon code 101, division by g"(X) is implemented as a cascade of two divisions: first by polynomial G.sub.1 (X) and then by polynomial G.sub.2 (X). A direct implementation of the division by G.sub.1 (X) can be achieved using a feedback linear shift register circuit, such as circuit 200 shown in FIG. 2. The operation of such a direct implementation of polynomial division can be found, for example, in Chapter 7 of the text "Error-Correcting Codes" referenced above. Circuit 200 receives one input data symbol on lead 201 per clock cycle.

In this embodiment, data to be stored, or data retrieved from the mass storage media, are packed in 8-bit bytes. Hence, an efficient check symbol generator is preferably one which operates from the packed bytes without incurring the overhead of unpacking the symbols. An example of such a check symbol generator is shown as shift register circuit 300 in FIG. 3. In shift register circuit 300, data to be stored or data retrieved from the mass storage media are provided two symbols (i.e. 8 bits) per system clock period. When all 36 data symbols are received into circuit 300, registers 301-309 contain the check symbols 111-119 respectively. The check symbols 111-119 are output two symbols at a time in the next five system clock periods, during which global parity symbol 102 continues to be computed. Global parity symbol 102 is output with the last check symbol 119.

However, since check symbol generation circuit 300 receives two input symbols per clock period to generate in shift registers 301-310 the ten check symbols 111-119 and 102, the content of each of shift registers 301-310 after each system clock period must be the same as the corresponding shift registers of feedback shift register circuit 200 (FIG. 2) after two clock periods. The derivation of the logic equations for check symbol generator circuit 300 follows from the requirement that check symbol generation circuit 300 after each system clock period is to be functionally equivalent to feedback shift register circuit 200 after two system clock periods. A derivation of the logic equations for the-input value for each of registers 301-310 is illustrated by Table 2.

Table 2 is a table showing the values f.sub.0, f.sub.1, and r.sub.0 -r.sub.9 in the feedback output terminals 321 and 322, and each of registers 301-310. Table 2 contains three rows labelled states 0-2 respectively. In state 0, the current values of check symbols 111-119 and 102 (i.e. r.sub.0 -r.sub.9) are shown held in registers 301-310. State 1 shows hypothetically, in terms of f.sub.0, f.sub.1, and r.sub.0 -r.sub.9, the values of feedback output terminals 321 and 322, and each of registers 301-310, after contributions by data symbol d.sub.h (i.e. bits I›7:4! of data byte I) to check symbols 111-119 and 102 are included. State 2 shows the values of feedback output terminals 321 and 322, and each of registers 301-310, after including the contributions to check symbols 111-119 and 102 by data symbol d.sub.1 (i.e. I›3:0! of the input data byte I). Feedback shift register circuit 300 transitions to state 2 from state 0 after one system clock period.

Feedback shift register circuit 300 operates in two phases. In the first phase ("phase 1"), indicated by the "shift" signal on node 333 at logic "zero" and during which the 36 data symbols are shifted into feedback shift register circuit 300 two symbols at a time, the values of the check symbols 111-119 and 102 are computed. In the second phase ("phase 2"), indicated by the "shift" signal on node 333 at logic "one", the check symbols 111-119 are shifted out of registers 301-309 two symbols at a time on nodes 331 and 332, while the contributions of check symbols 111-119 to check symbol 102 are computed. Finally, simultaneous with the output of check symbol 109 at node 331, check symbol 102 is output on node 332.

Feedback shift register circuit 300 is constructed in accordance with state 2 of Table 2. As shown in FIG. 3, the two input data symbols d.sub.h and d.sub.1 are provided on nodes 322 and 327. Data symbols d.sub.h and d.sub.1 are summed (i.e. exclusive-ORed) respectively with the output values r.sub.0 and r.sub.1 of registers 301 and 302 to yield feedback values (d.sub.h +r.sub.0) and (d.sub.1 +r.sub.1) on nodes 334 and 335. Prior to arrival of data symbols, registers 301-310 are each initialized to zero. In phase 1, AND gates 323 and 325 are "enabled", transmitting the values (d.sub.h +r.sub.0) and (d.sub.1 +r.sub.1) on nodes 334 and 335 to constant multipliers 336-321 in accordance with the logic operations of state 2 of Table 2. For example, the input terminals of feedback shift register 305 receive a value equal to (d.sub.h +r.sub.0)*.alpha..sup.11 +r.sub.6, by operation of multiplier 337 and exclusive-OR circuit 343. The input terminals of shift registers 302, 303, 306, and 308 are similarly provided with the values specified under state 2 of Table 2. In addition, shift registers 301, 304, 307 receives values r.sub.2, r.sub.5 and r.sub.8 respectively, each value representing a shift of two positions (i.e. division by X.sup.2). At the same time, the input values d.sub.h and d.sub.1 on nodes 322 and 327 are respectively provided, through multiplexers 330 and 329, to summers 345 and 346. At summer 345, the input value d.sub.h is exclusive-ORed (i.e. summed) with the value r.sub.9 in shift register 310. The summed value, i.e. d.sub.h +r.sub.9 is then multiplied by .alpha. at multiplier 347. The result of this multiplication is then summed at summer 346 with input value d.sub.1. The result of this summing at summer 346 is then multiplied by .alpha. at multiplier 348 to yield a value .alpha..sup.2 (d.sub.h +r.sub.9)+.alpha.*d.sub.1, which is provided as an input value to shift register 310, in accordance with state 2 of table 2.

In phase 2, the input values to multipliers 336-341 are zeroed, so that two shift register chains are formed. The first chain consists of shift registers 301, 303, 305, 307 and 309. The second chain consists of shift registers 302, 304, 306 and 308. Thus, at every system clock period, two check symbols are shifted out of registers 301 and 302 and provided on nodes 331 and 332 through multiplexers 330 and 329. At the same time, except for the last check symbol 119, the output check symbols 111-118, which are provided on nodes 331 and 332, are fed back to summers 345 and 346 for computation of the global parity symbol 102. When the last check symbol 119 is output 331, the control signal on lead 350 is asserted, so that the value at the output terminals of multiplier 347 is provided through multiplexers 328 and 329 to node 332 as global parity symbol 102. In this embodiment, global check symbol 102 results from the exclusive-OR of check symbol 118 and the value in shift register 310, multiplied by .alpha., at the time check symbols 117 and 118 are output at nodes 331 and 332. In a storage application, an error condition may exist which causes all symbols stored in the storage system to be zeroed. Under that error condition, as will be evident from the syndrome computation described below, the resulting syndrome coefficients become all zeroes, thereby masking the error condition. To avoid this error condition, the check symbols 110-119 and 102 can be stored bit-wise inverted. Upon data retrieval, i.e. during decoding, check symbols 111-119 and 102 are bit-wise inverted, prior to syndrome computation.

In feedback shift register circuit 300, multipliers 336-341 each multiply a 4-bit output value of either AND gate 323 or AND gate 325 to one of the factors .alpha..sup.3, .alpha..sup.10 and .alpha..sup.11. Also, multipliers 347 and 348 multiple, respectively, the output values of adders 345 and 346 by the factor .alpha.. Multipliers 336-341 can each be constructed out of multipliers which multiply a 4-bit data symbol .beta. to one of the constants .alpha., .alpha..sup.2, and .alpha..sup.3. To create the multipliers for multiplying the data symbol .beta. to the constants .alpha..sup.10 and .alpha..sup.11, the following identities in the Galois field GF(2.sup.4) of Table 1 are used:

Accordingly, 4-bit multipliers for multiplying .beta. to .alpha., .alpha..sup.2, .alpha..sup.3, .alpha..sup.10, and .alpha..sup.11 can be implemented from the logic equations shown in Table 3. Table 3 shows the logic equations which are used to construct each of the bits in the output value of these 4-bit multipliers over the Galois field GF(2.sup.4) defined above in Table 1, in which the bits .beta..sub.3 .beta..sub.2 .beta..sub.1 .beta..sub.0 represent the bits at bit positions 3, 2, 1, and 0, with bit 0 at the least significant position.

During a decoding operation, the partial syndromes S.sub.0, S.sub.1, S.sub.2 are computed in accordance with the equations for S.sub.i, i=0, 1, and 2 above. FIGS. 4a, 4b and 4c show respectively partial syndrome circuits 400, 430 and 460 for computing partial syndromes S.sub.0, S.sub.1, and S.sub.2.

Circuits 400, 430 and 460, similar to linear feedback shift register circuit 300 above, receive the same two data symbols d.sub.h and d.sub.1 per system clock period on leads 411 and 412, 441 and 442, and 471 and 472 respectively.

Accordingly, the logic equations for the next coefficients of partial syndromes S.sub.i (i=0, 1, and 2) in partial syndrome circuits 400, 430 and 460 are provided in Table 4. Table 4 expresses in terms of input values d.sub.h and d.sub.1, and the previous values r.sub.ij (i,j=0, 1, and 2), partial syndromes S.sub.i. In addition, Table 4 also shows the computation of S.sub.GP as a function of input data symbols d.sub.h and d.sub.1.

Thus, partial syndrome circuit 400 computes the coefficients S.sub.02, S.sub.01, and S.sub.02 of partial syndrome S.sub.0, partial syndrome circuit 430 computes the coefficients S.sub.12, S.sub.11, and S.sub.10 of partial syndrome S.sub.1, and partial syndrome circuit 460 computes the coefficients S.sub.22, S.sub.21, and S.sub.20 of partial syndrome S.sub.2. When all data symbols are received into partial syndrome circuits 400, 430 and 460, registers 401-403, 431-433, and 461-463 contains the coefficients S.sub.00, S.sub.01, S.sub.02, S.sub.10, S.sub.11, S.sub.12, S.sub.20, S.sub.21, and S.sub.22 respectively. Registers 401-403, 431-433, and 461-463 are initialized to zero prior to the arrival of any of the 36 data symbols of Reed-Solomon code 101. When the last check symbol (global parity symbol 102) is output, the input signals at 413, 443, and 473 are zeroed.

In practice, coding and decoding of data symbols do not occur simultaneously. For example, in a communication application, encoding is performed only during data transmission and decoding is performed only during data reception. Similarly, in a storage application, encoding is performed only when data are stored, and decoding is performed only during data retrieval. Thus, registers can be shared between the coding and decoding circuits. In this embodiment, registers 301-309 are also used as registers 401-403, 431-433, and 461-463.

Partial syndrome S.sub.GP (X) of the global parity check symbol 102 is computed using circuit 300. As explained above, to take advantage of the additional data integrity assurance of the Reed-Solomon code, the coefficients S.sub.30, S.sub.31, and S.sub.32 are estimated. The estimated coefficients, denoted ES.sub.30, ES.sub.31, and E.sub.32 are derived from S.sub.2w.sbsb.0, S.sub.1w.sbsb.0, and S.sub.0w.sub.0, where w.sub.0 =0, 1, and 2. The syndrome S.sub.GP of global parity check symbol 102 cannot be verified against an estimated S.sub.GP until check symbols 110-119 are computed. The syndrome S.sub.GP is stored in register 310 and provided on node 349 as .alpha.S.sub.GP. If no error is encountered, the final estimated partial syndrome ES.sub.GP should equal partial syndrome S.sub.GP, where ES.sub.GP is defined as:

A syndrome S.sub.GP2 is obtained by summing the estimated ES.sub.GP and S.sub.GP :

In this embodiment, S.sub.GP2 is implemented in hardware by the circuit represented schematically in FIG. 7. The input values ES.sub.3w.sbsb.0, (w.sub.0 =0, 1, and 2) in FIG. 7 are provided by a circuit 500 illustrated by FIG. 5 discussed below.

As mentioned above, to minimize hardware in one implementation, a burst limiting circuit, described below, is provided to limit error correction to within a 9-bit burst, or no more than one symbol error in each interleave.

Also, error location l.sub.w.sbsb.0 in interleave w.sub.0 is provided by the equation: ##EQU12##

To locate the physical location within the Reed-Solomon code 101, a value NIBBLE.sub.w.sbsb.0 is computed in each interleave w.sub.0 from error location l.sub.w.sbsb.0 :

This value NIBBLE.sub.w.sbsb.0 specifies the physical location of the data or check symbol where the error occurred. The value of NIBBLE.sub.w.sbsb.0 indicates the location of the error nibble, as measured from check symbol 111. For example, if the length of the data field is 16 bytes, and NIBBLE.sub.w.sbsb.0 has a value of -3, then the error occurs at the lower nibble of byte 15. Tables 5a, 5b and 5c show the physical error locations in each of interleaves 0, 1, and 2 respectively. Consequently also, a NIBBLE.sub.w.sbsb.0 value between 0-8 indicates an error occurring in one of the 5 check bytes in interleaved Reed Solomon code 110. If the negative value of NIBBLE.sub.w.sbsb.0 has a magnitude greater than twice the length of data field 101, then an out of range error has occurred.

FIG. 5 shows schematically a decoder circuit 500 for interleave w.sub.0 in accordance with the present invention. As shown in FIG. 5, partial syndromes S.sub.1w.sbsb.0, S.sub.2w.sbsb.0, and S.sub.0w.sbsb.0 are provided as input values to circuit 500. Circuit 500 provides as an output value a 7-bit output value of NIBBLE.sub.w.sbsb.0 (NIBBLE›6:0!) on bus 506, the error pattern S.sub.0w.sbsb.0 on 4-bit bus 507, the 4-bit error location ES.sub.3w.sbsb.0, and the expected 4-bit estimated partial syndrome ES.sub.3w.sbsb.0 on bus 509. The three estimated partial syndromes ES.sub.3w.sbsb.0 are combined (described below) to derive syndrome S.sub.GP. As mentioned above with respect to FIG. 7, when S.sub.GP is non-zero, the error pattern is given by:

where `+` denotes an "exclusive or" operation.

The value of NIBBLE.sub.w.sbsb.0 in the present embodiment is computed by a table look-up in circuit 520 using the value ##EQU13## on bus 521, which is computed in multiplier 522 as the product of the value S.sub.2w.sbsb.0 on bus 502, with the output value of inverse circuit 523. Inverse circuit 523 provides as output the multiplicative inverse of S.sub.1w.sbsb.0 in the GF(2.sup.4) Galois field defined in Table 1. Inverse circuit 523 implements a table look-up of multiplicative inverses. The multiplicative inverses of the elements in the Galois field GF(2.sup.4) of Table 1 are shown in Table 7. Multipliers 522 and 524 are 4-bit by 4-bit general purpose multipliers in the Galois field GF(2.sup.4).

The value ES.sub.3w.sbsb.0 is computed in multiplier 525 as the product of the value ##EQU14## and S2w.sbsb.0. In this embodiment, if S.sub.0w.sbsb.0, S.sub.1w.sbsb.0, and S.sub.2w.sbsb.0 are all zero (as determined by comparators 526, 527 and 528), or if S.sub.0w.sbsb.0 * S.sub.2w.sbsb.0 equals S.sub.1w.sup.2.sbsb.0, then it may be concluded that either no-error has occurred, or a correctable error has occurred in interleave w.sub.0. Any other condition signifies the occurrence of an uncorrectable error. In circuit 500, the value of S.sub.1w.sup.2.sbsb.0 is computed by squaring multiplier 525. Squaring multiplier 525 implements the following equation, for .beta.=›.beta..sub.3 .beta..sub.2 .beta..sub.1 .beta..sub.0 !, in the Galois field GF(2.sup.4) defined in Table 1:

Circuit 500 provides as output signals two error flags SYNOK.sub.w.sbsb.0 and ERR.sub.w.sbsb.0 for each interleave w.sub.0. SYNOK.sub.w.sbsb.o, when set, signals either (a) no error, or (b) a correctable error is detected in the interleave w.sub.0. When reset, SYNOK.sub.W.sbsb.0 represents occurrence of an uncorrectable error. These error conditions are summarized in Table 6. A global error control signal ERR is provided to indicate that an error is detected. The error control signal ERR is derived in the present embodiment by:

where denotes an "OR" operation.

In addition, a control signal ERRINGP is set when an error is detected in the global parity symbol. ERRINGP is derived by:

where denotes an "AND" operation.

The 4-bit error patterns ERRPAT0, ERRPAT1, and ERRPAT2 are provided by the equations:

Error patterns ERRPAT0, ERRPAT1 and ERRPAT2 are provided to derive the error patterns for error correction.

The present embodiment corrects a single burst error spanning no more than 3 symbols. Within interleaved Reed-Solomon code 101, the first error symbol in such a single error burst can occur in any one of the following six situations: (a) in interleave 2, at the lower nibble of a byte, with a 2-byte error pattern ERRPAT given by {0000, ERRPAT2, ERRPAT1, ERRPAT0}; (b) in interleave 2, at the upper nibble of a byte, with a 2-byte error pattern ERRPAT given by {ERRPAT2, ERRPAT1, ERRPAT0, 0000}; (c) in interleave 1, at the lower nibble of a byte, with a 2-byte error pattern ERRPAT given by {0000, ERRPAT1, ERRPAT0, ERRPAT2}; (d) in interleave 1, at the upper nibble of a byte, with a 2-byte ERRPAT error pattern given by {ERRPAT1, ERRPAT0, ERRPAT2, 0000}; (e) in interleave 0, at the lower nibble of a byte, with a 2-byte error pattern ERRPAT given by {0000, ERRPAT0, ERRPAT2, ERRPAT1}; and (f) in interleave 1, at the upper nibble of a byte, with a 2-byte error pattern ERRPAT given by {ERRPAT0, ERRPAT2, ERRPAT1, 0000}. In addition, if a single burst error is detected in global parity symbol 102, as indicated by error control signal ERRINGP, the error is correctable if no error is detected in interleave 0. In that case, the 2-byte error pattern ERRPAT is given by {0000, ERRPAT2, ERRPAT1, ERRPAT0}y. In view that an error in global check symbol 102 is correctable only if no error occurs in interleave 0, certain portions of the error correction data path can be shared between the error pattern ERRPAT0 in interleave 0 and the global check symbol's error pattern.

Any error within the burst limit of this embodiment can be corrected by locating the consecutive two bytes ERRBYTEA and ERRBYTEB at which the error occurs. To correct ERRBYTEA and ERRBYTEB, ERRBYTEA and ERRBYTEB are exclusive-ORed with the 2-byte error pattern ERRPAT. In this embodiment, errors other than the correctable errors enumerated above are not corrected.

FIG. 6 shows a burst limiter circuit 500 providing a 2-byte error pattern ERRPAT from the error patterns in each interleave and the error pattern corresponding to an error in global check symbol 102. As shown in FIG. 6, 4-bit error patterns ERRPATi from interleaves 0-2 and global error pattern S.sub.GP2 are received on 4-bit-busses 601-604 into burst limiter circuit 600. ERRPAT0 is bitwise-ORed with S.sub.GP2 to be used as an input value to four 4-bit 6:1 multiplexers 610-613. The other input data to the 4-bit 6:1 multiplexers 610-613 are ERRPAT1, ERRPAT2, and a constant value '0000. Multiplexers 610-613 are selected by control signals X0XX, 0XXX, X1XX, 1XXX, X2XX, and 2XXX. Control signal Xw.sub.0 XX ,w.sub.0 =0, 1 or 2, represents the condition in which the first error in a single error burst occurs in interleave w.sub.0 and at the lower nibble of a byte. Control signal w.sub.0 XXX, w.sub.0 =0, 1 or 2, represents the condition in which the first error in a single error burst occurs in interleave w.sub.0 and at the upper nibble of a byte. Of course, as discussed above, to take advantage that a correctable error in global check symbol 102 cannot occur simultaneously with an error in interleave 0 and which is an upper nibble of a byte, control signal 0XXX is also set when the global check symbol 102 contains an error.

The above detailed description is provided to illustrate the embodiments of the present invention, and should not be taken as limiting the scope of the present invention. Various modifications and variations within the scope of the present invention are possible. For example, even though the present invention is illustrated by operations in the Galois field GF(2.sup.4), one of ordinary skill would appreciate the principles of the present invention are equally applicable to Galois fields of other cardinalities. The present invention is defined by the following claims.