Method for Fabricating an SOI Substrate

1. Field of the Invention

The present invention generally relates to an SOI substrate and its fabrication method suitable for forming a silicon layer, having a thickness of about 1000 .ANG., atop the SOI substrate, on which a completely depletion-mode device can be fabricated.

2. Description of the Related Art

As compared with the method for fabricating integrated circuits on a bulk semiconductor substrate, the method of fabricating integrated circuits on a thin semiconductor layer which is deposited on an insulating layer has several advantages, such as superior device characteristics, and complete isolation between the devices. From this point of view, a structure called silicon-on-insulator (SOI) is, for example, configured with a single crystalline silicon layer formed on an insulating layer of SiO.sub.2, which overlies a single crystalline silicon substrate. By a silicon-wafer bonding method, the silicon layer provided with high-crystallization and any thickness at will can be achievable.

However, with respect to the SOI substrates formed by the wafer-bonding method, a key issue problem is how to form a silicon layer of uniform thickness by combining polishing with etching. A silicon layer having a thickness of about 0.1 .mu.m is used to fabricate completely depletion-mode metal-oxide-semiconductor field-effect transistors (MOSFET) thereon. Clearly, to decrease the threshold voltage V.sub.th variation among such MOSFET devices, it is important to precisely control the thickness of the silicon layer. Conventionally, plasma etching process has been utilized to control the uniformity of the silicon layer to a thickness of about 1000 .ANG. with a precision of .+-.50 .ANG.. However, if a decrease in the variation distribution of the threshold voltage V.sub.th in surfaces of the fabricated devices is required, it is necessary to further improve the planarization of the silicon layer. Therefore, the amount of time consumed and manufacturing cost of processing the silicon layer are greatly increased.

It is therefore an object of the present invention to resolve the aforementioned issues with which the prior arts are faced by providing an SOI substrate and its fabrication method. Even if the silicon layer formed atop the SOI substrate appears to be of non-uniform thickness, devices fabricated thereon have decreased threshold voltage variation in a surface of the substrate in particular.

For achieving above-identified object, the present invention provides a method for fabricating SOI substrate by bonding two semiconductor wafers via an insulating layer, wherein the doping concentration distribution of the silicon layer is locally varied corresponding to the thickness distribution.

Moreover, the silicon layer, according to the present invention, overlying the SOI substrate kept the threshold voltage of fabricated devices nearly constant by the fact that doping concentration of the silicon layer is locally varied corresponding to its thickness.

Accordingly, the threshold voltage of complete depletion-mode devices, such as SOI MOSFETs, fabricated on the SOI substrate depends on the doping concentration of the channel as well as the thickness of the silicon layer. Therefore, if the doping concentration of the channel is uniform, the threshold voltage reveals distribution variation corresponding to thickness distribution. In such a structure, according to the present invention, the doping concentration distribution corresponds to the thickness distribution locally, resulting in decreased threshold voltage variation even if there is distribution variation in thickness.

Other objects, features and advantages of the present invention will become apparent by way of the following detailed description of the preferred but non-limiting embodiment. The description is made with reference to the accompanying drawings, wherein:

FIGS. 1a-1e depict the process flow diagrams of fabricating an SOI substrate in accordance with the first preferred embodiment of the present invention in cross-sectional view;

FIGS. 2a-2c depict the process flow diagrams of fabricating an SOI substrate in accordance with the second preferred embodiment of the present invention in cross-sectional view; and

FIG. 3 depicts the threshold voltage distribution diagram of the fabricated SOI substrate.

Referring to FIGS. 1a.about.1e, the process flow diagram of an SOI substrate in accordance with the first embodiment of the present invention is depicted in cross-sectional view, wherein FIGS. 1b-1e are the partially expanded sectional views of the SOI substrate. As shown in FIG. 1a, oxidation to the surface of a wafer 1 forms an oxide layer 2 having a predetermined thickness. Then, the wafer 1 with the grown oxide layer 2 is bonded with another wafer 3 via the oxide layer 2 at room temperature. Those bonded wafers are thereafter subjected to thermal treatment to assure the bonding strength.

Then, as depicted in FIG. 1b, the surface of the wafer 1 is subjected to the sequential steps of polishing, plasma etching, and so on, to form and thin a silicon layer 4 to a predetermined thickness. As mentioned above, the thickness of the thinned silicon layer 4 reveals local distribution variation. After measuring the thickness by an ellipsometer, NANOSUPEKU (trademark name), t designates the maximum value of the measured thickness of the silicon layer 4; t-.increment.t represents the measured thickness of the maximum value t subtracted from its variation .increment.t. The doping concentration of the portion having thickness t designates N.sub.D.

Next referring to FIG. 1c, shield masks 5 formed of photoresist overlie portions of the silicon layer 4 that are thicker. Subsequently, as depicted in FIG. 1d, impurities are implanted into the silicon layer 4, through the shielding of masks 5, performed by an ion-implantor. Meanwhile, the implanted ions have the conductivity type same as that of the silicon layer 4. For example, if the silicon layer 4 is P-type, the implanted ions are acceptor impurities; if the silicon layer N-type, the implanted ions are donor impurities. The doping concentration of the implanted ions, relative to the portions of the silicon layer 4 having a thickness difference -.increment.t, appears as an increased doping concentration .increment.N.sub.D therein. Accordingly, the doping concentration is N.sub.D +.increment.N.sub.D while the thickness of the silicon layer 4 is t-.increment.t. The method for figuring the aforementioned N.sub.D +.increment.N.sub.D will be depicted in the following. The masks 5 are thereafter removed as shown in FIG. 1e. If required, damage recovery is done.

The relation among the maximum thickness t of the silicon layer 4, the doping concentration N.sub.D of the channel, and the silicon layer t-.increment.t associated with the doping concentration N.sub.D +.increment.N.sub.D is described below. When the gate voltage V.sub.g is applied at the threshold voltage V.sub.th, the potential energy of the silicon layer operated in completely depletion-mode is .PHI..sub.th,t, the charge density per unit volume is .rho., the dielectric constant of silicon is .epsilon..sub.Si, and the relative dielectric constant in vacuum is .epsilon..sub.o. The Poisson equations for the potential energy are given by ##EQU1## Because .rho.=qN.sub.D (q designates the electron charge and is kept constant), ##EQU2## For the same reason, .PHI..sub.th,t-.increment.t, t-.increment.t, and N.sub.D +.increment.N.sub.D have a relationship given by

For .PHI..sub.th,t =.PHI..sub.th,t-.increment.t given by equations (2) and (3),

An implanting dosage that satisfies equation (4) is applied to the silicon layer 4 during implanting. However, the solved N.sub.D according to equation (4) is merely an approximate value, and depends on device design including operating condition and process condition for fabrication device on SOI substrate. Hence, the solved doping concentration must operate in coordination practical conditions, and is somewhat adjusted for optimum.

In the first preferred embodiment, the doping concentration contained in the silicon layer is adjusted to overcome the problems arising from the thickness variation of the silicon layer that the conventional method encounters. Accordingly, the variation of the threshold voltage nearly approaches zero.

As depicted in FIG. 2, the process flow diagrams of an SOI substrate in accordance with the second embodiment of the present invention is depicted in cross-sectional view. After the bonded wafers are subjected to polishing and plasma etching to the predetermined thickness, similar to the first preferred embodiment, the thickness of the silicon layer is measured by predetermined spacing. In FIG. 2a, t designates the minimum value of the measured thickness of the silicon layer 4; t+.increment.t represents the measured thickness of the minimum value t added by its variation .increment.t. The doping concentration of the portion having thickness t designates N.sub.D.

As depicted in FIG. 2b, after clearly determining the thickness distribution of the silicon layer 4, shielding masks 5 formed of photoresist overlie portions of the silicon layer 4 that are thinner locally. Subsequently, as shown in FIG. 2c, impurities are implanted, through the masks 5 as shielding, into the silicon layer 4 by an ion implantor. Meanwhile, the portion of the silicon layer 4 with a thickness of t+.increment.t is provided with effective doping concentration (.vertline.N.sub.donor -N.sub.acceptor .vertline.) of a decreased difference of .increment.N.sub.D. The conductivity type of implanted impurities is opposite to that of the silicon layer 4. For instance, if the silicon layer 4 is P-type, the implanted impurities are donor ions; if the silicon layer 4 is N-type, the implanted impurities are acceptor ions. Then the masks are removed. If required, the SOI substrate is thereafter subjected to damage recovery treatment.

Moreover, after precisely controlling the thickness distribution of the silicon layer 4, the average thickness can be utilized as a criterion designated as t so as to vary the doping concentration based thereupon. At that time, the portion of the silicon layer 4 having smaller thickness than the average thickness t is doped with impurities of the same conductivity type as that of the silicon layer 4, and, furthermore, the portion of the silicon layer 4 having larger thickness than the average thickness t is doped with impurities of opposite conductivity type to that of the silicon layer 4.

FIG. 3 depicts the threshold voltage distribution diagram of the SOI substrate fabricated in accordance with the present invention, wherein cross-shaped symbols represent the measured results according to the conventional method, and circle symbols designate the measured results based upon the present invention. Depending on the thickness difference .increment.t, the associated doping concentration N.sub.D is adjusted to vary .increment.N.sub.D. As compared with either mechanical process or plasma etching process, the silicon layer 4 atop the SOI substrate appears a decreased threshold voltage variation. Similarly, the SOI substrate fabricated in accordance with the second preferred embodiment demonstrates the same results.

The threshold voltage of completely depletion-mode devices fabricated on the SOI substrate associates with the thickness of the silicon layer as well as the doping concentration of the channel region. Therefore, in accordance with the present invention, the local doping concentration is varied, depending upon the thickness difference of the silicon layer 4. Accordingly, the method for fabricating SOI substrate according to the present invention has the following effects:

(1) The threshold voltage of the fabricated completely depletion-mode devices has decreased variation, nearly approaching to zero. Therefore, high-quality SOI substrates can be acquired.

(2) Even though the polished silicon layer reveals inferior thickness variation, for example, about .+-.20%, the threshold voltage of the devices fabricated on the SOI substrate demonstrates decreased variation, thus reducing the manufacturing cost when using high-price plasma etching for planarization.

Alternative embodiments of the invention have now been described in detail. It is to be noted, however, that this description of these embodiments is also illustrative of the principles underlying the inventive concept. It is therefore contemplated that various modifications of the disclosed embodiments will, without departing from the spirit and scope of the invention, be apparent to persons of ordinary skill in the art, and the scope of the invention is intended to be limited only by the appended claims.