Voltage Regulator With Output Pull-Down Circuit

This application claims priority under 35 USC .sctn. 119 (e) (1) of provisional application number 60/040,183, filed Mar. 12, 1997.

This invention generally relates to electronic systems and in particular it relates to low dropout voltage regulators.

When the output current of a prior art low dropout (LDO), PMOS voltage regulator, as shown in FIG. 1, is changed rapidly, large transient output voltages can be induced at the regulator output. Usually the regulator can compensate for these transients and the output voltage can quickly recover before the transient voltages create problems in the system. However, in the case when a very large current load (hundreds of milliamps to several amps) is rapidly removed from a regulator, the output voltage can rise to dangerously high levels and remain high for a long period of time before returning to regulation. This high output voltage condition results when the output load current changes more rapidly than the amplifier can respond. For the period of time between the removal of the output current load and the appropriate response of the amplifier (the response time), the output voltage loses regulation. The gate of the output PMOS is still being held at a voltage level that can supply large currents to the load, but the load has been removed. The current that was previously going to the load begins charging the external load capacitor, C.sub.L, during the response time which forces the output voltage to rise. Once the amplifier has correctly responded to the change in the load current the output voltage of the amplifier is high enough to cut-off the output PMOS. With the output PMOS cut-off and the load current removed, the only current path available to discharge the high output voltage on C.sub.L is through the feedback resistors, R.sub.1 and R.sub.2. These resistors are usually high-valued resistors (to minimize the quiescent current of the regulator), and are only able to sink a few microamps of current. With only the resistor current available to discharge the load capacitor it can take hundreds of milliseconds for the regulator to return to regulation. The recovery time of the regulator can be improved by decreasing the size of the feedback resistors. However, to be effective, this solution requires decreasing the resistor values to the point where the quiescent current of the regulator becomes excessive.

Generally, and in one form of the invention, the voltage regulator circuit includes: an output transistor coupled between a voltage supply node and an output node; an amplifier coupled to the output transistor for controlling the response of the output transistor; feedback circuitry connected between the output node and the amplifier, the feedback circuitry providing feedback to the amplifier; and a pull-down circuit coupled to the output node.

In the drawings:

FIG. 1 is a schematic circuit diagram of a prior art low dropout, PMOS voltage regulator;

FIG. 2 is a schematic circuit diagram of a preferred embodiment low current, low dropout voltage regulator with voltage recovery circuit;

FIG. 3 is a schematic circuit diagram of the comparator shown in FIG. 2.

The prior art voltage regulator circuit of FIG. 1 includes amplifier A.sub.1 ; output PMOS transistor MP.sub.X ; load capacitance C.sub.L ; feedback resistors R.sub.1 and R.sub.2 ; resistance R.sub.ESR (R.sub.ESR is the equivalent series resistance of load capacitance C.sub.L); source voltage V.sub.CC ; reference voltage V.sub.REF ; load current I.sub.LOAD ; output voltage V.sub.OUT ; and feedback voltage V.sub.FB. FIG. 2 is a circuit schematic illustrating a preferred embodiment low current LDO output voltage recovery circuit constructed according to the teachings of the present invention. The circuit of FIG. 2 includes amplifier A.sub.1 ; comparator C.sub.1 ; PMOS transistors MP.sub.X and MP.sub.D ; capacitor C.sub.L ; feedback resistors R.sub.1 and R.sub.2 (feedback circuitry); resistance R.sub.ESR ; source voltage V.sub.CC ; reference voltage V.sub.REF ; trip voltage V.sub.TRIP ; load current I.sub.LOAD ; output voltage V.sub.OUT ; and feedback voltage V.sub.FB.

The preferred embodiment circuit of FIG. 2 adds a pull-down circuit PD.sub.1 to the prior art circuit of FIG. 1. The pull-down circuit PD.sub.1 includes comparator C.sub.1, trip voltage V.sub.TRIP, and pull-down transistor MP.sub.D. The comparator C.sub.1 is used to detect the output over-voltage condition and transistor MP.sub.D adds an internal current load to the output of the regulator while the over-voltage condition exists. The over-voltage condition can be detected by monitoring the output voltage of the amplifier A.sub.1 in the following manner. When there is no output current load placed on the regulator, the output voltage of the amplifier A.sub.1 is at voltage V.sub.a0. However, when an over-voltage condition exists because of the change in the load current I.sub.LOAD described above, the output voltage of the amplifier A.sub.1 rises to the maximum output voltage of the amplifier V.sub.a(max). The difference between the two voltages V.sub.a0 and V.sub.a(max) is approximately one volt which allows enough margin to accurately detect the over-voltage condition over process and temperature variations.

The schematic of the comparator C.sub.1 is shown in FIG. 3. The comparator circuit of FIG. 3 includes PMOS transistors MP.sub.1 and MP.sub.2 ; NMOS transistors MN.sub.1, MN.sub.2, and MN.sub.3, reference current I.sub.ref ; resistor R.sub.3 ; supply voltage V.sub.CC ; inverting comparator input IN-; non-inverting comparator input IN+; and comparator output V.sub.CO. The trip point of the comparator C.sub.1 is set by the resistor R.sub.3, and the current I.sub.ref in the following manner:

Using this equation, V.sub.trip is set 200 mV below V.sub.a(max).

The comparator works in the following manner. Under normal operating conditions the voltage on IN-, which monitors the output of the amplifier A.sub.1, is lower than the trip voltage V.sub.trip of the comparator C.sub.1. This forces a large V.sub.gs voltage on transistor MP.sub.1 which enters the linear region of operation and the output voltage of the comparator C.sub.1 rises to V.sub.trip. With the output of the comparator C.sub.1 high, transistor MP.sub.D in FIG. 2 is cut-off and no current is pulled from the output of the regulator. When an over-voltage condition exists due to the load current I.sub.LOAD of the regulator changing rapidly from a large value to near zero, the output voltage of the amplifier A.sub.1 rises above V.sub.trip which cuts off transistor MP.sub.1 and forces the output voltage of the comparator C.sub.1 to drop to virtual ground. When the output of the comparator C.sub.1 falls to ground, transistor MP.sub.D is forced into the linear region and pulls several milliamps of current from the output of the regulator, and returns the output voltage of the regulator back into regulation in a matter of a few milliseconds. Once the output voltage achieves regulation, the output of comparator C.sub.1 goes high and turns off transistor MP.sub.D, returning the regulator back to normal operation.

Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims. It is therefore intended that the appended claims encompass any such modifications or embodiments.