Magnetic-Free DC/DC Converter and Method of Operation Thereof

The present invention is directed, in general, to power conversion and, more specifically, to a magnetic-free DC/DC converter and a method of operation of the converter.

Regulated DC power supplies are employed in various analog and digital electronic systems. The power supplies are typically designed to produce a regulated output (i.e., the output voltage is maintained within a specific range) with electrical isolation between the input and output. Additionally, power supplies may also be designed to provide multiple outputs (e.g., positive and negative) that differ in voltage and current ratings. Two conventional topologies used in DC power supplies are a linear design topology and a switching design topology.

In the linear design topology, a low-frequency (e.g., 60 Hertz) transformer is used to provide electrical isolation between the input and output with a transistor acting as an adjustable resistor. While the linear power supply employs a simple design and introduces a moderate electromagnetic interference (EMI) with other equipment employed therewith, the topology endures several limitations. First, the low-frequency transformers are relatively large and, as a result, the dimensions of the linear power supply are constrained to accommodate the large low-frequency transformer. Due to the size limitations, the linear power supply is not preferable, especially, in environments where the components are being downsized. Additionally, the transistor, acting as an adjustable resistor, almost exclusively operates in its active region thereby resulting in a significant amount of power loss. Typically, the overall efficiencies of the linear power supplies are between 30% and 60%.

In contrast to the linear power supplies, the transformation of the DC voltage in the switching power supplies is accomplished using DC/DC converters. The DC/DC converters usually employ solid-state devices (e.g., transistors) as switching devices that are either completely on or completely off. Since the devices do not operate in the active region, power dissipation therethrough is significantly reduced resulting in a higher efficiency converter (typically, 70% to 90% efficient). Additionally, since the switching power supplies employ a high frequency isolation transformer, the size and weight of the switching power supplies may be significantly reduced.

In many applications, the voltage of the power supply rails of the electronic equipment exceeds the power requirements of the components employed therein. For instance, the optimum input voltages for short channel (e.g., L.sub.eff <0.2 .mu.m) complementary metal oxide semiconductor (CMOS) devices is less than 2 volts and the power supply rails on board-level systems is 3.3 volts. In such cases, a switched-mode DC/DC power converter is often employed to convert the voltage of the supply rails to the appropriate voltage of the individual components. Switched-mode DC/DC power converters generally include magnetic devices (e.g., inductors and transformers) that serve as a bridge for energy transfer in the converter. Presently, the magnetic devices cannot be integrated with other circuits and, as a result, are discrete components within the converter. While raising the switching frequencies of the converter may reduce the size of the magnetic devices, a discrete magnetic device is still necessary to achieve the energy storage and transfer function within the converter. For instance, in specific applications (e.g., smart power integrated circuits) where the control and switching devices (e.g., transistors and diodes) are integrated into an integrated circuit (IC), the magnetic devices remain discrete due to their size.

Accordingly, what is a need in the art is an improved power converter and method that overcomes the limitations of the prior art.

To address the above-discussed deficiencies of the prior art, the present invention provides magnetic-free DC/DC converters, methods of operation thereof and a computer system employing at least one converter. In one embodiment, the converter includes: (1) an input capacitor coupled to a DC input of the converter, (2) a first switch coupled between the input capacitor and an output of the converter to transfer electrical power from the DC input to the output when the first switch is closed, (3) an output capacitor coupled in parallel with the output of the converter, (4) a second switch coupled in parallel with the input capacitor to short the input capacitor when the second switch is closed and (5) a switching controller circuit, coupled to the first and second switches, that provides complementary control signals to the first and second switches that are a function of an output voltage of the converter.

The present invention therefore introduces a power converter that relies on capacitors for the transfer of energy within the converter rather than on magnetic components, such as transformers and inductors. Such magnetic-free converters may be advantageously embodied in monolithic integrated circuits.

In one embodiment of the present invention, the converter further comprises a voltage sensing circuit including a resistor divider network coupled in parallel with the output. The switching controller circuit senses a voltage at a node in the resistor divider network that is a function of the output voltage of the converter. Alternatively, the voltage sensing circuit may directly sense the output voltage of the converter.

In one embodiment of the present invention, the switching controller circuit comprises a flip-flop that provides the complementary control signals to the first and second switches. In an embodiment to be illustrated, the flip-flop is a DQ flip-flop.

In one embodiment of the present invention, the converter further comprises an inrush resistor, coupled between the input of the converter and the input capacitor, that limits a charge rate of the input capacitor. The inrush resistor, which is not necessary to the present invention, may be sized to meter the flow of input current to the input capacitor.

In one embodiment of the present invention, the output voltage is maintained at a single DC level. Alternatively, the output voltage may be made to vary.

In one embodiment of the present invention, the output voltage is selected from the group consisting of: (1) +5 volts and (2) +3.3 volts. Such voltages are commonly found in computer systems. Other voltages are certainly within the broad scope of the present invention.

In one embodiment of the present invention, the input and output capacitor, the first and second switches and the switching controller circuit are embodied in a monolithic integrated circuit. Alternatively, the present invention may be embodied as a circuit of discrete components.

The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.

For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a computer system that contains embodiments of multiple magnetic-free DC/DC converters constructed according to the present invention;

FIG. 2 illustrates a schematic diagram of an embodiment of the magnetic-free DC/DC converter of the present invention; and

FIG. 3 illustrates a timing diagram that depicts selected voltage and pulses during the operation of the magnetic-free DC/DC converter of FIG. 2.

Referring initially to FIG. 1, illustrated is a computer system 100 that contains embodiments of multiple magnetic-free DC/DC converters 130, 135 according to the present invention. The computer system 100 includes a power supply 110 that is typically coupled to a plurality of circuit boards (one of which is designated 120). The exemplary circuit board 120 includes the magnetic-free DC/DC converters 130, 135 that are individually coupled to a microprocessor 140 and dynamic random access memory (DRAM) 150, respectively. The magnetic-free DC/DC converters 130, 135 may be localized (i.e., integrated on the same chip with the component it supports) for applications requiring the energy source next to the component, for example high-speed circuits, or the converters may reside separately on a single chip. The present invention does not limit the magnetic-free DC/DC converters 130, 135 to reside in any specific location.

The power supply 110 generates a DC output voltage level that may be multiple DC output voltage levels (e.g., +3.3 or +5 volts). The power supply 110 output voltage is supplied by a power bus or other suitable mechanism to each of the circuit boards 120. The circuit boards may include, for instance, a motherboard (in a personal computer), "plug-in" dynamic DRAM chips, communication card(s) or video card(s). The magnetic-free DC/DC converters 130, 135 convert the output voltage from the power supply 110 to the voltage level requirements of the components or devices that the magnetic-free DC/DC converters 130, 135 support. The magnetic-free DC/DC converters 130, 135 are readily configured to provide the input voltage requirements of the component or device that it supports.

Turning now to FIG. 2, illustrated is a schematic diagram of an embodiment of a magnetic-free DC/DC converter 200 of the present invention. The magnetic-free DC/DC converter 200 includes an input DC voltage source 210 coupled to an inrush resistor 220. A capacitor discharging circuit 230 is coupled in series with the inrush resistor 220 and a first switch 240. The inrush resistor 220 reduces the current entering the capacitor discharging circuit 230 when the first switch 240 is initially closed. A transistor is typically used for the first switch 240. Of course, those skilled in the art should be familiar with other devices and switching design methodologies. The first switch 240 is also coupled to a load 270. A voltage sensing circuit 250 is coupled in parallel with the load 270 and to an output capacitor 260. A switching controller circuit 280 is coupled to the capacitor discharging circuit 230, the first switch 240 and the voltage sensing circuit 250.

The exemplary capacitor discharging circuit 230 includes an input capacitor 232 connected in series with a discharge resistor 234 and a second switch 236. The capacitor discharging circuit 230 allows the voltage across the input capacitor 232 to discharge by providing a current path when the second switch 236, typically a transistor, is ON (i.e., conducting). Those skilled in the art should be familiar with techniques for discharging capacitors. The voltage sensing circuit 250 includes a first and second resistor 252, 254 connected in series and a sample voltage V.sub.sample measured across second resistor 254 is described by the following equation :

The first and second resistors 252, 254 form a resistor divider network that allows adjustment, by varying the values of the first and second resistors 252, 254, of the output voltage V.sub.out to a desired value. The sample voltage V.sub.sample is provided to the switching controller circuit 280 thereby comparing the sample voltage V.sub.sample with a reference voltage V.sub.ref to determine the settings of the first and second switches 236, 240. The switching controller circuit 280 includes an operational amplifier 282 that is coupled to a DQ flip-flop 284. The operational amplifier 282 is configured as a comparator with the reference voltage V.sub.ref connected to the inverting input and the non-inverting input connected to the sample voltage V.sub.sample. The bistable output of the DQ flip-flop 284 provides a complementary switching arrangement with the first and second switches 236, 240.

Turning now to FIG. 3, illustrated is a timing diagram that depicts selected voltage and pulses during the operation of the magnetic-free DC/DC converter 200 of FIG. 2. The basic operation of the magnetic-free DC/DC converter 200 will hereinafter be described. It should be noted that the relative sizes of the separations between periods t.sub.0, t.sub.1, t.sub.2 and t.sub.3 are drawn for clarity and ease of explanation and are not necessarily to scale.

The voltage waveform 310 illustrates the sample voltage V.sub.sample, the voltage across the second resistor 254, and a dashed line 340 depicts the reference voltage V.sub.ref. A first and second switching control pulse waveforms 320, 330 demonstrated the control pulses for the first and second switches 240, 236 respectively. At a first time t.sub.0, the output capacitor 260 is completely discharged (i.e., V.sub.out =0 Volts) and the sample voltage V.sub.sample is also at zero volts. With the voltage at the noninverting input of the operational amplifier 282 at zero volts, a value lower than the reference voltage V.sub.ref (indicative of the output of the operational amplifier 282) causes the DQ flip-flop 284 to set (i.e., Q=1 and Q'=0) as illustrated by the first and second switching control pulse waveforms 320, 330. With the preceding conditions, the second switch 236 is not conducting (i.e., OFF) and the first switch 240 is ON. Those skilled in the art should appreciate that because of propagation delays inherent in the circuit, the first and second switches 236, 240, the operational amplifier 282 and the DQ flip-flop 284 do not change "state" instantaneously when the sample voltage V.sub.sample is greater or lower than the reference voltage V.sub.ref thereby resulting in the "ripple" in the voltage waveform 310. The magnitude of the ripple in the output voltage V.sub.out is dependent on the length of the propagation delays (i.e., the longer the propagation delays, the larger the magnitude of the ripple).

Between the first time period t.sub.0 and a second time period t.sub.1, the output capacitor 260 is charged through the inrush resistor 220 to the design output voltage V.sub.out and, at the second time period t.sub.1, the sample voltage V.sub.sample is equal to the reference voltage V.sub.ref, Assuming the voltage drops across the inrush resistor 220 and first switch 240 are negligible, the input capacitor 232 is also charged and the voltage across the input capacitor 232 is equal to the difference between the input and output voltage (V.sub.in 31 V.sub.out). After the second time period t.sub.1 (when V.sub.sample >V.sub.ref) , the output of the operational amplifier 282 changes state causing the DQ flip-flop 284 to reset (i.e. , Q=0 and Q'=1). With the new control signals Q, Q', the first and second switches 236, 240 are reconfigured with the first switch 240 OFF and the second switch 236 ON. Between the second time period t.sub.1 and a third time period t.sub.2, the output capacitor 260 discharges through the load resistor 270 and through the first and second resistors 252, 254 of the voltage sensing circuit 250. Also, during this period, with the second switch 240 ON, the input capacitor 232 is also discharging through the discharge resistor 234. Those skilled in the art should understand the necessity of discharging the input capacitor 232. If the voltage across the input capacitor 232 remains at the difference between the input and output voltage (V.sub.in -V.sub.out) when the first switch 240 is closed, the output voltage V.sub.out never attains the desired steady-state value. The voltage across the input capacitor 232, after the closing of the first switch 240, is increased from the difference between the input and output voltage (V.sub.in -V.sub.Out) and this prevents the voltage across the output capacitor 260 from reaching a steady-state condition at the desired output voltage V.sub.out. For the output voltage V.sub.out to reach a steady-state condition, the voltage across the input capacitor 232 should be below the difference between the input and output voltage (V.sub.in-V.sub.out) when the first switch 240 is closed. At the third time period t.sub.2, the sample voltage V.sub.sample has fallen to the reference value V.sub.ref and the output of the operational amplifier 282 again changes when the sample voltage V.sub.sample is less than the reference value V.sub.ref (V.sub.sample <V.sub.ref) causing the DQ flip-flop 284 to switch states (i.e., Q=1 and Q'=0). The output capacitor 260 is again charged to the designed output voltage V.sub.out at the fourth time period t.sub.3. The cycle of charging output capacitor 260 and discharging input capacitor 232 continues for the duration operation of the magnetic-free DC/DC converter 200.

For a better understanding of power electronics and switched-mode converters see Switching Power Supply Design, Abraham Pressman, McGraw Hill (1991), which is herein incorporated by reference.

Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.