Radio Communication Apparatus and Method

1. Field of the Invention

The present invention relates to radio communication systems via a repeater station such as a communications satellite, and in particular to a radio communication apparatus and method for compensating for frequency errors that may have occurred in a communication system.

2. Description of the Related Art

There have been known several methods by which multiple access may be achieved in satellite systems, including TDMA (time division multiple access (TDMA), pure ALOHA, and slotted ALOHA. In these multiple access methods, it is necessary to faithfully reproduce an original signal from a modulated burst signal received from each of earth stations which are widely distributed over the world.

In satellite communications, however, a burst signal generally includes frequency errors which are caused by up/down conversion in the transmission/reception system of each earth station and are caused by a frequency drift occurring in the satellite transponder. A frequency error caused in the transmission system of an earth station is different from that in another earth station, which can result in an interstation frequency error at the input to each earth station. On the other hand, frequency errors caused in the satellite transponder and the reception system of each earth station can be included commonly in all the burst signals received by the earth station.

The carrier recovery circuit at the receive side can sufficiently compensate for the interstation frequency error occurring in each of other earth stations. However, the common frequency errors which commonly appear in all received burst signals are much larger than the interstation frequency error. Therefore, it is difficult for the carrier recovery circuit to compensate for the common frequency errors by itself. If one tries to compensate for the common frequency errors by the carrier recovery circuit only, this compensation would be impossible without a long training bit field in the header of a burst signal. This manner is not a realistic solution because of reduced transmission efficiency. Then, an automatic frequency compensation (AFC) is required on the receive side where a pilot signal transmitted by the transmission side station is compared with a stable oscillator frequency. The use of AFC is necessary to compensate for any common frequency errors which may have occurred in the satellite and the receive side down-conversion.

However, a communication apparatus employing the AFC function as mentioned above needs a pilot oscillator, a down-converter and a demodulator for receiving the pilot signal in addition to necessary circuits for transmitting and receiving burst signals. Moreover, since a standby apparatus is necessary for emergency in a system base station, it is very difficult to reduce the size of the entire system and to simplify the system arrangement, which results in increased cost.

An object of the present invention is to provide a method which is capable of maintaining the accuracy of a received frequency by compensating for frequency errors with simplified configuration of a communication system.

Another object of the present invention is to provide a method which is capable of reducing frequency errors of received signals.

Still another object of the present invention is to provide a communication apparatus which is capable of coping with the frequency errors of received signals with a simple arrangement.

According to the present invention, a frequency error occurring in a repeater station and a receiving side is determined by using a check signal or a dummy signal received from the repeater station, and frequency control data corresponding to the frequency error is stored into a memory. By controlling a reception frequency based on the stored frequency control data, a data signal received from the repeater station is compensated for the frequency error. Therefore, a relatively large frequency error such as the common frequency error occurring in the satellite and the downconverter of the receiving side can be eliminated effectively.

According to a first aspect of the present invention, the check signal comprising a predetermined code pattern is received from the repeater station which has transmitted the check signal at the predetermined frequency, and then a reception frequency of the check signal is determined when the predetermined code pattern is detected from the check signal. After storing the frequency control data corresponding to the reception frequency of the check signal, the data signal is received from the repeater station based on the frequency control data stored. A radio station itself may transmit the check signal to the repeater station and then receive it from the repeater station.

Preferably, the reception frequency of the check signal is determined by a local oscillation frequency which is adjusted so that the predetermined code pattern is detected from the check signal. In this case, the frequency control data is a signal value of the local oscillation control signal when the predetermined code pattern is detected from the check signal.

According to a second aspect of the present invention, in a method for compensating a received signal for a frequency error in a first radio station, the received signal being received from a second radio station via a repeater station, a predetermined signal comprising a predetermined code pattern is received from the repeater station transmitting the predetermined signal at a predetermined frequency. The frequency control data is determined by adjusting a reception frequency of the predetermined signal received from the repeater station so that the predetermined code pattern is detected from the predetermined signal. The frequency control data corresponding to the reception frequency of the predetermined signal is stored into a memory when the predetermined code pattern is detected from the predetermined signal. Based on the frequency control data, the received signal is compensated for the frequency error.

According to a third aspect of the present invention, the data signal which has been transmitted at a predetermined frequency by a repeater station is comprised of a first preamble code pattern followed by a first synchronization code pattern. As a first step, it is checked whether the data signal is received in an initial acquisition state where a carrier signal of the data signal is recovered from the first preamble code pattern. When the data signal is received in the initial acquisition state, the check signal is transmitted to the repeater station, the check signal comprising a second preamble code pattern followed by a second synchronization code pattern. When receiving the check signal from the repeater station which has transmitted the check signal at the predetermined frequency, a reception frequency of the check signal received from the repeater station is determined when the second synchronization code pattern is detected from the check signal and then the frequency control data corresponding to the reception frequency of the check signal is stored into the memory when the second synchronization code pattern is detected from the check signal. Based on the frequency control data stored, the data signal is received from the repeater station when the first synchronization code pattern is detected from the data signal.

Further preferably, it is checked whether the first synchronization code pattern is detected from the data signal within a predetermined time interval, and when the first synchronization code pattern fails to be detected from the data signal within the predetermined time interval, the check signal is transmitted to the repeater station. When the second synchronization code pattern fails to be detected from the check signal which was transmitted, the control returns to the first step.

As described above, according to the present invention, by receiving a check signal through the repeater station, the frequency error caused in the repeater station and the receiving side radio station is previously detected, and the frequency control data or frequency compensation data at that time is stored. When a data signal is received at a normal operation, compensation is made for the frequency error by using the stored frequency control data. Therefore, the data signal can be received with compensating for the common frequency error as well as the interstation frequency error. Since the pilot signal is not needed in the AFC like the prior art, a miniaturized and low-cost communication system can be achieved.

FIG. 1 is a block diagram schematically showing an embodiment of the communication system according to the present invention;

FIG. 2A is a format diagram showing an example of a dummy burst signal to be used according to this embodiment;

FIG. 2B is a format diagram showing an example of a data burst signal;

FIG. 2C is a format diagram showing another example of the data burst signal;

FIG. 3 is a schematic flowchart showing an initial operation of this embodiment at the initial acquisition mode; and

FIG. 4 is a schematic flowchart showing a normal operation of this embodiment at the normal operation mode.

Referring to FIG. 1, an earth station is comprised of a transmission subsystem comprising a modulating circuit 1, an upconverter 2, and a high-power amplifier (HPA) 3, and a reception subsystem comprising a low-noise amplifier (LNA) 6, a downconverter 7, and a demodulating circuit 8. In the transmission subsystem, the modulating circuit 1 receives transmission data and burst modulates a carrier to produce a modulated burst signal. The modulated burst signal is upconverted to a predetermined transmitter RF frequency by the up-converter 2 and is then amplified by the high-power amplifier (HPA) 3 to a level suitable for transmission. The transmission burst RF signal which has been output from the high-power amplifier 3 is transmitted as an up-link signal to a communication satellite 5 through an antenna 4.

Receiving such an up-link signal from an earth station, the communication satellite 5 serves as a repeater allowing the up-link signal to be amplified and converted in frequency for the down-link.

A low-level burst RF signal received from the communication satellite 5 through the antenna 4 is input to the low-noise amplifier (LNA) 6 which amplifies it to keep the carrier-to-noise ratio at an acceptable value. The downconverter 7 converts the RF signal to an IF signal and passes it to the demodulating circuit 8 for extraction of the included information. The transmission and reception operations of the entire system are controlled by a control processor 9 using a timer 10 as necessary. A more detailed description will be provided hereinafter.

The modulating circuit 1 selects a modulating signal from a data burst modulating signal D.sub.n for normal operation and a dummy burst modulating signal D.sub.dm for check operation under the control of the control processor 9 and then burst modulates a carrier according to the selected modulating signal to output the modulated burst signal to the upconverter 2.

More specifically, when transmission data is input to the modulating circuit 1, a UW combiner 101 adds a sequence known as a unique word (UW) for burst synchronization to the transmission data and passes it to a PR combiner 102. The PR combiner 102 further adds a prefixed bit pattern known as the preamble to it. The preamble consists of a carrier recovery code and a bit timing recovery code (see FIG. 2). By the UW combiner 101 and the PR combiner 102, the data burst modulating signal D.sub.n is generated based on the transmission data, and is output to a selector 103. On the other hand, a dummy burst generator 104 outputs the dummy burst modulating signal D.sub.dm to the selector 103 in accordance with control of a transmission controller 107. The dummy burst generator 104 is comprised of a UW combiner and PR combiner.

The selector 103 selects either the data burst modulating signal D.sub.n or the dummy burst modulating signal D.sub.dm in accordance with control of the transmission controller 107 and outputs the selected modulating signal to a modulator 105 of a predetermined modulation scheme. As described later, the data burst modulating signal D.sub.n of the transmission data is selected at a normal operation mode, and the dummy burst modulating signal D.sub.dm of the dummy burst is selected at an initial acquisition mode or a self-check mode. The modulator 105 burst modulates the carrier which is generated by a local oscillator 106 in accordance with the selected modulating signal and outputs the modulated burst signal to the upconverter 2.

The demodulating circuit 8 performs the frequency error compensation in addition to a normal demodulation operation. The modulating circuit 8 is provided with a frequency converter comprising a mixer 201 and a variable-frequency local oscillator 202, which compensate the received IF burst signal for frequency errors. The mixer 201 receives the IF burst signal from the downconverter 7 and mixes it with the local oscillation signal generated by the local oscillator 202. Since the oscillation frequency of the local oscillator 202 varies in accordance with a control signal S.sub.w, as described later, the local oscillator 202 can compensate the received burst signal for the frequency errors.

A demodulator 203 receives the frequency-converted burst signal from the mixer 201 and burst demodulates it into received data. The demodulator 203 performs the demodulation, as known well, by using a clock reproduced by a clock recovery circuit 204 and a carrier reproduced by a carrier recovery circuit 205. When the clock and the carrier have been reproduced, the demodulator 203 becomes in the initial acquisition state.

The carrier recovery circuit 205 is comprised of a well-known PLL (phase-locked loop) circuit comprising a voltage-controlled oscillator (VCO), a phase comparator, and a loop filter. Since the control voltage for the VCO becomes low when the carrier has been recovered, it can be easily checked whether a carrier has been recovered by monitoring the control voltage for the VCO.

A UW detector 206 detects the unique word (UW) from the received data produced by the demodulator 203. When detecting the unique word, the UW detector 206 outputs a UW detection signal to a reception controller 207, the control processor 9, and an AFC (automatic frequency compensation) circuit 208, respectively.

The reception controller 207 detects the initial acquisition of the demodulator 203 by monitoring the control voltage V.sub.CO received from the carrier recovery circuit 205, and further detects the detection of the unique word by monitoring the UW detection signal received from the UW detector 206. The reception controller 207 controls the AFC circuit 208 on the basis of the detection timing of the unique word and causes an LO control data memory 209 to store an LO initial control data at the detection timing of the unique word of the received dummy burst signal.

The AFC circuit 208 performs the AFC operation under control of the reception controller 207 in accordance with a frequency error signal which is the control voltage received from the carrier recovery circuit 205 so as to reduce the frequency errors. More specifically, in order to reduce the frequency errors in the carrier recovery circuit 205, the AFC circuit 208 varies the LO control signal S.sub.LO to adjust the local oscillation frequency supplied to the mixer 201. Such a loop including the AFC circuit 200 can compensate for a relatively small frequency error such as an interstation frequency error.

The initial LO control data to be stored in the LO control data memory 209 is LO control data which is used to compensate for a relatively large frequency error such as the common frequency error as mentioned before. As described above, since the common frequency error is included in the dummy burst signal received via the communication satellite 5, the LO initial control data can be determined on the basis of the LO control signal S.sub.LO at the time when the unique word of the received dummy burst signal is detected. The LO initial control data stored in the LO control data memory 209 is converted into analog by a digital-to-analog converter 210 which passes the LO control signal to an added 211. The adder 211 adds the LO initial control signal to the control signal output from the AFC circuit 208, and outputs the resultant to the local oscillator 202 as an LO control signal S.sub.LO.

At initial acquisition of the demodulator 203, the control processor 9 controls the transmission controller 107 so that the dummy burst signal is generated and transmitted. Under the control of the control processor 9, the transmission controller 107 switches the selector 103 so as to select the dummy burst side and initiates the dummy burst generator 104. As a result, the dummy burst modulating signal D.sub.dm is generated and transferred to the modulator 105 through the selector 103, and the dummy burst RF signal is emitted from the antenna 4 to the communication satellite 5. Moreover, the controller processor 9 checks whether the unique word is detected within a predetermined time interval by using the timer 10. If the unique word is not detected within the predetermined time interval, the control processor 9 changes to self-check mode where the dummy burst signal is transmitted, as described later.

Comparing the signal formats as shown in FIGS. 2A and 2B, it is understood that the dummy burst signal of FIG. 2A has a carrier recovery code CR which is much longer than that of a normal burst signal of FIG. 2B. For example, the carrier recovery code CR of the dummy burst signal is about 1000 bits length in terms of the number of bits. Such a long carrier recovery code CR allows the carrier recovery circuit 205 of the demodulating circuit 8 to perform an accurate carrier reproduction even if the frequency and phase errors of the carrier are large. The unique word UW of the dummy burst signal is identical to that of the normal burst signal.

Alternatively, as shown in FIG. 2C, the carrier recovery code CR and the bit timing recovery code BR may be set to the same code CR+BR (for example, `101010 . . . 10`) to concurrently perform the carrier recovery and the clock recovery. It is also a preferred embodiment of the present invention that a dummy burst signal and a data burst signal are generated by using such a preamble format that the carrier recovery code CR and the bit timing recovery code BR are combined into the same code CR+BR. In this case, the carrier recovery code and the bit timing recovery code (CR+BR) of the dummy burst signal are set to be longer than that of the data burst signal.

Next, an operation of this embodiment shown in FIG. 1 will be described in detail with reference to the flowcharts.

Referring to FIG. 3, the control processor 9 checks through the reception controller 207 at all times whether the demodulator 203 reaches the initial acquisition state (step S301). When the demodulator 203 becomes in the initial acquisition mode (Yes of step S301), the control processor 9 instructs the transmission controller 107 to perform the dummy burst transmission and instructs the reception controller 207 to perform the dummy burst reception.

The transmission controller 107, receiving the instruction for the dummy burst transmission, performs the transmission control of the dummy burst signal such that the selector 103 selects the dummy burst generator 104 which generates the dummy burst modulating signal D.sub.dm. The modulator 105 modulates the carrier wave generated by the local oscillator 106 in accordance with the dummy burst modulating signal D.sub.dm, and the dummy burst signal as the modulated burst is output to the upconverter 2. Thus, the dummy burst RF signal is transmitted to the communication satellite 5 (step S302).

On the other hand, receiving the instruction of the dummy burst reception, the reception controller 207 checks whether the dummy burst signal has been received from the communication satellite 5 based on carrier and clock reproduction and unique word detection as describe before (step S303). More specifically, the carrier recovery circuit 205 performs carrier reproduction based on the pattern of the carrier recovery code CR of the dummy burst signal received from the communication satellite 5. In the carrier recovery, the AFC circuit 208 receives an error signal V.sub.CO indicating frequency and phase errors from the carrier recovery circuit 205, and outputs the LO control signal S.sub.LO to the local oscillator 202 through the adder 211 so as to adjust the local oscillation frequency of the local oscillator 202. When the error signal V.sub.CO of the carrier recovery circuit 205 is reduced below a predetermined level, based on the LO control signal S.sub.LO at that time, LO initial control data is determined as indicating a local oscillation frequency necessary for receiving the dummy burst signal. After the carrier recovery is completed, the clock reproduction is performed based on the bit timing recovery code BR of the dummy burst signal. In the case of the format shown in FIG. 2C, it is needless to say that carrier and clock are recovered concurrently based on the preamble CR+BR. After the carrier and clock reproduction is thus completed, the demodulator 203 demodulates a sequence following the bit timing recovery code BR from the received dummy burst signal, and the UW detector 206 detects the unique word UW.

At the time when the unique word UW is detected, the reception controller 207 recognizes that the frequency error or the common frequency error has been estimated. Therefore, when the unique word UW is detected and the reception of the dummy burst signal is successfully completed (Yes of step S303), the reception controller 207 stores LO initial control data indicating the LO control signal at that time into the LO control data memory 209 (step S304). In other words, the LO initial control data stored in the LO control data memory 209 is the compensation data of the common frequency error which is caused by the frequency drift of the transponder in the communication satellite 5 and the downconversion of the downconverter 7.

At the same time, the control processor 9 outputs the instruction indicative of stopping the dummy burst transmission to the transmission controller 107 (step S305). This causes the dummy burst generator 104 to stop generating the dummy burst modulating signal D.sub.dm, and the selector 103 to select the data burst modulating signal D.sub.n. Furthermore, the control processor 9 switches the demodulating circuit 8 to the normal operation mode (step S306).

In the normal operation mode, the common frequency error estimated based on the received burst signal is canceled out by adding the LO initial control data stored in the LO control data memory 209 to the output of the AFC circuit 208. The relatively small level error such as an interstation frequency error is reduced by the AFC circuit 208 using the carrier recovery code CR and the bit timing recovery code BR in the received data burst signal. Therefore, the frequency errors of the received data burst signal are effectively removed by the LO control signal S.sub.LO obtained by adding the output of the AFC circuit 208 and the output of the LO control data memory 209.

Referring to FIG. 4, when the demodulating circuit 8 is switched to the normal operation mode, the control processor 9 resets the timer 10 (step S401), and then, checks whether the unique word UW has been detected by the UW detector 206 (step S402). If the unique word UW is detected (Yes of step S402), then the reception controller 207 puts the AFC circuit 208 into operation, causing the received data burst signal to be compensated for the relatively small level error such as an interstation frequency error as mentioned above (step S403). Since the length of the burst signal is predetermined, the length of the data field following the unique word UW can be calculated. Therefore, the reception controller 207 allows the AFC circuit 208 to be operated only in the data field based on the detection timing of the unique word UW. In other words, the frequency error compensation can be performed in the data field of a received data burst signal.

If the unique word UW is not detected (No of step S402), then it is checked whether the predetermined time interval preset in the timer 10 has passed (step S404), and the unique word detection step 402 is repeatedly performed until the predetermined time interval has passed.

If the unique word is not detected within the predetermined time interval (No of step S402 and Yes of S404), there is a possibility that the reception of a burst signal has been impossible, so that the modulating circuit 1 and the demodulating circuit 8 are shifted to the self-check mode. When in the self-check mode, the dummy burst generator 104 generates the dummy burst modulating signal D.sub.dm and outputs it to the modulator 105 through the selector 103, and the dummy burst RF signal is emitted toward the communication satellite 5 (step S405).

When receiving the dummy burst signal from the communication satellite 5, that is, when the unique word UW is detected by the unique word detector 206 (Yes of step S406), the control processor 9 determines that a burst signal can be normally received. After resetting the timer 10 (step S401), the control processor 9 returns to the above-mentioned sequence S402-S404.

If the unique word UW is not able to be detected (No of step S406), it is judged that the dummy burst signal is not able to be received, and the control processor 9 returns to the initial acquisition mode so as to perform the above-mentioned adjustment of the local oscillation frequency of the local oscillator 202 (S301-S306).