CDMA Receiver

1. Field of the Invention

The present invention generally relates to a multiple-access communications system, and in particular to a receiver and receiving method for use in a CDMA (Code Division Multiple Access) communications system using a spread spectrum (SS) scheme.

2. Description of the Related Art

Power control, as known well, is a necessary function in a CDMA system serving mobile users, because of the near-far problem. On the link from a mobile terminal to the base station, each signal is received with a different amount of path loss due to, for example, variations in distances of the mobile terminals from the base station. Therefore in a case where all the mobile terminals transmit with the same signal power, their signals will arrive at the base station with different power levels. This near-far problem is solved by controlling the power transmitted by each mobile terminal such that the same power level is received at the base station from each mobile terminal. In general, the base station continuously measures the Signal-to-Interference power ratio (hereinafter referred to as SIR) based on the power level of a signal received from a mobile terminal and provides continuous feedback to the mobile terminal so that the mobile terminal can adjust its power level dynamically.

Another power control technique has been proposed in Japanese patent unexamined publication No. 5-75571. In this technique, at the mobile terminal, the power level of a signal received from the base station is measured and then the transmitted signal power is dynamically adjusted according to the received power level.

Still another technique of obtaining SIR of a received signal at a mobile terminal is disclosed in Japanese patent unexamined publication No. 5-37490. According to this publication, SIR is obtained by comparing a desired signal power with all received signal powers and is used to determine whether the communication quality is good. In a case where SIR is lower than a predetermined threshold value, the user is informed of communication impairment by beep sound or blinking light. Therefore, the user can do an immediate corrective action such as reorienting the receiving antenna or the like.

However, the above conventional receivers in the base station or the mobile terminal provide the following disadvantages. First, in a case where the base station receives a signal with relatively low SIR from a mobile terminal due to multiple-user interference and/or transmission channel distortion, there is a possibility that a synchronization tracking system causes the receiving timing to be locked to a noise signal. Since such a receiving timing error is interpreted as impaired SIR, the power control system of the base station increases the power transmitted by the mobile terminal until reaching the maximum transmission power level. The increased transmission power causes the reduced battery life.

Further, since the receiving antenna of the base station cannot be easily reoriented, it is very difficult to employ the conventional receiver in the base station.

An object of the present invention is to provide a receiver and receiving method which achieve an stable receiving operation even when SIR is relatively low.

Another object of the present invention is to provide a receiver and receiving method which is able to provide the reliable receiving reference timing which ensures a stable communication quality and a stable transmission power control.

According to the present invention, a phase control operation for synchronization tracking is performed at a variable rate. The variable rate is determined depending on a magnitude of the signal power relative to the interference power such as a signal-to-interference power ratio (SIR).

A spread spectrum receiver according to the present invention is comprised of a chip sync circuit for controlling a phase of a spreading code for tracking synchronization at a phase control rate to produce a despreading code, wherein the phase control rate is variable according to a rate control value. A rate control value for controlling the phase control rate is determined based on a magnitude of the signal power relative to the interference power. More specifically, after a predetermined number of power levels is set based on the interference power, the signal power is compared with the power levels to determine the magnitude of the signal power. And the rate control value is determined so as to be in proportion to the magnitude of the signal power. Therefore, the lower the phase control rate of the chip sync circuit, the smaller the magnitude of the signal power relative to the interference power. In other words, the chip sync circuit controls the phase of the spreading code for tracking synchronization at intervals of a time period to produce the despreading code, the time period being variable according to the rate control value. The time period becomes shorter as the magnitude of the signal power relative to the interference power is larger and longer as the magnitude of the signal power relative to the interference power is smaller.

Therefore, by lowering the phase control rate when SIR is impaired, the error rate of receiving timing detection due to noises can be reduced, resulting in stable power control and improved communication quality.

FIG. 1 is a block diagram showing an embodiment of a radio receiver according to the present invention;

FIG. 2 is a block diagram showing an example of a chip synchronization circuit as shown in FIG. 1; and

FIGS. 3A-3C are diagrams showing a vector addition and averaging method of the symbols of a received unique word in an I-Q plane.

A CDMA receiver according to the present invention is used to receive a spread spectrum signal which is subjected to spreading modulation at a transmitting system of a base station or a mobile station in a spread spectrum (SS) communications system.

Referring to FIG. 1, after a radio receiver (not shown) demodulates a received SS signal into a demodulated SS signal, the demodulated SS signal is converted into a quantized received SS signal by an analog-to-digital converter (not shown). The quantized received SS signal is output to a correlator 101 and a chip sync circuit 102.

The correlator 101 performs despreading by use of a spreading code SC generated by a spreading code generator 103 and a despread timing signal T.sub.DSC generated by the chip sync circuit 102. More specifically, the correlator 101 performs multiplies and accumulates the quantized received SS signal and the spreading code SC according to the despread timing signal T.sub.RSC, and generates a symbol-rate quantized received signal, that is, a despread received signal.

The chip sync circuit 102 first searches for a chip timing providing synchronization between the quantized received SS signal and the spreading code SC while sequentially shifting the phase of the spreading code SC by a predetermined amount under the control of a processor 111. When the chip timing is found, the chip sync circuit 102 outputs a sync flag signal FLAG to the processor 111 and then outputs the despread timing signal T.sub.RSC to the correlator 101. After the sync acquisition, the chip sync circuit 102 enters into the sync tracking operation which is performed according to a tracking rate control signal SPC as described in detail later.

The despread signal generated by the correlator 101 in the above manner is output to a detector (or demodulator) 104 which demodulates it into received data, for example, a speech signal and a control signal. The demodulated control signal is used in the processor 111. The despread signal is also output to a symbol-sync detector 105, an RSSI measurement circuit 106, and an ISSI measurement circuit 107. The symbol-sync detector 105 detects a unique word (UW) or a pilot signal from the despread signal to establish symbol synchronization. The symbol timing signal is output to the RSSI measurement circuit 106, the ISSI measurement circuit 107, and the processor 111.

The RSSI measurement circuit 106 measures a desired signal power (hereinafter called RSSI) by inputting the symbols indicative of a unique word according to the symbol timing signal (see FIG. 3A), converting them into the same phase quadrant (see FIG. 3B) and then averaging the signal powers of the converted symbols (see FIG. 3C). That is, an in-phase vector addition is performed and then the result is averaged.

The ISSI measurement circuit 107 measures an interference signal power (hereinafter called ISSI) by inputting the symbols indicative of the unique word according to the symbol timing signal (see FIG. 3A) and then averaging the difference in power between RSSI and the received power of each symbol of the unique word. The output ISSI is provided to multipliers 108 and 109 which multiply ISSI by coefficients .beta.1 and .beta.2, respectively. It is assumed that .beta.1 is greater than .beta.2 by a predetermined amount. Therefore, the multipliers 108 and 109 provide two power levels: .beta.1*ISSI and .beta.2*ISSI. Needless to say, three or more multipliers having respective coefficients .beta.1, .beta.2, .beta.3, . . . , may be provided to set three or more power levels. It should be noted that RSSI and ISSI may be detected by other known methods.

A comparator 110 inputs RSSI from the RSSI measurement circuit 106 and further inputs the power levels .beta.1*ISSI and .beta.2*ISSI from the multipliers 108 and 109, respectively. The comparator 110 compares RSSI with each of .beta.1*ISSI and .beta.2*ISSI to produce a rate control signal SPC in accordance with the following condition. SPC is set to .alpha.1 when RSSI is greater than .beta.1*ISSI, SPC is set to .alpha.2 when RSSI is not greater than .beta.1*ISSI but greater than .beta.2*ISSI, and SPC is set to .alpha.3 when RSSI is not greater than .beta.2*ISSI, where .alpha.1>.alpha.2>.alpha.3. The rate control signal SPC is output to the chip sync circuit 102 which performs the sync tracking in an operation timing clock according to the rate control signal SPC.

The processor 111 performs the whole operation control of the receiver through control signals while receiving the received control signal, the symbol sync signal, the sync flag signal FLAG and other necessary signals.

Referring to FIG. 2, the chip sync circuit 102 is comprised of a timing shift circuit 201, an early timing shift circuit 202, and a late timing shift circuit 203. The timing shift circuit 201 receives the spreading code SC from the spreading code generator 103 and shifts the phase of the spreading code SC by Tc/m, that is, 1/m chip, according to the control signal received from the processor 111 or a shift direction signal received from a comparator 214, where Tc is a chip duration and m is an integer greater than 0. The output code DSC is supplied to the early timing shift circuit 202, the late timing shift circuit 203, and a first correlator 204, further is supplied as the despread timing signal T.sub.RSC to the correlator 101. The early timing shift circuit 202 produces an early spreading code by shifting the phase of the spreading code SC by +Tc/n, that is, +1/n chip, and the late timing shift circuit 203 produces a late spreading code by shifting the phase of the spreading code SC by -Tc/n, that is, -1/n chip, where n is an integer greater than 0.

The first correlator 204 produces a correlation value .gamma.1 of the quantized received signal and the despreading code DSC received from the timing shift circuit 201. A second correlator 205 produces a correlation value .gamma.2 of the quantized received signal and the early spreading code received from the early timing shift circuit 202 and a third correlator 206 produces a correlation value .gamma.3 of the quantized received signal and the late spreading code received from the late timing shift circuit 203.

The correlation values .gamma.2 and .gamma.3 are output to a subtractor 207 which subtracts the correlation value .gamma.3 from the correlation value .gamma.2 to produce an error signal ES=.gamma.2-.gamma.3. The correlation values .gamma.1 and .gamma.2 are output to a comparator 208 and the correlation values .gamma.1 and .gamma.3 are output to a comparator 209. The comparators 208 and 209 concurrently produce a logical value of 1 when the correlation value .gamma.1 is greater than each of the correlation values .gamma.2 and .gamma.3. Therefore, an AND gate 210 outputs a sync flag signal FLAG of 1 to the processor 111 when .gamma.1>.gamma.2 and .gamma.1>.gamma.3. As described before, the processor 111 is informed of the synchronization acquisition when detecting synchronization between the sync flag signal FLAG received from the AND gate 210 and the symbol sync signal received from the symbol-sync detector 105.

The error signal ES=.gamma.2-.gamma.3 is output to an integrator comprising a multiplier 211, an adder 212, and a delay shift register 213 which are connected as known well. The multiplier 211 receives the error signal ES=.gamma.2-.gamma.3 from the subtractor 207 and multiplies it by the magnitude .alpha. of the rate control signal SPC: .alpha.1, .alpha.2, or .alpha.3 (here .alpha.1>.alpha.2>.alpha.3). In other words,the magnitude .alpha. of the rate control signal SPC serves as an integral coefficient or the inverse of an integral time constant. Therefore, the smaller the magnitude .alpha. of the rate control signal SPC, the slower the integral IES of the error signal ES increases or decreases.

A comparator 214 compares the absolute value of the integral output IES with a predetermined reference value .delta. to output a shift direction signal to the timing shift circuit 201. More specifically, when IES>+.delta., the comparator 214 output a backward shift signal SD(+) to the timing shift circuit 201 or when IES <-.delta., the comparator 214 output a forward shift signal SD(-) to the timing shift circuit 201. Further, when IES exceeds +.delta. or -.delta., the comparator 214 outputs a reset signal to the delay shift register 213 of the integrator to initialize the contents of the shift register 213.

Upon receiving the backward shift signal SD(+) from the comparator 214, the timing shift circuit 201 delays the phase of the spreading code SC by 1/m chip. Contrarily, upon receiving the forward shift signal SD(-), the timing shift circuit 201 advances the phase of the spreading code SC by 1/m chip.

During the initial sync acquisition, the timing shift circuit 201 of the chip sync circuit 102 is not controlled by the shift direction signal received from the comparator 214 but the control signal received from the processor 111. More specifically, under the control of the processor 111, the spreading code generator 103 generates the spreading code SC to output it to the correlator 101 and the timing shift circuit 201 of the chip sync circuit 102. The timing shift circuit 201 sequentially shifts the phase of the spreading code SC in units of 1/m chip until the spreading code SC is in phase with the quantized received SS signal. Upon detecting the synchronization between the sync flag signal FLAG and the symbol sync signal, the processor 111 switches the timing shift circuit 201 from sync acquisition to sync tracking.

In the sync tracking operation, the timing shift circuit 201 performs the timing shift operation according to the shift direction signal received from the comparator 214. More specifically, each time the absolute value of the integral IES of the error signal ES exceeds .delta., the timing shift circuit 201 delays or advances the phase of the spreading code SC by 1/m chip. As described before, the time period elapsed before the absolute value of the integral IES of the error signal ES reaches .delta. is dependent on the magnitude .alpha. of the rate control signal SPC received from the comparator 110. In other words, the timing shift circuit 201 performs the timing shift operation at time intervals determined according to the rate control signal SPC. More specifically, the rate control signal SPC is set to a smaller magnitude as the ratio of RSSI to ISSI or SIR becomes lower, that is, the receiving condition becomes impaired. Therefore, in cases where SIR is impaired, the timing shift operation is performed by the timing shift circuit 201 at relatively long time intervals. In other words, the timing shift rate of the chip sync circuit 102 is changed depending on the degree of SIR impairment.

Since the timing shift rate of the chip sync circuit 102 is lower as SIR becomes lower, the receiving timing error due to noises is effectively prevented, resulting in stable receiving operation. Therefore, stable transmission power control and stable communications can be maintained even when SIR is relatively low.