Bandgap Reference Circuit

The present invention in general relates to electronic circuits, and in particular relates to circuits providing temperature independent reference voltages.

It is common in the electronic art to use reference voltage in connection with complex circuits and systems. Various circuits for generating reference voltages are well known, including those which employ temperature compensation so that the reference voltage is substantially independent of the temperature over a significant range.

Bandgap reference circuits are known, for example, from:

›1! Horowitz, P., Hill, W.: The art of electronics, Second Edition, Cambridge University, Press, chapter 6.15: Bandgap (V.sub.BE) reference, pages 335-341;

›2! Ahuja, B. et. al.: A programmable CMOS Dual Channel Interface Processor for Telecommunications Applications, IEEE Journal of Solid State Circuits, vol. SC-19, no. 6, December 1984;

›3! Song, B. S., Gray, P. R.: A Precision Curvature-Compensated CMOS Bandgap Reference, IEEE Journal of Solid-State Circuits, vol. SC-18, No. 6, December 1983, pages 634-643;

›4! U.S. Pat. No. 4,375,595 to Ulmer et. al.;

›5! Ruszynak, A.: CMOS Bandgap Circuit, Motorola Technical Developments, volume 30, March 1997, published by Motorola Inc., Schaumburg, Ill. 60196, pages 101-103; and

›6! U.S. Pat. No. 4,896,094 to Greaves et. al.

The principle used in the circuits described in ›1! and ›2!, as with many other similar circuits, is based on adding two voltages whose temperature coefficients have opposite signs. One voltage is generated by a current of a given amount flowing through a diode or bipolar transistor resulting in a negative temperature coefficient and the other voltage is obtained across a first resistor through which a current flows whose value is defined by the voltage difference on two diodes or bipolar transistors operating on different current density levels and by a second resistor.

FIG. 1 illustrates a simplified circuit diagram of prior art bandgap reference circuit 100 (hereinafter circuit 100). Circuit 100 comprises operational amplifier 130 ("op amp"), resistor 110 having a value of R.sub.1, resistor 120 with value R.sub.2, resistor 115 having value R.sub.C1, resistor 125 having value R.sub.C2, transistor 135 (also: Q.sub.0), transistor 116 (also: Q.sub.i1), transistor 126 (also: Q.sub.i2), and current source 160. Circuit 100 is coupled to a first potential VCC at line 191 and to a second potential GND at line 192. Circuit 100 provides a reference potential V.sub.BG at line 195. Potential V.sub.BG is, preferably, referred to the GND potential. In the example of FIG. 1, transistors Q.sub.i1, Q.sub.i2, and Q.sub.0 are bipolar transistors of negative-positive-negative (npn) type having, as illustrated representative for Q.sub.0, a base 137 "B", an emitter 138 "E", and an collector 136 "C". Preferably, the VCC potential is positive compared to the GND potential. Connections of op amp 130 to lines 191 and 192 are well known in the art and not shown for simplicity.

Resistors 115 (R.sub.C1) and 125 (R.sub.C2) couple the collectors C of transistors 116 (Q.sub.i1) and 126 (Q.sub.i2), respectively, to line 191 (VCC). The emitters E of transistors 116 (Q.sub.i1) and 126 (Q.sub.i2) are coupled together to current source 160 which is itself coupled to line 192 (GND). The collector C of transistor 135 (Q.sub.0) is coupled to line 191. The emitter E of transistor 135 (Q.sub.0) is coupled at node 111 to line 192 via serially resistors 110 (R.sub.1), node 112, and 120 (R.sub.2). The emitter E of Q.sub.0 (node 111) is coupled also to the base B of Q.sub.i2. Node 112 is coupled to the base B of Q.sub.i1. Collectors C of Q.sub.i1 and Q.sub.i2 are coupled to negative input 131 and positive input 132, respectively, of op amp 130. Output 133 of op amp 133 is coupled to the base B of Q.sub.0 and forms thereby line 195 (V.sub.BG).

For further explanation, V.sub.R1 is a voltage across resistor 110 (between nodes 111 and 112); V.sub.R2 is a voltage across resistor 120 (between node 112 and line 192); V.sub.BE0, V.sub.BEi1, and V.sub.BEi2 are voltages across bases (B) and emitters (E) of transistors Q.sub.0, Q.sub.i1, and Q.sub.i2, respectively. Currents I.sub.i1 and I.sub.i2 are generated by current source 160 and flow through collectors (C) and emitters (E) of transistors Q.sub.i1 and Q.sub.i2, respectively. For simplicity, base currents are neglected.

As illustrated by an encircled uppercase letter M, the values R.sub.C2 and R.sub.C1 of resistors 125 and 115 are, preferably, in the ratio of:

with the slash / standing for division. As illustrated by encircled N, the emitter areas A.sub.i1 of Q.sub.i1 and A.sub.i2 of Q.sub.i2 are, preferably, related as:

Ratios M and N provide that currents I.sub.i1 and I.sub.i2 and current densities in Q.sub.i1 and Q.sub.i2 are different. In general, ratios M*N can be expressed as current density ratio Y:

Hence, the emitter-base voltages V.sub.BEi1 (of Q.sub.i1) and V.sub.BEi2 (of Q.sub.i 2) are different. A voltage difference .DELTA.V can be calculated by:

with V.sub.T for a temperature voltage, 1n for logarithm naturalis operation and * for multiplication. V.sub.T is a temperature depended figure known in the art and described e.g., in ›1! as

with k=1.38*10.sup.-23 Joule/Kelvin, e.sub.0 =1.60*10.sup.-19 Coulomb, and T the absolute temperature in Kelvin. For T=300K, V.sub.T is around 26 mV (millivolts). Voltage difference .DELTA.V appears as

across resistor 110 and drives a current .DELTA.V/R.sub.1. Voltage V.sub.R2 across resistor 120 is formed by the current .DELTA.V/R.sub.1 in resistor 110 according to:

Reference potential V.sub.BG at line 195 is:

or, using equations (3) and (6),

or, more simple written with X=(1+R.sub.2 /R.sub.1)*1n(Y),

The temperature dependence of equation (10) is obtained by forming the first deviation (dT/T) over the temperature T:

The first term V.sub.BE0 in (10) being approximately V.sub.BE0 =0.6 volts has a first, negative temperature coefficient TC.sub.1 =dV.sub.BE0 /dT of e.g., -2 millivolts/Kelvin. By choice of R.sub.1, R.sub.2, Y (M and N), the second term X*V.sub.T of (10) can have an temperature coefficient TC.sub.2 of e.g., +2 millivolts/Kelvin. Preferably, TC.sub.1 is related to TC.sub.2 by

with .apprxeq. for being substantially equal, .vertline. for absolute value, (-1) for opposite sign, and * for multiplication. Using equation (5), the second term of (10) X*V.sub.T is expressed as:

or in the deviation form for TC.sub.2 =2 millivolts/Kelvin

The value of X.apprxeq.23 is a convenient value for further discussions.

A noise voltage V.sub.N is superimposed on V.sub.BG. The noise voltage V.sub.N can result from e.g., thermal noise on resistors 110 (R.sub.1), 120 (R.sub.2), transistors 116 and 126. The noise voltage is related to R.sub.1 and R.sub.2 as approximated by:

with the .about. symbol for "proportional". However, for X=(1+R.sub.2 /R.sub.1)*1n(Y).apprxeq.23 it is inconvenient to reduce the ratio R.sub.2 /R.sub.1 to low values, because of a difficult implementation of high Y=M*N values in the 1n(Y) part (equation 3).

As known in the art, the noise voltage V.sub.N can be filtered out by external capacitor 150 having a capacity of e.g., between 1 to 100 nano farads. Such capacitors are difficult to integrate into circuit 100. As shown by dashed lines in the example of FIG. 1, external capacitor 150 is coupled between lines 195 (V.sub.BG) and 192 (GND). When circuit 100 is integrated, then external capacitor 150 is an external component which is not wanted for consuming e.g., space.

In another approach, Ahuja in FIG. 6 of ›2! and Ruszynak in ›5! show that transistors (such as e.g., Q.sub.i1 and Q.sub.i2 of FIG. 1) can be implemented by multiple transistors of the same type which are serially coupled ("stacked"). The voltage difference .DELTA.V is thereby enlarged. However, N serial coupled bases and emitters require a supply voltage (e.g., VCC) higher than N*V.sub.BE. This is, however, not suitable when VCC is a low voltage.

This invention seeks to provide a bandgap reference circuit which mitigates the above mentioned disadvantages.

FIG. 1 illustrates a simplified circuit diagram of a prior art bandgap reference circuit;

FIG. 2 illustrates a simplified circuit diagram of a bandgap reference circuit of the present invention;

FIG. 3 illustrates the present invention in general by a simplified circuit diagram of a transistor serially coupled with two resistors; and

FIG. 4 is a simplified circuit diagram of circuit of FIG. 2 in a preferred embodiment of the invention.

According to the present invention, a bandgap reference circuit has serially coupled transistors of alternate type (pnp-npn) to provide the voltage difference .DELTA.V. The Y-ratio providing different current densities is distributed over these transistors. In comparison to the prior art, the R.sub.2 /R.sub.1 resistance ratio can be decreased so that noise voltage V.sub.N is smaller and needs, preferably, no filtering by an external capacitor.

FIG. 2 illustrates a simplified circuit diagram of bandgap reference circuit 200 (hereinafter circuit 200) of the present invention. Circuit 200 is intended to be a non-limiting example. A person of skill in the art is able based on the following description to make changes without departing from the scope of the present invention.

Similarly to prior art circuit 100, circuit 200 comprises operational amplifier 230 ("op amp"), resistor 210 having a value of R.sub.1, resistor 220 with value R.sub.2, resistor 215 having value R.sub.C1, resistor 225 having value R.sub.C2, transistor 235 (also: Q.sub.0), transistor 216 (also: Q.sub.i1), transistor 226 (also: Q.sub.i2) and current source 260. Reference numbers 110/210, 111/211, 112/212, 115/215, 116/216, 120/220, 125/225, 126/226, 130/230, 131/132, 132/232, 133/233, 135/235, 136/236, 137/237, 138/238 and 160/260 denote similar components in FIGS. 1-2 whose function can, however, differ as explained below. The term `transistor` is intended to include any device having current and control electrodes, such as for example, bipolar devices. Other types of transistors can also be used. Transistors Q.sub.i1, Q.sub.i2, and Q(k) which will be explained later, provide voltages V.sub.BE are therefore convenient symbols for pn-junctions, so that these transistors can be replaced also by other components having pn-junctions, such as semiconductor diodes.

Circuit 200 also comprises a plurality of current sources 271, 272, 273, 274, 275, and 276 and a plurality of transistors 281, 282, 283, 284, 285, 286. Further, transistors 281-286 are referred to as Q(k) with k=1 to K=6.

Similarly as circuit 100, circuit 200 is coupled to a first potential VCC at line 291 and to a second potential e.g., GND at line 292. Circuit 200 provides a reference potential V.sub.BG at line 295. Potential V.sub.BG is, preferably, referred to the GND potential. In the example of FIG. 2, transistors Q.sub.i1, Q.sub.i2, and Q.sub.0 are bipolar transistors of negative-positive-negative (npn) type (e.g., "a first type") having, as illustrated representative for Q.sub.0, base 237 "B", emitter 238 "E", and collector 236 "C". For simplicity, transistors Q(k) are illustrated by circles which also represent voltage sources. The letters "B", "E" and "C" identify the control and current electrodes, respectively. In the example of FIG. 2, transistors Q(1) Q(2), Q(5) and Q(6) are, preferably, of a second or e.g., pnp-type. Transistors Q(3) and Q(4) are, preferably, of the first or e.g., npn-type.

Preferably, the VCC potential is positive compared to the GND potential. Connections of op amp 230 to lines 291 and 292 are well known in the art and not shown for simplicity.

Resistors 215 (R.sub.C1) and 225 (R.sub.C2) couple the collectors C of transistors 216 (Q.sub.i1) and 226 (Q.sub.i2), respectively, to line 291 (VCC). The emitters E of transistors 216 (Q.sub.i1) and 226 (Q.sub.i2) are coupled together to current source 260 which is itself coupled to line 292 (GND). The collector C of transistor 235 (Q.sub.0) is coupled to line 291. The emitter E of transistor 235 (Q.sub.0) is coupled at node 211 to line 292 via serially resistors 210 (R.sub.1), node 212, and 220 (R.sub.2). Collectors C of Q.sub.i1 and Q.sub.i2 are coupled to negative input 231 and positive input 232, respectively, of op amp 230. Output 233 of op amp 230 is coupled to the base B of Q.sub.0 and forms thereby line 295 (V.sub.BG).

Unlike prior art circuit 100, the emitter E of Q.sub.0 (node 211) is coupled to the base B of Q.sub.i2 via transistors Q(5), Q(3), and Q(1). Preferably, Q(5), Q(3), and Q(1) are serially coupled with node 211 to B of Q(5), E of Q(5) to B of Q(3), E of Q(3) to B of Q(1), E of Q(1) to B of Q.sub.i2. Node 212 is coupled to the base B of Q.sub.i1 via transistors Q(6), Q(4), and Q(2). Preferably, Q(6), Q(4), and Q(2) are serially coupled with node 212 to B of Q(6), E of Q(6) to B of Q(4), E of Q(4) to B of Q(2), and B of Q(2) to B of Q.sub.i1. The order of B and E is thereby not essential. Transistors Q(1) to Q (6) and Q.sub.i1 and Q.sub.i2 form thereby transistor chain 280. In some parts of chain 280, transistors Q(k) of first type (npn) and second type (pnp) are serially coupled in an alternate type configuration. For example, transistors Q(5), Q(3) and Q(1) form chain 280-1 of pnp/npn/pnp-types and transistors Q(6), Q(4), and Q(2) from chain 280-2 also of pnp/npn/pnp-types. For the purpose of explanation, the emitters E of transistors Q(1), Q(2), Q(5) and Q(6) are, preferably, coupled to line 291 via current sources 271, 272, 275, and 276, respectively. The collectors C of transistors Q(1), Q(2), Q(5) and Q(6) are, preferably, coupled to line 292. The emitters E of transistors Q(3) and Q(4) are, preferably, coupled to line 292 via current sources 273 and 274, respectively. The collectors C of transistors Q(3) and Q(4) are, preferably, coupled to line 291. Transistors Q(1) to Q(6) are, preferably, configured as emitter follower. To couple emitters E and collectors C between lines 292 and 291 in this way is convenient, but not essential for the present invention. It is only important, that current sources 271-276 drive transistors Q(1) to Q(6) at their current electrodes (e.g., E and C). In another classification, illustrated by dashed frames, transistors Q(1) and Q(2) form transistor pair 241, transistors Q(3) and Q(4) form transistor pair 242, and transistors Q(5) and Q(6) form transistor pair 243.

For further explanation, voltages, currents and other units are introduced. Similar to prior art circuit 100 of FIG. 1, V.sub.R1 is a voltage across resistor 210 (between nodes 211 and 212); V.sub.R2 is a voltage across resistor 220 (between node 212 and line 292); V.sub.BE0, V.sub.BEi1, and V.sub.BEi2 are voltages across bases (B) and emitters (E) of transistors Q.sub.0, Q.sub.i1, and Q.sub.i2, respectively. Currents I.sub.i1 and I.sub.i2 are generated by current source 260 and flow through collectors (C) and emitters (E) of transistors Q.sub.i1 and Q.sub.i2, respectively. For simplicity, base currents are neglected. A.sub.i1 and A.sub.i2 are the emitter areas of transistors Q.sub.i1 and Q.sub.i2, respectively and A.sub.k are the emitter areas of transistors Q(k). Voltages V.sub.BE1 to V.sub.BE6 are the base-emitter voltages of transistors Q(1) to Q(6). V.sub.BE3 and V.sub.BE4 for npn-type transistors Q(3) and Q(4) are positive, e.g., +0.6 volts and the other V.sub.BE1256 for pnp-type transistors Q(1), Q(2), Q(5), and Q(6) are negative, e.g., -0.6 volts. Current sources 271-276 provide emitter currents I.sub.1 to I.sub.6 of transistors Q(1) to Q(6).

As illustrated by an encircled uppercase letter M, the values R.sub.C2 and R.sub.C1 of resistors 225 and 215 are, preferably, in the ratio of:

with the slash/standing for division. As illustrated by encircled N, the emitter areas A.sub.i1 of Q.sub.i1 and A.sub.i2 of Q.sub.i2 are, preferably, related as:

Ratios M and N provide that currents I.sub.i1 and I.sub.i2 and current densities in Q.sub.i1 and Q.sub.i2 are different.

As illustrated by encircled uppercase letters H at current source 272, S at 273, and D at 276, currents I.sub.k of current sources 271-276 are, preferably related as:

As illustrated by encircled P at Q(1), U at Q(4), and L at Q(5), emitter areas A.sub.k are, preferably, related as:

For explanation, it is now assumed that currents I.sub.1, I.sub.4, I.sub.5, areas A.sub.2, A.sub.3, A.sub.6 (these with no encircled letters), have a magnitude of 1. With a current density in a transistor defined as current I.sub.k /area A.sub.k, the current densities of transistors Q.sub.i1, Q.sub.i2, Q(1) to Q(6) are now compared as:

.DELTA.V is now calculated by applying the mesh law as:

Taking into account the positive and negative values of V.sub.BEk, for different transistor types, equation (25) is given as:

In other words, .DELTA.V is a sum of base-emitter voltages V.sub.BEk (k=1 to K) ##EQU1## of serially coupled base and emitter electrodes of a plurality of transistors Q(k)(k=1 to K) partly having a different type (e.g., npn and pnp) so that some of said base-emitter voltages V.sub.BEk have different signs (.+-.1) and partly equalize each other.

In analogy to equation (4), .DELTA.V is obtained as:

The .PI. is the multiplication symbol and Y.sub.m stand for density ratios. For example, density ratios are Y.sub.0 for transistors Q.sub.i1 and Q.sub.i2, Y.sub.1 =P*H for transistor pair 241, Y.sub.2 =S*U for pair 242, and Y.sub.3 =L*D for pair 243. The total density ratio Y is distributed to substantially all of said plurality of transistors Q(k) and, preferably, also to Q.sub.i1 and Q.sub.i2.

Now, using equations (6), (7), (8) and (9) from the background section, V.sub.BG is obtained as

or, written with X=(1+R.sub.2 /R.sub.1)*1n(.PI.Y.sub.m),

This result is now compared to the prior art. It is now possible to obtain a high ratio Y so that the ratio R.sub.2 /R.sub.1 can be reduced. R.sub.2 /R.sub.1 is still responsible for the noise voltage V.sub.N. However, V.sub.N is reduced. Also, external capacitor 150 in prior art circuit 100 of FIG. 1 is no longer required. Although, transistors are coupled serially, circuit 200 does not require higher supply voltage (e.g., VCC). These features makes circuit 200 applicable for low voltage applications.

FIG. 3 illustrates the present invention in general by a simplified circuit diagram of transistor 235 serially coupled with resistors 210 (value R.sub.1) and 220 (value R.sub.2). Transistor 235 and resistors 210 and 220 have already been explained in connection with FIG. 2. Similarly to equation (27), voltage V.sub.R1 =.DELTA.V across resistor 210 is defined as a sum of .DELTA.V.sub.m (m=1 to M) of M transistor pairs m. ##EQU3##

Every transistor pair m, such as e.g., pairs 241-243 or Q.sub.i1 /Q.sub.i2 of FIG. 2, provides .DELTA.V.sub.m, such as for example, .DELTA.V.sub.1 =V.sub.BE1 -V.sub.BE2,.DELTA.V.sub.2 =V.sub.BE3 -V.sub.BE4, .DELTA.V.sub.3 =V.sub.BE5 -V.sub.BE6,.DELTA.V.sub.4 =V.sub.BEi1 -V.sub.BEi2. Every transistor pair has its current density ration Y.sub.m, explained in equation (30). Every base-emitter voltage difference .DELTA.V.sub.m causes a partial noise voltage V.sub.Nm. The partial noise voltages V.sub.Nm are not added linearly as .DELTA.V.sub.m, but added in a non-linear fashion to the above mentioned noise voltage V.sub.N : ##EQU4## with the supercript "2" at V.sub.Nm for square operation and the superscript "-1/2" symbol for square root operation. V.sub.N can be approximated for constant V.sub.Nm to:

Circuit 200 (FIGS. 2-3) of the present invention is now compared to prior art circuit 100 of FIG. 1. Continuing the discussion of equations (1) of (15) of the background section, convenient values of X.apprxeq.23 or, for simplicity of calculating X=24, can be calculated by varying parameters Y and R.sub.2 /R.sub.1 :

For circuit 100, convenient values are 1n(Y)=4, (Y.apprxeq.54) and R.sub.2 /R.sub.1 =5. While Y=M*N is limited by the different current densities of e.g., two transistors Q.sub.i1 and Q.sub.i2, resistor ratio R.sub.2 /R.sub.1 =5 remains high. In circuit 200 of the present invention, Y is distributed and can be increased to e.g., Y=4*4*4*4*4*4*4*4=65536 as explained in equations (16) to (33) with M, N, P, H, S, U, L, D =4. According to equation (35), ratio R.sub.2 /R.sub.1 is approximated as:

Assuming that, in circuit 100 and in circuit 200, every transistor pair generates an equal partial noise voltage V.sub.Nm. With equations (15) and (35) a ratio of noise voltages V.sub.N (200) of circuit 200 and V.sub.N (100) of prior art circuit 100 is calculated as: ##EQU5## As an advantage of the present invention, circuit 200 has 50% less output noise than prior art circuit 100.

FIG. 4 is a simplified circuit diagram of circuit 300 in a preferred embodiment of the invention. Circuit 300 is an implementation of circuit 200. Reference numbers 210/310, 211/311, 212/312, 215/315, 216/316, 220/320, 225/325, 226/326, 230/330, 231/331, 232/332, 235/335, 260/360, 271/371, 272/372, 273/373, 274/374, 275/375, 2761376, 281/381, 282/382, 283/383, 284/384, 285/385, 286/386, 291/391, 292/392, and 295/395 denote similar components in circuit 200 (FIG. 2) and circuit 300 (FIG. 4). However, their function can differ as explained below.

Circuit 300 comprises operational amplifier 330 ("op amp"), resistors 315 (value RC.sub.1), 325 (RC.sub.2), 310 (R.sub.1), and 320 (R.sub.2); npn-transistors 316 (also Q.sub.i1), 326 (Q.sub.i2), 335 (Q.sub.0) 383 (Q(3)), 384 (Q(4)), 360 (providing I.sub.i1 +I.sub.i2), 373 (providing I.sub.3) and 374 (providing I.sub.4); pnp-transistors 381 (Q(1)), 382 (Q(2)), 385 (Q(5)), 386 (Q(6)), 371 (providing I.sub.1), 372 (providing I.sub.2), 375 (providing I.sub.5), 376 (providing I.sub.6); nodes 311 and 312; first supply terminal 391 (at VCC), second supply terminal 392 (at GND), output terminal (for V.sub.BG), first bias terminal 393 (receiving V.sub.BIAS1) and second bias terminal 394 (receiving V.sub.BIAS2).

For convenience of explanation, collector (C or in plural Cs), emitter (E or Es) and base (B or Bs) electrodes of transistors 316, 326, 335, and 381-386 are abbreviated as, for example, C of Q.sub.i1 standing for a collector of npn-transistor 316. Resistors 315 is coupled to supply terminal 391 and to negative input 331 of op amp 330, Resistor 325 is coupled to terminal 391 and to positive input 332 of op amp 330. C of Q.sub.i1 is coupled to input 331 of op amp 330. C of Q.sub.i2 is coupled to input 332 of op amp 330. E of Q.sub.i1 and E of Q.sub.i2 are coupled together to C of 360. E of 360 is coupled to supply terminal 392. B of 360 is coupled to bias terminal 394. Output 333 of op amp 330 is coupled to output terminal 395 and to B of Q.sub.0. C of Q.sub.0 is coupled to supply terminal 391. E of Q.sub.0 is coupled to resistor 10 via node 311. Resistor 320 is serially coupled to resistor 310 at node 312 and is coupled to supply terminal 392.

Now, current paths k between terminals 391 and 392 are explained. These paths are in FIG. 4 illustrated vertically. Es of transistors 371, 372, 375, and 376 are coupled to supply terminal 391; and Es of transistors 373 and 374 are coupled supply terminal 392. Bs of transistors 371, 372, 375 and 376 are coupled to bias terminal 393; and Bs of transistors 373 and 374 are coupled to bias terminal 394. Cs of transistors 371-376 are coupled to E of Q(1)-Q(6), respectively. Cs of Q(1), Q(2), Q(5) and Q(6) are coupled to terminal 392; and Cs of Q(3) and Q(4) are coupled to terminal 391. In other words, a number of K=6 current paths k are coupled between terminals 391 and 392. Each current path k is formed by a serial combination of a first and a second transistor, such as e.g., path 1 by 371 and Q(1), path 2 by 372 and Q(2), path 3 by 373 and Q(3), path 4 by 374 and Q(4), path 5 by 375 and Q(5), and path 6 by 376 and Q(6). Preferably, first and second transistors are coupled in such a way that C of the first transistor (e.g., 371-376 is coupled to E of the second transistor (e.g., Q(1) to Q(6)). First transistors (e.g., 371-376) which receive bias voltages, such as, e.g., V.sub.BIAS1 for 371, 372, 375, and 376 and V.sub.BIAS2 for 373 and 374 operate as current sources (cf. 271-276 in FIG. 2) and provide currents I.sub.k (I.sub.1 to I.sub.6). First transistors (371) determine currents I.sub.k. Second transistors (Q(k)) are characterized by their emitter areas A.sub.k. A person of skill in the art is able to implement first and second transistors in such a way that current densities I.sub.k /A.sub.k second transistors Q(k) are different. Different current densities in second transistors (Q(k)) result in different base-emitter voltages V.sub.BEk of Q(k). The number of currents paths is, preferably, K=6, but other numbers, such as K=8, 10, 12, . . . or higher or odd numbers K can also be used.

Now, it is explained how the Bs and Es of Q.sub.i1, Q.sub.i2, and Q(k) are coupled to provide .DELTA.V across resistor 310. Connecting lines are shown in FIG. 4 horizontally. B of Q.sub.i2 is coupled to E of Q(1); B of Q(1) is coupled to E of Q(3); B of Q(3) is coupled to E of Q(5); and B of Q(5) is coupled to node 311. B of Q.sub.i1 is coupled to E of Q(2), B of Q(2) is coupled to E of Q(4); B of Q(4) is coupled to E of Q(6); and B of Q(6) is coupled to node 312.

The present invention which has been introduced by the examples of circuits 200 and 300 (FIGS. 2-4) is a bandgap reference circuit employing a voltage V.sub.BE which is added to a voltage difference .DELTA.V. V.sub.BE has a first temperature coefficient (e.g., TC.sub.1) and .DELTA.V has a second temperature coefficient (e.g., TC.sub.2). A plurality of K current paths k has current sources k (e.g., transistors 371-376) and pn-junctions k (e.g., between B-E of Q(k) ) with areas A.sub.k. Current sources and pn-junctions are serially coupled between supply terminals (e.g., between terminals 391 and 392). Current densities I.sub.k /A.sub.k in the pn-junctions k are different so that voltages V.sub.BEk across the pn-junctions k in each current path k are also different. The pn-junctions k of adjacent current paths k and k+1 are serially coupled, so that .DELTA.V=.SIGMA.V.sub.BEk (for k=1 to K). A first number K.sub.1 of pn-junctions are arranged in a first direction (e.g., with positive V.sub.BE) and a second number K.sub.2 of pn-junctions are arranged in a second, opposite direction (e.g., with negative V.sub.BE). Therefore, only the differences between V.sub.BEk (k of K.sub.1) and V.sub.BEk (k of K.sub.2) are added, wherein their absolute values .vertline.V.sub.BEk .vertline. are not added.

The first number K.sub.1 of pn-junctions in the first direction are, preferably, base-emitter (B-E) junctions of npn-transistors (e.g., first type) and the second number K.sub.2 of pn-junctions in the second direction are B-E junctions of pnp-transistors (e.g., second type). Preferably, the first number K.sub.1 is equal to the second number K.sub.2. K.sub.1 and K.sub.2 can have different values and can be related such as by K.sub.1 =K.sub.2 +2 or K.sub.2 =K.sub.1 +2. Circuit 300 in the example of FIG. 4, uses K.sub.1 =2 npn-transistors (Q(3) and Q(4)) and uses K.sub.2 =4 pnp-transistors (Q(1), Q(2), Q(5), Q(6)). This is convenient, but other configurations, such with K.sub.2 =4 (4 pnp-transistors) and K.sub.1 =2 (2 npn-transistors) are also possible to be implemented.

In the bandgap reference circuit of the present invention, the voltage difference .DELTA.V=V.sub.T *1n(Y), is obtained with Y=.PI.Y.sub.m (for m=1 to M,M.ltoreq.K/2). Y.sub.m can be considered as the current density ratio of pn-junction pairs, so that current densities are distributed over substantially all current paths.

In other words, the present invention can be described as a reference circuit which comprises a first portion for providing a first voltage (e.g., V.sub.BE0) with a first temperature coefficient TC.sub.1 and a second portion for providing a second voltage with a second, opposite temperature coefficient TC.sub.2. The first portion is formed by, e.g., transistor 235/335 in FIGS. 2-4 and the second portion is formed by, e.g., the other transistors, such as, e.g., by transistors Q.sub.i1, Q.sub.i2, Q(1), Q(k) to Q(K) (cf. chain 280 in FIG. 2) and current sources (e.g., 271-276/371-376). The second voltage (e.g., .DELTA.V) is added to the first voltage to output voltage V.sub.BG which is substantially temperature independent. The second portion has serially coupled transistors Q(k) of alternatively a first type (e.g., npn) and a second type (e.g., pnp). Transistors Q(k) have areas A.sub.k and carry currents I.sub.k, thus providing current densities I.sub.k /A.sub.k which are different so that each transistor Q(k) contributes to the second voltage (e.g., .DELTA.V) by a voltage V.sub.BEk between two of its electrodes (e.g., B and E). A person of skill in the art is able to modify circuit 300 without departing from the scope of the present invention. For example, he or she can use more than K=6 current paths.

As mentioned in the background section of this specification (equations 9 to 15), it is inconvenient to reduce the resistor ratio R.sub.2 /R.sub.1 to low values in a prior art circuit (e.g., circuit 100). Prior art circuits, such as, e.g., in ›5! and ›6! try to overcome this problem by stacking transistors which distribute current densities. However, absolute values of .vertline.V.sub.BE .vertline. are added so that such circuits require supply voltages which are a multiple of V.sub.BE. According to the present invention, pnp-transistors and npn-transistors, which are arranged in an alternating order, provide a voltage difference .DELTA.V from their different base-emitter voltages V.sub.BEk. Absolute values .vertline.V.sub.BEk .vertline. are substantially, not added. Circuits 200 and 300 use supply voltages between lines 291 and 292 which are in the range of V.sub.BE itself. These features make it possible to operate the circuit in a low voltage environment.

In circuit 200 of the present invention (and in its preferred embodiment 300), the ratio of R.sub.2 and R.sub.1 of resistors 220 and 210, respectively, is different and the total noise V.sub.N is reduced by e.g., 50%. Circuit 200 can be integrated on a monolithic chip without, e.g., an external filtering capacitor.

It will be appreciated that although only one particular embodiment of the invention has been described in detail, various modifications and improvements can be made by a person skilled in the art based on the teachings herein without departing from the scope of the present invention. Accordingly, it is the intention to include such modifications as will occur to those of skill in the art in the claims that follow.