PCI Card for Receiving a GPS Signal

1. Field of the Invention

The invention relates generally to peripheral component interconnect (PCI) cards for personal computers and more particularly to a PCI card for receiving a global positioning system (GPS) signal.

2. Description of the Prior Art

A personal computer (PC) is commonly used to process location, navigation, and timing data provided by a global positioning system (GPS) receiver. The GPS receiver downconverts a GPS satellite signal, correlates the downconverted signal against a replica signal, and computes GPS-derived data for location, navigation, and timing information from the correlation signal. The GPS-derived data is then issued to the PC using a convenient data signal interface format such as RS232, RS422, PC104, or PCMCIA. The PC processes and displays the GPS-derived data in a form that is useful for an application.

Existing GPS receivers include one or more memory chips for storing correlation and computation firmware and a microprocessor for executing the firmware to correlate the GPS signal and compute the GPS-derived data. Such GPS receivers are conceptually straightforward because they are self-contained and the communication with the PC is simple and well-defined. However, the use of the memory chips and microprocessor in the GPS receiver is wasteful because the PC must include memory and processing power in any case. Further, due to the recent advances in custom GPS chipsets, the cost of the memory chips and microprocessor in the GPS receiver are a major portion of the cost of an entire GPS receiver. Unfortunately, little or no effort has been made to use the memory and processing power in the PC to reduce or eliminate the cost of memory chips and/or microprocessor in the GPS receiver because of the conceptual complexity of such GPS receiver and because the convenient data signal interface formats are too slow to pass the downconverted signal and/or the correlation signal between the GPS receiver and the PC.

Recently, a peripheral component interconnect (PCI) bus has been used to interface high speed signals between the PC and an embedded PCI card for full-motion video editing and serving. The PCI bus provides a data path capable of accessing up to 264 megabytes of data per second. In addition to being optimized for high bandwidth, the PCI bus also addresses cache coherency, multiple bus master support, and processor independence. Commercial PCI bus bridges are now available for interfacing to the PCI bus.

It is therefore an object of the present invention to provide a peripheral component interconnect (PCI) global positioning system (GPS) downconverter card for receiving a GPS signal and issuing a downconverted GPS signal according to a PCI bus format.

Another object is to integrate a PCI GPS downconverter card for downconverting a GPS signal with a host personal computer (PC) for correlating the downconverted GPS signal and computing GPS-derived information for location, navigation, or timing.

Another object is to provide a PCI GPS correlator card for receiving a GPS signal and issuing a GPS correlation signal according to a PCI bus format.

Another object is to integrate a PCI GPS correlator card for downconverting and correlating a GPS signal to a host PC for computing GPS-derived information for location, navigation, or timing.

Briefly, in a first embodiment of the present invention a PCI GPS downconverter card includes a GPS downconverter and a PCI bus bridge. In a second embodiment of the present invention a GPS receiver includes the PCI GPS downconverter card and a host PC including a host PCI bus bridge and an executable code including a correlation program and a location, navigation, and timing (LNT) program. In a third embodiment of the present invention a PCI GPS correlator card includes a GPS downconverter, a GPS correlator, and a PCI bus bridge. In a fourth embodiment of the present invention a GPS receiver includes the PCI GPS correlator card and a host PC including a host PCI bus bridge and an executable code including an LNT program.

An advantage of the present invention is that the PCI GPS downconverter card issues a downconverted GPS signal in a PCI bus format allowing for further processing in a host PC.

Another advantage is that the GPS receiver uses a microprocessor and memory in a host PC for correlating a downconverted GPS signal and computing GPS-derived information, thereby reducing the cost of the GPS receiver.

Another advantage is that the PCI GPS correlator card issues a GPS correlation signal in a PCI bus format allowing for further processing in a host PC.

Another advantage is that the GPS receiver uses a microprocessor and memory in a host PC for computing GPS-derived information, thereby reducing the cost of the GPS receiver.

These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various figures.

FIG. 1 is a block diagram of a personal component interconnect (PCI) global positioning system (GPS) downconverter card of the present invention;

FIG. 2 is a block diagram of the present invention of a GPS receiver including the PCI GPS downconverter card of FIG. 1 integrated into a personal computer (PC);

FIG. 3 is a block diagram of a PCI GPS correlator card of the present invention; and

FIG. 4 is a block diagram of the present invention of a GPS receiver including the PCI GPS correlator card of FIG. 3 integrated into a personal computer (PC).

FIG. 1 illustrates a personal component interconnect (PCI) global positioning system (GPS) downconverter card of the present invention and referred to by the general reference number 10. The PCI GPS downconverter card 10 preferably includes a low noise amplifier 12 for receiving a conducted electrical GPS signal including GPS location determination data from a GPS antenna. The low noise amplifier 12 passes an amplified GPS signal to a GPS frequency downconverter 14. The GPS frequency downconverter 14 uses a local oscillator signal from a local oscillator 16 to downconvert the frequency of the GPS signal and issues a downconverted GPS signal. A quantizer 18 samples the downconverted GPS signal at a rising or falling edge of a reference clock signal from a reference clock oscillator 20 and issues a bit stream for the downconverted signal including an I bit stream representing two or more levels of inphase modulation in the GPS signal and a Q bit stream representing two or more levels of quadrature phase modulation in the GPS signal. Preferably, the local oscillator 16 includes a phase lock loop to lock the local oscillator signal to the reference clock signal. A PCI bus bridge 22 caches the I and Q bits in a memory 24 and passes the bits, representative of the GPS location determination data, to a PCI bus 26 when authorized over the PCI bus 26 to do so.

Several U.S. Patents teach apparatus and methods for downconverting and correlating the GPS signal. U.S. Pat. No. 4,754,465 for a "Global Positioning System Course Acquisition Code Receiver" by Trimble, incorporated herein by reference, discloses a representative example of a GPS downconverter. U.S. Pat. No. 5,390,207 by Fenton et al. for a "Pseudorandom Noise Ranging Receiver Which Compensates for Multipath Distortion by Dynamically Adjusting the Time Delay Spacing between Early and Late Correlators", U.S. Pat. No. 5,402,450 by Lennon for a "Signal Timing Synchronizer", and U.S. Pat. No. 5,414,729 by Fenton for a "Pseudorandom Noise Ranging Receiver Which Compensates for Multipath Distortion by Making Use of Multiple Correlator Time Delay Spacing", incorporated herein by reference, teach various apparatus and methods for correlating to the GPS signal.

FIG. 2 illustrates a global positioning system (GPS) receiver of the present invention and referred to by the general reference number 40 and including the PCI GPS downconverter card 10 of the FIG. 1 coupled to the PCI bus 26. The GPS receiver 40 includes a host personal computer (PC) 44 including a processor 46 including various associated hardware, a memory 48 including an executable code 50 and variable data 52, and input/output hardware 54 operating on a host bus 55 in a conventional manner. The input/output hardware 54 includes circuitry for communicating to external equipment over serial and/or parallel interfaces. Typically, the memory 48 includes one or more read only memory chips for storing a BIOS program, a dynamic ram for storing variable data 52 including cache data, a hard disk drive and hard disk, and one or more soft disk drives where soft disk memories may be inserted. The host PC 44 further includes a PCI bus bridge 56, including a memory 58, for converting between PC-formatted signals on the PCI bus 26 and host bus signals on the host bus 55. The executable code 50 includes code for authorizing the card PCI bus bridge 22 (FIG. 1) and receiving the bits for the downconverted GPS signal from the PCI bus 26 through the PCI bus bridge 56. The executable code 50 further includes a correlation program 60 for providing a GPS replica and correlating the downconverted GPS signal to the GPS replica to provide correlation data. A location, navigation, or timing (LNT) program 62, included in the executable code 50, operates on the correlation data to compute GPS-derived location, navigation, or timing information. A keyboard 64 receives requests from a user for operating the PC 44. A display 66 displays information including the GPS-derived location to the user in a visually perceptible form.

FIG. 3 illustrates a personal component interconnect (PCI) global positioning system (GPS) correlator card of the present invention and referred to by the general reference number 100. The PCI GPS correlator card 100 preferably includes a low noise amplifier 102 for receiving a conducted electrical GPS signal including location determination data from a GPS antenna. The low noise amplifier 102 passes an amplified GPS signal to a GPS frequency downconverter 104. The GPS frequency downconverter 104 uses a local oscillator signal from a local oscillator 106 to downconvert the frequency of the GPS signal and issues a downconverted GPS signal. A quantizer 108 samples the downconverted GPS signal at a rising or falling edge of a reference clock signal from a reference clock oscillator 110 and issues a quantized GPS signal to at least one correlator 112. Preferably, the local oscillator 106 includes a phase lock loop to lock the local oscillator signal to the reference clock signal. The correlator 112 receives a GPS replica signal from a replica generator 114 and provides a correlator output signal including correlation data to a PCI bus bridge 122 for a correlation of the quantized GPS signal and the GPS replica signal. The replica generator 114 uses the reference clock signal and receives adjustment data for adjusting a PRN code, a rate, and a timing to acquire and track the GPS signal. Preferably, the correlation data is organized into at least two 1023 bit words corresponding to the correlation data of 1023 bits in each of the I channel and Q channel of the GPS signal with the 1023 bits in each of the I and Q channels of the replica signal. The PCI bus bridge 122 caches the bits in a memory 124 and passes the words, representative of the GPS location determination data, to a PCI bus 126 when authorized over the PCI bus 126 to do so. The PCI bus 126 issues a feedback adjustment signal including the adjustment data to the PCI bus bridge 122. The PCI bus bridge 122 passes the adjustment data to the replica generator 114.

FIG. 4 illustrates a global positioning system (GPS) receiver of the present invention and referred to by the general reference number 140 including the PCI GPS correlator card 100 coupled to the PCI bus 126. The GPS receiver 140 includes a host personal computer (PC) 144 including a processor 146 including associated hardware, a memory 148 including an executable code 150 and variable data 152, and input/output hardware 154 operating on a host bus 155 in a conventional manner. The input/output hardware 154 includes circuitry for communicating to external equipment over serial and/or parallel interfaces. Typically, the memory 148 includes one or more read only memory chips for storing a BIOS program, a dynamic ram for storing variable data 152 including cache memory, a hard disk drive and hard disk, and one or more soft disk drives where soft disk memories may be inserted. The host PC 144 further includes a PCI bus bridge 156, including a memory 158, for converting between PCI-formatted signals on the PCI bus 126 and host bus signals on the host bus 155. The executable code 150 includes code for authorizing the card PCI bus bridge 122 (FIG. 3) to pass the words for the correlation data across the PCI bus 126 through the PCI bus bridge 156. The executable code 150 further includes a feedback adjustment program 160 for providing adjustment data for changing the rate, the timing, and the PRN code to cause the GPS replica signal generating by the replica generator 114 (FIG. 3) to acquire and to track the GPS signal. The executable code 150 further includes a location, navigation, or timing (LNT) code 162 for operating on the correlation data to compute GPS-derived location, navigation, or timing information. Because the correlator output signal has a lower baud rate than the downconverted GPS signal, the processor 146 can operate at a lower instruction rate or allocate of smaller percentage of time for processing GPS than the processor 46 (FIG. 2). A keyboard 164 receives requests from a user for operating the PC 144. A display 166 displays information including the GPS-derived location to the user in a visually perceptible form.

The characteristics and operation of the PCI bus 26 (FIG. 2) and 126 (FIG. 4) are described in "PCI Hardware and Software Architecture and Design" pages 1 to 749, by Edward Solari and George Willse published by Annabooks of San Diego, Calif., ISBN 0-929392-28-0, second edition in 1994 and 1995. Several commercially available parts are available for use as the PCI bus bridge 22 (FIG. 1), 56 (FIG. 2), 122 (FIG. 3), and 126 (FIG. 4) including a Xilinx model XC7300 EPLD described in "Designing Flexible PCI Interfaces With Xilinx EPLDs" available from Xilinx, Inc., San Diego, Calif., under a part no. 0010216-02; an AMCC series S5930-S5933 described in "AMCC S5930-S5933 PCI Controllers, PCI Local Bus, Matchmaker PCI Controllers" available from Applied Micro Circuits Corporation of San Diego, Calif.; and Altera MAX7000, FLEX8000, FLEX9000, and FLASHlogic model series' described in "PCI Compliance of Altera Devices, Application Brief 140, May 1995, ver. 2", "Ride the PCI Bus with Altera CPLDs" published in 1995, and "PCI Compliance Checklist EPM7160E-10P" available from Altera Corporation, San Jose, Calif.

Methods and apparatus for operating according to the PCI format are included in U.S. Pat. No. 5,396,602 for "Arbitration Logic for Multiple Bus Computer System" by Amini et al., U.S. Pat No. 5,446,869 for "Configuration and RAM/ROM Control of PCI Extension Card Residing on MCA Adapter Card" by Padgett et al., U.S. Pat. No. 5,448,703 for "Method and Apparatus for Providing Back-to-Back Data Transfers in an Information Handling System Having a Multiplexed Bus" by Amini et al., U.S. Pat. No. 5,448,704 for "Method for Performing Writes of Non-Contiguous Bytes on a PCI Bus in a Minimum Number of Write Cycles" by Spaniol et al., and U.S. Pat. No. 5,450,551 "System Direct Memory Access (DMA) Support Logic for PCI Based Computer System" by Amini et al., the teachings of which are incorporated herein by reference.

Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that such disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.