US 5,828,558 AGrant
PWN Controller Use With Open Loop Flyback Type DC to AC Converter
Issue Date:1998-10-27
•40 Claims
•10 Drawing Sheets
Abstract
A controller and ring generator circuit realized therefrom utilizing an open loop flyback topology to achieve a desired output voltage waveform. A characteristic feature of the controller is that it provides the required signals to control a ring generator circuit having an open loop fly back topology. The controller functions to generate a PWM signal that is used to switch the primary of a transformer on and off. The controller includes the necessary functionality to control the duty cycle of the generated PWM signal so as to produce a sine wave output on the secondary of the transformer. The controller also includes overcurrent protection circuitry that tracks the load current by sensing the current through the primary winding. In addition, the circuit permits negative current in the secondary by use of a synchronous rectifier circuit coupled to an additional secondary transformer winding. An output bridge circuit creates a full sine wave from the generated half wave output.
Metadata
Assignee
- Powerdsine, Ltd.
Inventors
- Dror Korcharz
- Alon Ferentz
Application Information
Application Number:US 022281&
Filing Date:1998-02-11
Priority Date:1998-02-11
Art Unit:288
Classifications
IPC:
H02M 3335
Field of Search:
36337920;21;15;16;17;40;41;131;132;89;95;98164;252;253;418;324;413
Patent Drawings (10 sheets)
Description
FIELD OF THE INVENTION
The present invention relates generally to PWM controllers and more particularly relates to a PWM controller suitable for use with open loop DC to AC converters having flyback topology.
BACKGROUND OF THE INVENTION
DC to AC converters such as ring generators are well known devices in common use today for providing the ringing signals used to ring a standard telephone. Telephone service providers employ them to generate the standard ringing tone sent to the telephone(s) installed at the customer's premises. In addition, manufacturers of telephone PBX equipment employ ring generators to provide the ringing signals used to ring the extension telephone sets connected to the PBX equipment.
Typical ring generators are designed to provide sinusoidal or substantially sinusoidal waveforms. Smaller telephone systems, e.g., small loop carrier systems, PBX or key systems, generally make use of electronic ringing techniques as opposed to designs employing large iron core transformers. These smaller systems are typically required to be able to ring a large percentage of the lines simultaneously.
Further, more and more optical fiber is being introduced into the telephone loop plant which the associated increased need for small, reasonably efficient ring generators having well controlled sinusoidal output waveforms. Systems such as fiber to the curb (FTTC) typically serve four residences and may provide up to 12 telephone channels. Fiber to the home (FTTH) systems serve only one residence and typically provide less than three telephone channels. These and other related telephone systems are required to provide a source of ringing which is capable of ringing up to three line simultaneously. In addition, each line may have as many as five ringers associated with it. The output of the ring generator device must be sufficient to drive each of the ringers on all the supported telephone lines with reasonable efficiency and must maintain a sinusoidal wave shape.
In addition, the ring generator device must be able to be powered from power sources of varying input voltage, such as the commonly found voltages of 5, 12, 24 or 48 Vdc. The power consumption of such a device should be limited so as not to draw excess power and deprive other power supplies in the system of sufficient power to operate satisfactorily. The ring generator device should also be capable of being subjected to overcurrent, i.e., low resistance fault, and short circuit conditions without being sustaining permanent damage. If the device is subjected to an overload due to an excessive number of ringers being rung simultaneously, it must continue to operate and output a sinusoidal waveform, even if it must reduce the output voltage to a point that is not sufficient to ring the excessive ringer load.
SUMMARY OF THE INVENTION
The present invention discloses a PWM controller and DC to AC converter circuit realized therefrom that utilizes an open loop flyback topology. For illustration purposes, the invention is presented within the context of an open loop flyback type ring generator circuit. However, the application of the PWM controller of the present invention is not limited to ring generators but can be adapted to control any other type of DC to AC converter having an open loop flyback topology.
A characteristic feature of the controller is that it provides the required signals to control a ring generator circuit having an open loop fly back topology. The controller functions to generate a PWM signal that is used to switch the primary of a transformer on and off. The controller includes the necessary functionality to control the duty cycle of the generated PWM signal so as to produce a sine wave output on the secondary of the transformer. The controller also includes overcurrent protection circuitry that tracks the power through the output load by sensing the current through the primary winding. In addition, the circuit permits negative current in the secondary by use of a synchronous rectifier circuit coupled to an additional secondary transformer winding. An output bridge circuit creates a full sine wave from the generated half wave output.
The controller functions to implement the well known equation for the transfer function of a flyback transformer circuit in continuous mode as given by ##EQU1## where
V.sub.OUT =desired output voltage
V.sub.IN =input voltage
N=turns ratio between the primary and the secondary in the transformer
The above equation gives an expression for D the duty cycle of the PWM signal generated by the controller. The values on the right hand side of the equal sign are known, thus the value D can be calculated, thus achieving an open loop configuration. The turns ratio N is determined beforehand and the output voltage V.sub.OUT is the desired sine function, which can be generated by any well known means such as a ROM or synchronous state machine. In addition, V.sub.IN can be sampled and included in the equation.
The overcurrent protection means in the controller, is operative to sense the current flowing through the primary of the transformer. When the current exceeds a predetermined threshold, an internal up/down counter is incremented increasing the value of a protection constant which the value for the turns ratio N is multiplied by. This causes the output voltage to decrease until the overcurrent condition is eliminated. This is equivalent to increasing the turns ratio, which effectively shortens the duty cycle, which would yield a lower output voltage if it were not for the larger turns ratio.
The primary characteristics of the ring generator controller and the ring generator circuit of the present invention are (1) that the ring generator operates in an open loop topology as opposed to traditional closed loop design, (2) that the circuit generates an AC sine wave from a DC input, (3) that the resultant circuit is relatively simple and inexpensive to manufacture and (4) that the resultant control circuit can be realized in an ASIC.
The circuit can operate with various input voltages V.sub.IN such as 5, 12, 24 and 48 Vdc. The amplitude of the generated sine wave output voltage V.sub.OUT can vary from 50 to 90 Vrms and is stable despite changes in V.sub.IN. Further, the output voltage V.sub.OUT and can have any of the various frequencies in use by the telecommunication systems around the world including but not limited to 17, 20, 25 and 50 Hz. The circuit also comprises inhibit means with functions to shut down the output and reduce the current consumption of the circuit. The inhibit means comprises an internal synchronization circuit to delay the inhibit action until the output ringing signal reaches the zero level.
There is therefore provided in accordance with the present invention a controller suitable for controlling an open loop flyback DC to AC converter circuit, the circuit including a transformer having a primary and a secondary, the controller comprising sampling means for generating a digital number representative of the magnitude of a source of DC electrical power, sine generator means for generating a digital representation of a sinusoidal waveform, processing means for determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU2## wherein
D=duty cycle of PWM signal
N=turns ratio of the transformer
V.sub.IN =voltage level of the source of DC electrical power
V.sub.OUT =digital representation of a sinusoidal waveform
and pulse width modulation means for generating the PWM signal in response to the duty cycle generated by the processing means.
The sampling means may comprise A/D converter means or comparator means for comparing the magnitude of the source of DC electrical power with a converter signal, a counter responsive to the output of the comparator means, converter means for generating the converter signal in response to the output of the counter and a latch for periodically latching the output of the counter.
The comparator means may comprise a voltage divider coupled to the source of DC electrical power, filter means for low pass filtering the converter signal and a comparator for comparing the output of the voltage divider and the output of the filter means and generating an compare signal therefrom. In addition, the sine generator means can comprise counting means coupled to look up table means or synchronous state machine means.
The processing means comprises a multiplier for generating the product N.multidot.V.sub.IN, an adder for generating the sum N.multidot.V.sub.IN +V.sub.OUT and a divider for dividing V.sub.OUT by the sum. Further, the controller further comprises synchronization means for generating a sequence of pulses in response to both the positive and negative zero crossings of the output sine wave.
The controller comprises overcurrent protection means operative to reduce the duty cycle of the PWM signal in response to an overcurrent condition in the output of the circuit and is also operative to shut down the pulse width modulation means in response to a severe current overload or short circuit applied to the output of the circuit.
The controller comprises bridge control means for generating a bridge control signal for converting a half wave sine function to a full wave sine function, the bridge control signal having the same frequency as the sine wave output by the circuit. In addition, controller comprises buffer means coupled to the output of the pulse width modulation means, the buffer means for generating an output PWM signal with suitable drive and load characteristics.
There is also provided in accordance with the present invention a controller for controlling the operation of a DC to AC converter circuit, the circuit connected to a source of DC electrical power and having an open loop flyback topology including a transformer having a primary winding and a secondary winding, a switch coupled to the primary winding and an output bridge circuit, the controller comprising sampling means for generating a digital representation of the voltage level of the source of DC electrical power, sine generator means for generating a digital representation of a sinusoidal waveform, processing means for determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU3## wherein
D=duty cycle of PWM signal
N=turns ratio of the transformer
V.sub.IN =voltage level of the source of DC electrical power
V.sub.OUT =digital representation of a sinusoidal waveform
and pulse width modulation means for generating the PWM signal in response to the duty cycle generated by the processing means, the PWM signal output by the controller and input to the switch and bridge control means for generating a bridge control signal output by the controller and input to the output bridge circuit, the output bridge circuit operative to convert a half wave sine function to a full wave sine function subsequently output by the circuit.
The controller further comprises overcurrent protection means operative to reduce the duty cycle of the PWM signal in response to an overcurrent condition in the output of the circuit. The overcurrent protection means comprises pulse counting means for counting pulses in response to the current in the primary exceeding a predetermined threshold and generating UP and DOWN signals in accordance thereto, up/down counter means for incrementing and decrementing a counter in response to the UP and DOWN signals, respectively, wherein the processing means is adapted to receive and process the output of the up/down counter such that the duty cycle of the PWM signal is adjusted in accordance therewith.
Further, there is provided in accordance with the present invention a method of controlling a DC to AC converter circuit having an open loop flyback topology, the circuit including a transformer having a primary and a secondary, the method comprising the steps of generating a digital number representative of the magnitude of a source of DC electrical power, generating a digital representation of a sinusoidal waveform, determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU4## wherein
D=duty cycle of PWM signal
N=turns ratio of the transformer
V.sub.IN =voltage level of the source of DC electrical power
V.sub.OUT =digital representation of a sinusoidal waveform
and generating the PWM signal in response to the duty cycle generated by the processing means.
The step of generating a digital number comprises comparing the magnitude of the source of DC electrical power with a converter signal and maintaining a count in response thereto, generating the converter signal in response to the magnitude of the count and periodically latching the value of the count. The step of comparing comprises dividing the source of DC electrical power to generate a divided voltage, low pass filtering the converter signal and generating a filtered signal therefrom and comparing the divided voltage with and the filtered signal and generating a compare signal therefrom.
Also, the step of determining comprises generating the product N.multidot.V.sub.IN, generating the sum N.multidot.V.sub.IN +V.sub.OUT and dividing V.sub.OUT by the sum. The method further comprises the step of generating a sequence of pulses in response to both the positive and negative zero crossings of the output sine wave. The method also comprises the step of reducing the duty cycle of the PWM signal in response to an overcurrent condition in the output of the circuit.
The method further comprises the step of suspending the generation of the PWM signal in response to a severe current overload or short circuit applied to the output of the circuit. The method further comprises the step converting a half wave sine function to a full wave sine function.
In addition, there is provided in accordance with the present invention a method of controlling a DC to DC converter circuit having an open loop flyback topology, the circuit including a transformer having a primary and a secondary, the method comprising the steps of generating a digital number representative of the magnitude of a source of DC electrical power, generating a digital representation of the desired output voltage, determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU5## wherein
D=duty cycle of PWM signal
N=turns ratio of the transformer
V.sub.IN =voltage level of the source of DC electrical power
V.sub.OUT =digital representation of the desired output voltage
and generating the PWM signal in response to the duty cycle generated by the processing means.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
FIG. 1 is a high level schematic diagram of a ring generator circuit presented to illustrate the principles of the present invention;
FIG. 2A is a graph illustrating the current through the primary and the secondary winding of the transformer when operating in continuous mode;
FIG. 2B is a graph illustrating the current through the primary and the secondary winding of the transformer when operating with no load and exhibiting an interruption in current flow, i.e., non continuous mode;
FIG. 2C is a graph illustrating the current through the primary and the secondary winding of the transformer when operating with a synchronous rectifier in the secondary;
FIG. 3 is a high level block diagram illustrating the ring generator controller of the present invention;
FIG. 4 is a block diagram illustrating the ring generator controller of the present invention in more detail;
FIG. 5 is a block diagram illustrating the pulse count circuitry in more detail;
FIG. 6 is a schematic diagram illustrating a ring generator circuit constructed in accordance with an embodiment of the present invention;
FIG. 7 is a graph illustrating the voltage V.sub.DS of transistor Q.sub.1 and the current I.sub.1 during the periods when Q.sub.1 is ON and OFF;
FIG. 8 is a graph illustrating the voltage V.sub.D across the series combination of diodes 202, 204 and the current I.sub.2 during the periods when Q.sub.1 is ON and OFF;
FIG. 9 is a graph illustrating the voltage V.sub.GS of transistor Q.sub.1 and the current I.sub.1 during the periods when Q.sub.1 is OFF and ON;
FIG. 10 is a schematic block diagram illustrating the A/D converter and associated circuitry is more detail;
FIG. 11A is a diagram illustrating the half wave rectified sinusoidal waveform generated by the ring generator circuit at the input to the output bridge circuitry;
FIG. 11B is a diagram illustrating the half wave rectified sinusoidal waveform of FIG. 11A in more detail highlighting the varying widths of the controller PWM output pulses used to generate the output waveform; and
FIG. 12 is a schematic diagram illustrating the output bridge circuitry in more detail.
DETAILED DESCRIPTION OF THE INVENTION
Notation Used Throughout
The following notation is used throughout this document.
General Description
The present invention comprises a PWM controller suitable for realizing a DC to AC converter having an open loop fly back topology. A characteristic feature of the controller is that is provides the necessary circuitry to control the duty cycle of a PWM signal as a function of input voltage, transformer turns ratio and desired output voltage. Both the controller itself and an example ring generator circuit constructed therefrom are presented and described in detail. The ring generator circuit of the type disclosed herein has applications to various communication systems such as PBXs, key systems, facsimile switching, CTI equipment, rural telephony, satellite telephony, VSAT terminal and wireless local loop telephone systems.
The ring generator controller of the present invention has been embodied in an ASIC and is commercially available as Part No. PD5019 manufactured by PowerDsine Ltd., Petach Tikva, Israel. A family of ring generator circuits, Part Nos. PD22xx, PD21xx and PD23xx, embodying the ring generator controller of the present invention is commercially available as well from the above mentioned company.
To aid in understanding the principles of the controller of the present invention, a simplified ring generator circuit is presented in FIG. 1. This simplified ring generator circuit, generally referenced 90, comprises a transformer 72 having a primary winding 74 and a secondary winding 76. The primary is coupled to a ring generator controller, generally referenced 10 and FET 88, capacitor 70. The secondary is coupled to a diode 82, synchronous rectifier 80, capacitor 84 and output bridge circuit 86.
The primary characteristics of the controller and corresponding ring generator circuit of the present invention are (1) that the circuit operates in an open loop topology as opposed to traditional closed loop design, (2) that the circuit is operative to generate an AC sine wave from DC, (3) that the resultant circuit is simple and inexpensive to manufacture and (4) that the resultant control circuit can optionally be realizable in an ASIC.
With reference to FIG. 1, the controller 10 functions to sample the input voltage V.sub.IN and to generate the drive signal for switch (FET) 88. It will be appreciated by those skilled in the art that circuit 90 has an open loop flyback topology with no feedback from the output voltage V.sub.OUT. The controller 10 generates a pulse width modulated (PWM) signal to switch the FET 88 on and off such that a rectified half sine wave is generated at the input to the output bridge circuit 86. The output bridge circuit 86 functions to generate a full output sine wave from the rectified sine wave input thereto.
The circuit can operate with various input voltages V.sub.IN including but not limited to 5, 12, 24 and 48 Vdc. The amplitude of the generated sine wave output voltage V.sub.OUT can vary from 50 to 90 Vrms with other voltage ranges also possible. In addition, the output voltage can have any of the various frequencies in use by the telecommunication systems around the world including but not limited to 17, 20, 25 and 50 Hz. The circuit also comprises inhibit means with functions to shut down the output and reduce the current consumption of the circuit. The inhibit means comprises an internal synchronization circuit to delay the inhibit action until the output ringing signal reaches the zero level.
The circuit also comprises overcurrent protection means which is activated when the input current exceeds a predetermined threshold. The overcurrent protection means comprises circuitry that limits the input current in order to avoid excessive current being applied to the ringer circuitry and also excessive current being output from the portion of the power generation circuitry that feeds the output bridge circuitry, thus preventing damage to the ring generator circuit. The controller functions to generate the proper peak amplitude in the secondary so as to avoid clipping the peak of the output sine wave. If the overcurrent condition is severe, the protection means will disconnect the ringer within 800 ms and will activate the ring generator after an arbitrary delay, e.g., 5 seconds. During this period, the ringer current consumption is reduced to a low level. When the overload or short circuit is removed, the ringer automatically resumes normal operation after a certain time period.
The operation of circuit 90 will now be described in more detail. As discussed previously, the circuit functions to generate a half sine wave signal, which the output bridge circuit 86 converts into the full sine wave output signal V.sub.OUT, in open loop fashion with no sampling of the output signal. This is achieved by utilizing the well known transfer function for a flyback circuit. The transfer function of the circuit, in combination with known entities in the circuit, is used to calculate the duty cycle of the switching signal applied to the switch 88. The transfer (or transmission) function relates the output voltage as a function of the duty cycle, input voltage and the ratio of the primary winding and the secondary winding, and is expressed in the following equation ##EQU6## and
V.sub.OUT =half sine wave output voltage
V.sub.IN =input voltage
N=turns ratio
N.sub.1 =number of turns on the primary winding
N.sub.2 =number of turns on the secondary winding
D=duty cycle of the PWM signal input to the switch
Thus, the output voltage V.sub.OUT can be expressed as ##EQU7##
It is important to note that the above equation for the transfer function is valid only when the current through the transformer 72 is continuous. Thus, during each and every cycle of the circuit, a loop of current must flow either in the primary winding 74 or the secondary winding 76, thus maintaining a flow of current through the transformer 72.
Considering the above transfer function, all the entities with the exception of the duty cycle can be determined beforehand. The output voltage V.sub.OUT is a known entity, even though it is the voltage that the circuit is generating. The input voltage V.sub.IN is also known as it can be periodically sampled. Further, the turns ratio N can be predetermined and thus known for a particular application. The only entity not known or predetermined is the duty cycle D which must be calculated each cycle. Thus, solving the above equation for D yields ##EQU8##
Thus, the controller 10, functions to calculate during each cycle, the duty cycle D which is used to adjust accordingly, the pulse width of the switching signal applied to the gate of the FET 88.
As previously stated, the above equation is only valid if the current through the transformer 72 is continuous. The current through both the primary 74 and the secondary 76 is determined, among other things, by the switching signal applied to the switch 88, by the circuitry coupled to the secondary and by the load (if any) placed either at the input to the output bridge circuit 86 or at the output.
Continuous current through the transformer can be achieved by one of two methods. The first is to place a minimum load in the secondary circuit and the second is to use what is known as a synchronous rectifier or synchronous diode circuit. A graph illustrating the current through the primary and the secondary winding of the transformer when a load is placed in the secondary is shown in FIG. 2A. The current through the transformer 72 is shown for one cycle of the circuit having a period T. The time period T.sub.ON represents the time the switch 88 is on and T.sub.OFF represents the time the switch is off. The controller 10 functions to generate a PWM signal to drive switch 88 having a duty cycle that is determined in accordance with the above described equation.
Curve 20 depicts the current I.sub.1 flowing through the primary when the switch 88 is on and curve 22 depicts the current I.sub.2 flowing though secondary when the switch is off. The current traces in FIG. 2A represent the case when continuous current through the transformer is achieved by placing a minimum bleeder load in the secondary circuit. As can be seen, the load creates a DC level which is wasteful of energy and makes the circuit inefficient. As the bleeder load increases, the DC level increases which makes the circuit even more inefficient.
A graph illustrating the current through the primary and the secondary winding of the transformer when operating with no bleeder or other type of load is shown in FIG. 2B. Curve 30 depicts the current I.sub.1 flowing through the primary when the switch 88 is on and curve 32 depicts the current I.sub.2 flowing though secondary when the switch is off. These current curves represent the case where no synchronous diode or bleeder load is utilized in the circuit. Thus, with reference to FIG. 1, the secondary only comprises diode 82 and capacitor 84. In this case, there is no path for the current to flow back to the primary when the back EMF is created during the period the switch 88 is off. There is no mechanism for the voltage on the capacitor 84 to discharge because diode 82 is reverse biased. Since there is no load in the secondary, the current through the secondary falls to zero and the voltage on the capacitor creeps higher and higher, destroying the sine wave shape of the output. At this point, the voltage on the capacitor does not follow the transfer function.
A graph illustrating the current through the primary and the secondary winding of the transformer when operating at a high efficiency with a synchronous rectifier in the secondary is shown in FIG. 2C. Curve 40 depicts the current I.sub.1 flowing through the primary when the switch 88 is on and curve 42 depicts the current I.sub.2 flowing though secondary when the switch is off. In this case, the synchronous diode 80 is placed in the secondary and functions to give back energy to the primary during the time the switch 88 is off. During the time the switch is on, the current I.sub.1 in the primary steadily increases until the switch turns off. When the switch turns off, the current I.sub.2 steadily decreases in the secondary. At some point, the current decreases to below zero where it changes direction. It is at this point when the current flow changes direction, that the synchronous diode circuit kicks in to maintain the flow of current in the secondary. Note that without a synchronous diode 80, the diode in the secondary of the flyback transformer does not permit a negative current to flow. When current cannot flow through the diode, the transmission function is not valid anymore and the output loses its sine wave shape.
The controller suitable for controlling an open loop flyback ring generator circuit will now be described in more detail. A high level block diagram illustrating the ring generator controller of the present invention is shown in FIG. 3. With reference to FIG. 1, the ring generator controller 10 comprises the necessary elements to realize the following equation as presented hereinabove. ##EQU9## Each of the entities on the right side of the equation are known. The input voltage V.sub.IN is sampled and input to the controller as shown in FIG. 1. In addition, the turns ratio N is known and available to the controller. The remaining entity, the output voltage V.sub.OUT is also known, since it the voltage that is desired to be generated at the output.
With reference to FIG. 3, the controller 10 comprises an A/D converter 50, multiplier 52, adder 54, divider 56, PWM circuit 58, output buffer 60, clock circuitry 62 and sine generator 64. The input voltage V.sub.IN is input to the A/D converter 50 which output a voltage representative of V.sub.IN. The output of the A/D converter is input to one of the two inputs of multiplier 52. The turns ratio N is input to the second input of the multiplier. The multiplier outputs the product N.multidot.V.sub.IN which is input to one of the two input of the adder 54.
Clock circuitry generates the necessary clock signals to drive sine generator 64 which can comprise a read only memory (ROM) containing a digitally sampled sine function. Note that only 90 degrees of sine function data is required. The output of the sine generator represents the output voltage V.sub.OUT. This is then input to the second input of adder 54. The adder generates the sum N.multidot.V.sub.IN +V.sub.OUT which is input to one of the two inputs of divider 56. The second input to the divider is the V.sub.OUT from the sine generator. The divider generates the dividend D as shown in the equation above.
The duty cycle value D is input to a conventional pulse width modulation (PWM) circuit 58 which functions to generate a square wave output signal having a duty cycle D. The output of the PWM circuit is input to the buffer 60 which generates a signal able to drive the switch 88.
It is apparent to those skilled in the electrical arts that the controller of FIG. 3 can be realized in many different ways as long as the equation for the duty cycle D is implemented. To better illustrate application of the controller of the present invention, an example ring generator controller is presented which realizes the above equation for the duty cycle D. A block diagram illustrating an example ring generator controller circuit in more detail is shown in FIG. 4.
The ring generator controller, generally referenced 100, implements the equation for the duty cycle D as described in detail in connection with FIG. 3. The ring generator circuit 100 of FIG. 4 implements the equation for the duty cycle D utilizing an A/D converter 112, multiplier 114, adder 116, divider 118, shifter 126, sine generator 128 and PWM circuit 120. In addition, the controller 100 comprises a pulse count circuit 106, up/down counter 108, clock circuitry 130, sync pulse circuitry 134 and buffers 122, 124. Power is supplied to the circuit via V.sub.CC 102 supplied from an external source. A ground 104 connects the circuit to a ground reference potential.
The clock circuitry 130 comprises standard circuitry for generating the various clock and reset signals used throughout the controller 100. In particular, the clock circuitry has two inputs XTAL.sub.1, XTAL.sub.2 to which a clock drive source is to be connected. For example, the clock drive source can have a frequency of between 10 to 20 MHz. The clock circuit is adapted to receive a simple RC oscillator, crystal oscillator, ceramic resonator, LC or external clock drive source. The clock circuit also comprises frequency divider circuitry to divide the clock into smaller frequencies. The two inputs F0, F1 can be used to determine the frequency of the sine wave output signal V.sub.OUT. The INHIBIT input functions to shut down the output signal from the PWM circuit 120. This reduces the current consumption of the controller and associated circuitry. The clock circuitry comprises internal synchronization circuitry that delays the inhibit action until the output sine wave signal level crosses the zero level. Note that the INHIBIT input can be used to generate the ringing signal's on/off intervals.
The A/D converter 112 functions to sample the input voltage V.sub.IN. A signal called CAD.sub.-- IN is input to the converter and a signal called PAD.sub.-- OUT is output from the converter. The A/D converter and related circuitry is adapted, in this example, to generate an 8 bit output that already has the turns ratio N factored into the output. In addition, the value output by the A/D converter is twice the product of the turns ratio times the input voltage, i.e., 2.multidot.N.multidot.V.sub.IN. The operation of the A/D converter and the method of sampling the input voltage is described in more detail hereinbelow in connection with FIG. 11.
The output of the A/D converter is input to one of the two input of the multiplier 114. The second input is the output of up/down counter 108. The up/down counter 108 in combination with pulse count circuitry 106 and an external comparator comprise the overcurrent protection means for the ring generator circuit. The principle of the overcurrent protection mean is to increase the value of the N.multidot.V.sub.IN term in the equation for D given above. Increasing the N.multidot.V.sub.IN term forces the equation to yield a lower value for D. As N.multidot.V.sub.IN increases, the duty cycle calculated decreases, thus lowering the output voltage which, in turn, reduces the current flow through the load.
The pulse count circuitry 106 receives a signal called CL which is a signal comprising of pulses indicating whether the current through the load is less than or greater than the maximum permissible current. The pulse count circuitry 106 is a 10 bit counter which functions to count the number of CL pulses received during each half cycle of the output sine wave. The frequency of the CL pulses may be as high as 300 KHz. The higher the count number, the higher the overload or overcurrent condition in the circuit. The count circuitry receives the clock and reset signals from the clock circuitry 130 required to perform the counting function on a half cycle basis. The counter is reset at a rate of approximately 34 to 100 Hz.
A block diagram illustrating the pulse count circuitry in more detail is shown in FIG. 5. The pulse count circuitry 106 comprises a 10 bit pulse counter 300 adapted to receives the CL signal, reference source 302 and comparators 304, 306. The pulse count circuitry is adapted to generate UP and DOWN signals based on the reference source 302 and the value of the pulse counter 300. Logic circuits 304, 306 compare the value of the reference source 302 with the value of the pulse counter 300. Logic block 304 comprises logic circuit means for determining whether the pulse counter is less than or equal to the reference source value. If it is, the DOWN signal is asserted. Similarly, logic block 306 comprises logic circuit means for determining whether the pulse counter is greater than the reference source value. If it is, the UP signal is asserted. Although not shown, the two signal F0, F1, input to the clock circuitry 130 (FIG. 4) are utilized by the pulse count circuitry 106 in determining the reference source value. Values of F0, F1 corresponding to higher frequency output sine wave signals, correspond to lower values of the reference source 302.
The UP and DOWN signals output by the pulse count circuitry 106 and input to up/down counter 108 are generated once for each half cycle of the sine wave output. The up/down counter 108 is a 5 bit counter that is adapted to count within the range 16 to 31. Once the counter 108 reaches a value of 16, additional DOWN pulses do not effect the count. Likewise, once the counter reaches a value of 31, additional UP pulses do not effect the count. If neither of the UP or DOWN signals are active, the count is not effected. In general, when no overcurrent condition exists, the value of the up/down counter is 16.
The output signal UD of counter 108 is input to the delay circuit 110 and the second input of the multiplier 114. The multiplier is adapted to multiply its two inputs together to yield the following 8 bit value ##EQU10## when no overcurrent condition exists, the terms `2` and ##EQU11## cancel each other out leaving only N.multidot.V.sub.IN. When an overcurrent condition does exist, the output of the multiplier will be higher than N.multidot.V.sub.IN but less than 2.multidot.N.multidot.V.sub.IN. Note that the signal UD can easily be divided by 32 by a right shift of 5 bits.
The output of the multiplier 114 is input to one of the two inputs of adder 116. The second input to the adder comprises the output of the sine generator 128. The sine generator functions to generate a 7 bit digital representation called V.sub.O of the output signal. The generator 128 receives a clock input from the clock circuitry 130. The generator 128 may be implemented in numerous ways well known in the art. For example, a combination address counter/ROM look up table containing the sine function samples can be used to generate the sine output. Alternatively, a synchronous state machine can be used that is adapted to generate the required sine function samples. The sum generated by the adder can be expressed as the following ##EQU12##
The output of the adder 116 is input to one of two inputs of divider 118. The second input is the output of a shifter 126. The input to the shifter is the output V.sub.O of the sine generator 128. The shifter 126 functions to shift the sine output V.sub.O 7 bits to the left, i.e., V.sub.O is multiplied by 128. This is done in preparation for the divide. The output of the divider is a 7 bit number D in the range 0 through 127 that is representative of the duty cycle. The output of the divider is given by ##EQU13##
The output D of the divider 118 is input to the pulse width modulation (PWM) circuit 120. The PWM circuit is a standard circuit that converts the input that is within the range 0 through 127 to a square wave having a duty cycle in accordance thereto. The duty cycle which can range between 0 and 1 expressed as a percentage (0 to 100%) is given as ##EQU14## The PWM circuit 120 functions to generate two output signals, a PWM signal and its inverse PWM. These two signals are input to buffers 122, 124, respectively to generate buffered signals. The buffers 122, 124 generate PWM signals that are suitable for driving an external transistor or circuit which is connected to the controller 100.
In addition to the pulse count circuit 106, the PWM circuit 120 also receives the CL signal input. Receipt of the CL signal, which indicates an overcurrent condition in the ringer circuit, causes the PWM unit to immediately terminate the current pulse width cycle. Thus, if the PWM signal is high at the time the CL signal is received, it is immediately brought low effectively terminating the current cycle.
The delay circuit 110 operates with the pulse count circuitry 106 and up/down counter 108 to provide overcurrent protection for the ringer circuit. The output UD of the up/down counter 108 is input to the delay circuit 110. When the value of UD reaches 31, its maximum, the delay circuit triggers a timer having a predetermined maximum, e.g., 300 mS. If the output UD of the up/down counter remains 31 for the full duration of the 300 ms count, the PWM.sub.-- OFF signal is generated.
The PWM.sub.-- OFF signal is input to the PWM circuit 120 and the sine generator 128. When received by the PWM circuit, the PWM.sub.-- OFF signal causes the PWM to shut off completely thus reducing the duty cycle to 0. When received by the sine generator, the PWM.sub.-- OFF signal causes the sine generator to shut down also, i.e., the value V.sub.O output by the sine generator is reduced to zero after the current cycle is completed.
After the PWM.sub.-- OFF signal is generated, the delay circuit triggers a second timer, this one set for a much longer period, e.g., 5 seconds. After waiting the period of the second timer, i.e., 5 seconds, the PWM.sub.-- OFF signal is de-asserted and the sine generator is reset to start generating the sine from the 0 degree point. In addition, the PWM circuit is turned back on. Since the contents of the up/down counter are not effected, the first timer of 300 ms can be immediately trigger again with the subsequent assertion of the PWM.sub.-- OFF signal after 300 ms providing the count remains at 31 for the duration. In this fashion, the delay circuit can trigger the PWM.sub.-- OFF signal over and over as long as the overcurrent/overload condition exists.
In addition to generating the sine function values, the sine generator 128 functions to generate a bridge control signal used by the output bridge circuit (described hereinbelow) to convert the rectified sine to a full positive and negative sine wave.
The sync pulse circuitry 134 receives an output from the sine generator 128 and the necessary clock signals from the clock circuitry 130 to generate an output signal that comprises a series of pulses representing the zero crossings of the sine wave output. Pulses are generated for both positive and negative zero crossing transitions. This circuit can be used, for example, by external telecommunication equipment to perform other related telecom functions.
An example ring generator circuit constructed utilizing the controller 100 of FIG. 4 will now be described in more detail. A schematic diagram illustrating a ring generator circuit constructed in accordance with an embodiment of the present invention is shown in FIG. 6. The ring generator circuit, generally referenced 150, is constructed around the ring generator controller 100 of FIG. 4. The circuit 150 is generally of the form as shown as described in connection with FIG. 1.
In general, the controller 100 generates the PWM switching signal which is used to switch a transistor on and off. During the on period, current flows through the primary winding of the transformer. When the transistor switches off, current flow is induced in the secondary of the transformer. The rectified sine wave voltage is converted into a sine wave by an output bridge circuit.
The input voltage V.sub.IN is filtered by a capacitor 152 and inductor or ferrite bead 156. The input voltage is applied to a voltage divider comprising resistors 154, 158. The output of the divider, denoted by V.sub.SAMPLE, is smoothed by capacitor 160. The sampled input voltage is input to the plus input of a comparator 224. The sampled voltage V.sub.SAMPLE is used to derive the input to the A/D converter 112 (FIG. 4) in the controller 100. The output of the comparator forms the input CAD.sub.-- IN to the A/D converter. The operation of this circuit is described in more detail hereinbelow.
The output of the ferrite bead 156 is input to a voltage regulator 162 which may comprise the LM7805, a 5 V voltage regulator IC manufactured by National Semiconductor or any other suitable voltage regulator. The output of the regulator 162 forms the V.sub.CC for the ringer circuit and the controller 100 and is filtered by capacitor 170 which preferably has a value of 0.33 .mu.F. The output of the regulator is also input to a voltage divider comprising resistors 164, 166. The output of the divider, denoted by V.sub.REF, is filtered by a capacitor 168 which preferably has a value of 10 nF. The voltage V.sub.REF is input to the plus input of comparator 222. The comparator functions to generate the CL pulses input to the controller 100 which serve to indicate an overcurrent condition at the output of the ringer.
The output of the ferrite bead 156 is also filtered by capacitors 172, 174. Capacitor 172 may comprise an aluminum electrolytic capacitor having a value or 47 .mu.F and capacitor 174 may comprise a high frequency, low ESR capacitor having a value of 1 .mu.F. The input voltage is then applied to the primary winding 176 of transformer 180. Transformer 180 comprises a single primary winding and two secondary windings 178, 208. Secondary winding 178 is used to transfer energy from the primary for producing the output of the ringer. Secondary winding 208 is used in the operation of the synchronous rectifier or diode which is described in more detail hereinbelow. The primary winding 176 having N.sub.1 turns, the secondary winding 178 having N.sub.2 turns and the turns ratio N given by N.sub.2 /N.sub.1.
The INHIBIT input to the controller 100 is provided by an external source. As described previously, the INHIBIT input controls the output of the ringer PWM circuit. A clock drive source 226 such as a ceramic resonator or crystal is connected to the XTAL.sub.1, XTAL.sub.2 inputs of the controller 100. Clock drive source 226 provides the clock drive for the clock circuitry 130 (FIG. 4) portion of the controller 100. The two frequency selection inputs F0, F1 determine the frequency of the sine wave output by the ringer, as described in more hereinabove. The V.sub.CC input is connected to the V.sub.CC line and GND is connected to ground potential. The example circuit of FIG. 6 does not utilize the SYNC signal or the PWM signal generated by the controller.
The bridge control signal is output from the BRC output of the controller and connected to the output bridge circuitry 200. The PAD.sub.-- OUT and CAD.sub.-- IN signals in combination with the A/D converter circuitry are described in more detail below in connection with FIG. 11.
The primary circuit is switched on and off by a switch Q.sub.1 which may comprise any suitable transistor such as the n-channel enhancement mode MOSFET shown in FIG. 6. An n-channel logic level type of transistor is well suited in this particular example assuming the controller outputs a 5 V logic level switching signal. One skilled in the art will recognize that other types of transistors can be used in situations where the voltages are other than 5 V, e.g., 12 V.
A resistor 218 and capacitor 216 are connected between the source and the drain of the transistor Q.sub.1. The resistor 218 and capacitor 216 form a snubber circuit which functions to greatly reduce the voltage spikes that would normally appear on the drain terminal of transistor Q.sub.1. The large voltage spikes caused by the back EMF generated by the distributed inductance in the primary winding circuitry and by the inherent diode formed between the drain and the source of the transistor Q.sub.1. A suitable value for the resistor 218 is 62 ohms and for the capacitor 216 is 330 pF.
The source of transistor Q.sub.1 is connected to resistor 214 which functions to develop a voltage proportional to the current flowing through the primary 176. This current is proportional to the power input to the ringer circuit which, in turn, is proportional to the power transferred to the load. Thus, the voltage developed across resistor 214 is proportional to the ringer input power and to the load power and can be used to detect whether an overload condition exists. A suitable value for resistor 214 is approximately 0.1 ohms.
The voltage developed across the resistor 214 is input to the minus input of comparator 222. When the current is below the reference threshold, the output of the comparator remains high. The output of the comparator 222 will switch to a low level whenever the current flowing through the primary exceeds a predetermined threshold. This threshold is determined by the combination of the value of V.sub.REF and the value of resistor 214. As described above, pulses on the CL input of the controller 100 cause the PWM circuit to lower the duty cycle of the PWM output signal. This, in turn, is intended to lower the output voltage and thus, the load current. This is reflected back to the primary and reduces the current flowing through the transistor Q.sub.1. This causes the voltage across resistor 214 to decrease and eventually, the output of the comparator 222 will go high. Thus, in the event of an overcurrent condition, a series of pulses on the CL input line are generated which are effective to lower the load current and reduce or eliminate the overcurrent condition.
Assuming a value of 0.1 ohms for resistor 214, the circuit 150 is adapted such that when the current through the primary exceeds approximately 2 A, a CL pulse will be generated. This requires a reference voltage V.sub.REF of 0.2 V to be supplied to the plus input of comparator 222. The threshold for generating the CL pulses can be adjusted by changing the value of the resistor 214 and the value of the reference voltage V.sub.REF.
A resistor 183 in series with a capacitor 182 is connected in parallel across the secondary 178 of the transformer 180. Resistor 183 and capacitor 182 function as a snubber to reduce the high voltage spikes generated in the secondary circuit from the back EMF generated when Q.sub.1 turns off. Suitable values for the resistor 183 and the capacitor 182 are 390 ohm and 220 pF, respectfully.
The secondary circuit also comprises a diode 184 and capacitor 186. When Q.sub.1 is on, diode 184 prevents current from flowing. When Q.sub.1 turns off, current flows through diode 184 in the positive I.sub.2 direction and charges capacitor 186, thus generating a positive voltage V.sub.RS across the capacitor 186. Note that without the diode 184, the capacitor would discharge when Q.sub.1 turns on again and current flows through the primary. During operation, voltages in excess of 100 V may be generated across the capacitor 186. A suitable value for capacitor 186 is 0.22 .mu.F.
The operation of the synchronous rectifier circuit, generally referenced 230, will now be described in more detail. The synchronous rectifier 230 is located on the secondary of the transformer 180 and comprises diodes 192, 194, 202, switch Q.sub.2, inductor or ferrite bead 188, zener diodes 190, 204, resistors 196, 198, capacitor 206 and secondary winding 208. Switch Q.sub.2 is preferably a transistor such as an n-channel enhancement MOSFET. Zener diode 190 preferably has a threshold voltage of 15 V and zener diode 204 preferably has a threshold voltage of 5.1 V. The value of resistors 196, 198 is preferably 1K and 10K ohms, respectively. Note that the inductance of the primary winding 176 is denoted by L.sub.1, the inductance of the secondary winding 178 denoted by L.sub.2 and the inductance of secondary winding 208 denoted by L.sub.3.
When transistor Q.sub.1 is on, i.e., R.sub.DS .apprxeq.0, the current I.sub.1 in the primary winding 176 flows through L.sub.1 in accordance with the following equation ##EQU15## The current in the secondary winding 178 (which is wound in the opposite direction as indicated by the dots in FIG. 6) would be minus I.sub.2, but the diode 184 and the synchronous rectifier 230 do not permit current to flow. Thus, the current I.sub.2 is zero.
When transistor Q.sub.1 shuts off i.e., R.sub.DS .fwdarw..infin., the current I.sub.1 is zero. The voltage on the secondary is reversed due to the back EMF and the current I.sub.2 flows through diode 184 and charges capacitor 186. The current flow I.sub.2 immediately begins to decrease in a linear fashion according to ##EQU16## When the current through the loop comprising the secondary winding 178, capacitor 186 and diode 184 reaches zero, the diode becomes reverse biased and thus does not permit negative I.sub.2 current to flow. It is at this point that the synchronous diode begins to conduct, permitting current to flow from the capacitor 186 to the secondary winding 178. In other words, the capacitor functions as a voltage source that charges the transformer 180.
An illustrative example will now be presented to highlight the operation of the synchronous rectifier 230. For purposes of the example it is assumed that V.sub.IN is approximately 12 V, the turns ratio N1:N2 is 1:4 and the turns ratio N1:N3 is approximately 1:1, where N1, N2, N3 are the number of turns for windings 176, 178, 208, respectively.
When transistor Q.sub.1 is on, i.e., R.sub.DS .apprxeq.0, current I.sub.1 flows in the primary winding 176. The current I.sub.2 in the secondary 178 is zero since diode 184 is reverse biased. Current does flow, however, through the secondary winding 208. The inductance L.sub.3 creates a current loop through zener diode 204, diode 202 and capacitor 206. Due to the turns ratio of 1:1, 12 V is generated across the secondary 208. Thus, there is a drop of 5.1 V across the zener diode, 0.7 V across the diode 202 yielding 6.2 V across the capacitor 206. The voltage V.sub.D is equal to -5.8 V. For there to be a sufficient voltage V.sub.GS to turn on transistor Q.sub.2, V.sub.GS must exceed the positive threshold voltage of transistor Q.sub.2. The zener diode 190 can optionally be used to limit V.sub.GS to a safe value. In this case, the voltage V.sub.D across the series diodes 202, 204 is -5.8 V and thus transistor Q.sub.2 is off and the current I.sub.2 is zero.
The moment transistor Q.sub.1 turns off, the voltages across secondary windings 178, 208 reverse directions due to the back EMF generated. Assuming that the output voltage is approximately 100 V, the voltage VL.sub.1 generated across the primary winding 176 equals the voltage VL.sub.3 generated across the secondary winding 208 and is given by ##EQU17## Therefore, the voltage V.sub.D is now 25+6.2=31.2 V. There is now sufficient potential to exceed the threshold voltage of transistor Q.sub.2 which is protected by zener diode 190. Once Q.sub.2 turns on, current begins to flow through resistor 196, zener diode 190, ferrite bead 188, zener diode 204 and diode 202. The voltage V.sub.GS on the gate of transistor Q.sub.2 is 15 V, thus Q.sub.2 is on and current is permitted to flow is both positive and negative directions. Note, however, that in actuality, current through transistor Q.sub.2 only flows in the negative I.sub.2 direction due to diode 192. Thus, current flows through the synchronous rectifier 230 only for negative I.sub.2 current.
When the next cycle begins, transistor Q.sub.1 turns on and the voltage VL.sub.3 across the secondary winding 208 becomes 12 V again. This causes a rapid discharge of charge from the gate of transistor Q.sub.2 through diode 194 permitting it to quickly turn off. Resistor 196 functions to soak up excess voltage supplied to the gate of Q.sub.2. Note that the ferrite bead 188 functions to limit the current spike that is generated when transistor Q.sub.1 turns on and Q.sub.2 did not yet turn off, e.g., the first 100 nanoseconds. During this time it appears as a short. Optionally the PWM signal can be used to turn Q.sub.2 off before Q.sub.1 turns on.
To aid in understanding the operation of the synchronous rectifier 230, a series of graphs are presented that show the relationship between the current in the transformer windings and the transistor Q.sub.1 voltages.
A graph illustrating the voltage V.sub.DS across Q.sub.1 and the corresponding current I.sub.1 during the periods when Q.sub.1 is ON and OFF is shown in FIG. 7. The trace 260 shows the voltage V.sub.DS of transistor Q.sub.1 during the time Q.sub.1 is on and off. During the time Q.sub.1 is on, V.sub.DS is zero and R.sub.DS .apprxeq.0. The voltage VL.sub.1 across the primary is given by ##EQU18## However, since V.sub.IN is a constant and VL.sub.1 =V.sub.IN, the magnitude of the current I.sub.1 flowing through the primary 176 can be expressed as the following ##EQU19## where C is a negative constant. Thus, the current I.sub.1 in the primary, as shown in trace 262, steadily increases, from an initial negative value to a final positive value. The current I.sub.1 is initially negative due to the voltage impressed on it from the secondary during the previous cycle when Q.sub.1 was off.
When the PWM signal from the controller 100 turns Q.sub.1 off, the voltage V.sub.DS is rising and R.sub.DS .fwdarw..infin.. When Q.sub.1 turns off, the current I.sub.1 through the primary 176 is zero.
A graph illustrating the voltage across the series combination of diodes 202, 204 and the current I.sub.2 during the periods when Q.sub.1 is ON and OFF is shown in FIG. 8. While transistor Q.sub.1 is on and current flows through the primary, the voltage V.sub.D is approximately -5.8 V as shown in trace 270. Transistor Q.sub.2 is off, diode 184 is reverse biased and no current flows through the secondary 178, i.e., the current I.sub.2 is zero, as shown in trace 272.
When transistor Q.sub.1 turns off, the back EMF generates 25 V across the secondary 208 and the voltage V.sub.D increases to approximately 31.2 V. This is sufficient to turn on transistor Q.sub.2 thus permitting negative I.sub.2 current to flow. Initially, however, the current I.sub.2 is positive and, although the synchronous rectifier is on, current cannot flow through it due to the reverse biased diode 192. The current I.sub.2 steadily decreases until it reverses direction and becomes negative. The synchronous rectifier 230 permits the current I.sub.2 to flow in the negative direction as described in detail above.
A graph illustrating the voltage V.sub.GS of transistor Q.sub.1 and the current I.sub.1 during the periods when Q.sub.1 is OFF and ON is shown in FIG. 9. While V.sub.GS is zero, as shown in trace 280, transistor Q.sub.1 is off. The current I.sub.1 through the primary is thus zero, as shown in trace 282. When the PWM signal from the controller goes high, VGS goes to a high level and transistor Q.sub.1 turns on. This causes the primary current flow I.sub.1 to steadily increase in accordance with the following expression, as given hereinabove ##EQU20##
The A/D converter and its associated circuitry will now be described in more detail. A schematic block diagram illustrating the A/D converter and associated circuitry is more detail is shown in FIG. 10. To aid in understanding, the A/D portion of the controller 100 is shown with the input sampling circuitry of the ringer circuit 150 (FIG. 6). In particular, the input voltage V.sub.IN is applied to a voltage divider comprising resistors 154, 158. The output of the voltage divider, denoted V.sub.SAMPLE, is input to the plus input of comparator 224. The output of the comparator, denoted CAD.sub.-- IN, is input to the A/D circuitry 112.
The A/D converter circuitry 112 comprises an 8 bit up/down counter 290, PWM generator 294 and an 8 bit latch 292. The output of the latch forms the output of the A/D converter and can range from 0 to 255. The counter output is coupled to the PWM generator 294 and the latch 292. The output of the PWM generator 294, denoted PAD.sub.-- OUT, is input to a low pass filter which is connected to the minus input of the comparator 224. The low pass filter comprises series resistor 210 and capacitor 212 connected between the minus input of the comparator 224 and ground.
In operation, a high level for CAD.sub.-- IN causes the counter 290 to increase its count. This causes the output of the PWM 294, i.e., PAD.sub.-- IN to increase its duty cycle which causes the voltage at the minus input of comparator 224 to increase. Eventually, CAD.sub.-- IN goes low which causes the counter 290 to reduce its count. Which, in turn, causes PAD.sub.-- OUT to decrease its duty cycle and the voltage on the minus input of the comparator 224 to decrease. Once steady state conditions are reached, i.e., a slowly varying input voltage V.sub.IN, the counter value will oscillate around the value of the sampled voltage. The combination of resistor 210 and capacitor 212 function to smooth, i.e., integrate, the PAD.sub.-- OUT signal.
It is recalled that the expression for the output voltage V.sub.OUT is given as the following ##EQU21## Solving for D yields ##EQU22## The value representative of V.sub.OUT is an 7 bit number output by the sine generator 128 (FIG. 4) that can range in value from 0 to 100 corresponding to a V.sub.OUT of 0 to 100 V peak or 70 Vrms. Thus, V.sub.OUT can be expressed as
An expression for N.multidot.V.sub.IN is given by: ##EQU23## where R.sub.154 and R.sub.158 correspond to the values of resistors 154, 158, respectively. The value 255 represents the maximum value of the A/D converter output while the value 5 represents a 5 V full scale value for the input voltage. The term ##EQU24## is the protection multiplier used to provide the ringer with overcurrent protection. The factor of 2 present in the equations presented above, is already factored into the terms of the equation.
Thus, an expression for N can be written as follows ##EQU25## For values of V.sub.OUT other than 100 V peak, the equation above becomes ##EQU26## It is important to note that the above equations are presented assuming the following
V.sub.OUT =100 V peak
V.sub.IN =12 V
N=4
N.multidot.V.sub.IN =48
Given the above assumptions, an expression for the duty cycle D can be written as ##EQU27## If other values of input voltage are desired, the turns ratio N must be modified accordingly.
The following table provides values of N for typical values of input voltage.
In constructing a ring generator circuit based on the controller of the present invention, one should first choose the input voltage. Once the input voltage is chosen, this determines the value of N for the transformer. The value of resistors 154, 158 can then be chosen once N is determined.
A diagram illustrating the half wave rectified sinusoidal waveform generated by the ring generator circuit at the input to the output bridge circuitry is shown in FIG. 11A. The half sine wave as shown in trace 240, is the voltage V.sub.RS that is generated across the capacitor 186 (FIG. 6) and input to the output bridge circuit 200.
A diagram illustrating the half wave rectified sinusoidal waveform of FIG. 11A in more detail highlighting the varying widths of the pulses used to generate the output waveform is shown in FIG. 11B. An examination of FIG. 11B reveals that the output voltage is a sequence of DC values, smoothed to resemble a sine wave. For illustration purposes, three steps of the output voltage 242, 244, 246 are shown. A plurality of pulses 248 having a duty cycle T.sub.ON.sup.N make up the portion of the output voltage referenced 242. As the value of the sine function increase, the pulse width increases accordingly. Step 244 is comprised of pulses having a pulse width T.sub.ON.sup.N+1. Similarly, step 246 is comprised of pulses having a width T.sub.ON.sup.N+2.
The output bridge circuit will now be described in more detail. A schematic diagram illustrating the output bridge circuitry in more detail is shown in FIG. 12. The output bridge circuit, generally referenced 200, functions to convert the half sine wave signal V.sub.RS to a full sine wave with positive and negative transitions. Since output bridge circuits are well known in the art, the circuit 200 presented herein will not be described in great detail.
The output bridge circuit 200 comprises four switches controlled by the bridge control signal BRC output from the sine generator 128 (FIG. 4). This signal is input to two opto couplers 340, 370. Opto coupler 340 comprises LED 344 and transistor 342. The anode of LED 344 is coupled to V.sub.CC via resistor 346. Similarly, opto coupler 370 comprises LED 374 and transistor 372. The cathode of LED is coupled to ground via resistor 376. The bridge control signal is connected to the cathode of LED 344 and the anode of LED 374.
The bridge control signal is a square wave signal having a period equal to that of the sine wave generated. Assuming the bridge control signal is initially high, the LED 374 in opto coupler 370 conducts while the LED 344 in opto coupler 340 is off. Thus, transistor 372 is on and the switch comprised of NPN transistors 366, 364, 362 are all off. Current does flow through resistor 358. In addition, current cannot flow through resistors 310, 318 therefore PNP transistors 312, 314 are off.
If opto coupler 340 is off, current flows through resistor 320 to provide base drive to turn on transistors 322, 324, 326. Thus, current flows through resistors 356, 328 turning on transistors 352, 354. Thus, a current path is created from V.sub.RS through transistor 352, resistor 382 to V.sub.OUT and through the load, resistor 380, transistor 326 and returning to V.sub.RS.
Assuming now the bridge control signal goes low, the LED 344 in opto coupler 340 conducts while the LED 374 in opto coupler 370 shuts off. Thus, transistor 342 is on and the switch comprised of NPN transistors 322, 324, 326 are all off. Current does flow through resistor 320. Current cannot flow through resistors 356, 328 therefore PNP transistors 352, 354 are off.
If opto coupler 370 is off, current flows through resistor 358 to provide base drive to turn on transistor 366, 364, 362. Thus, current flows through resistors 310, 318 turning on transistors 312, 314. A current path is thus created from V.sub.RS through transistor 314, resistor 380 to V.sub.OUT and through the load, resistor 382, transistor 362 and returning to V.sub.RS.
Capacitor 384 in combination with resistors 380, 382 smooth the output voltage V.sub.OUT. Resistors 380, 382 are preferable low valued such as on the order of 10 ohms. Capacitor is preferably on the order of 0.1 .mu.F. Diodes 316, 330, 350, 360 function to reduce voltage spikes and protect the output bridge and related circuitry.
While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made. For example, one skilled in the art could adapt the ring generator controller of the present invention to operate with other type of open loop flyback DC to AC converter circuits such as UPSs and AC generators from a battery supply. In addition, the present invention can be used to implement an open loop flyback DC to DC converter by removing the sine generator and output bridge circuitry.
Claims
What is claimed is:
1. A controller suitable for controlling an open loop flyback DC to AC converter circuit, said circuit including a transformer having a primary and a secondary, said controller comprising: sampling means for generating a digital number representative of the magnitude of a source of DC electrical power; sine generator means for generating a digital representation of a sinusoidal waveform; processing means for determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU28## wherein D=duty cycle of PWM signal N=turns ratio of said transformer V.sub.IN =voltage level of said source of DC electrical power V.sub.OUT =digital representation of a sinusoidal waveform; and pulse width modulation means for generating said PWM signal in response to the duty cycle generated by said processing means.
2. The controller according to claim 1, wherein said sampling means comprises A/D converter means.
3. The controller according to claim 1, wherein said sampling means comprises: comparator means for comparing the magnitude of said source of DC electrical power with a converter signal; a counter responsive to the output of said comparator means; converter means for generating said converter signal in response to the output of said counter; and a latch for periodically latching the output of said counter.
4. The controller according to claim 3, wherein said comparator means comprises: a voltage divider coupled to said source of DC electrical power; filter means for low pass filtering said converter signal; and a comparator for comparing the output of said voltage divider and the output of said filter means and generating an compare signal therefrom.
5. The controller according to claim 1, wherein said sine generator means comprises counting means coupled to look up table means.
6. The controller according to claim 1, wherein said sine generator means comprises synchronous state machine means.
7. The controller according to claim 1, wherein said processing means comprises: a multiplier for generating the product N.multidot.V.sub.IN ; an adder for generating the sum N.multidot.V.sub.IN +V.sub.OUT ; and a divider for dividing V.sub.OUT by said sum.
8. The controller according to claim 1, further comprising synchronization means for generating a sequence of pulses in response to both the positive and negative zero crossings of the output sine wave.
9. The controller according to claim 1, further comprising overcurrent protection means operative to reduce the duty cycle of said PWM signal in response to an overcurrent condition in the output of said circuit.
10. The controller according to claim 1, further comprising overcurrent protection means operative to shut down said pulse width modulation means in response to a severe current overload or short circuit applied to the output of said circuit.
11. The controller according to claim 1, further comprising bridge control means for generating a bridge control signal for converting a half wave sine function to a full wave sine function, said bridge control signal having the same frequency as the sine wave output by said circuit.
12. The controller according to claim 1, further comprising buffer means coupled to the output of said pulse width modulation means, said buffer means for generating an output PWM signal with suitable drive and load characteristics.
13. A controller for controlling the operation of a DC to AC converter circuit, said circuit connected to a source of DC electrical power and having an open loop flyback topology including a transformer having a primary winding and a secondary winding, a switch coupled to said primary winding and an output bridge circuit, said controller comprising: sampling means for generating a digital representation of the voltage level of said source of DC electrical power; sine generator means for generating a digital representation of a sinusoidal waveform; processing means for determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU29## wherein D=duty cycle of PWM signal N=turns ratio of said transformer V.sub.IN =voltage level of said source of DC electrical power V.sub.OUT =digital representation of a sinusoidal waveform; pulse width modulation means for generating said PWM signal in response to the duty cycle generated by said processing means, said PWM signal output by said controller and input to said switch; and bridge control means for generating a bridge control signal output by said controller and input to said output bridge circuit, said output bridge circuit operative to convert a half wave sine function to a full wave sine function subsequently output by said circuit.
14. The controller according to claim 13, further comprising overcurrent protection means operative to reduce the duty cycle of said PWM signal in response to an overcurrent condition in the output of said circuit.
15. The controller according to claim 13, further comprising overcurrent protection means operative to shut down said pulse width modulation means in response to a severe current overload or short circuit applied to the output of said circuit.
16. The controller according to claim 14, wherein said overcurrent protection means comprises: pulse counting means for counting pulses in response to the current in said primary exceeding a predetermined threshold and generating UP and DOWN signals in accordance thereto; up/down counter means for incrementing and decrementing a counter in response to said UP and DOWN signals, respectively; wherein said processing means is adapted to receive and process the output of said up/down counter such that the duty cycle of said PWM signal is adjusted in accordance therewith.
17. The controller according to claim 13, wherein said sampling means comprises A/D converter means.
18. The controller according to claim 13, wherein said sampling means comprises: comparator means for comparing the magnitude of said source of DC electrical power with a converter signal; a counter responsive to the output of said comparator means; converter means for generating said converter signal in response to the output of said counter; and a latch for periodically latching the output of said counter.
19. The controller according to claim 18, wherein said comparator means comprises: a voltage divider coupled to said source of DC electrical power; filter means for low pass filtering said converter signal; and a comparator for comparing the output of said voltage divider and the output of said filter means and generating an compare signal therefrom.
20. The controller according to claim 13, wherein said sine generator means comprises counting means coupled to look up table means.
21. The controller according to claim 13, wherein said sine generator means comprises synchronous state machine means.
22. The controller according to claim 13, wherein said processing means comprises: a multiplier for generating the product N.multidot.V.sub.IN ; an adder for generating the sum N.multidot.V.sub.IN +V.sub.OUT ; and a divider for dividing V.sub.OUT by said sum.
23. The controller according to claim 13, further comprising synchronization means for generating a sequence of pulses in response to both the positive and negative zero crossings of the output sine wave.
24. The controller according to claim 13, further comprising buffer means coupled to the output of said pulse width modulation means, said buffer means for generating an output PWM signal with suitable drive and load characteristics.
25. A method of controlling a DC to AC converter circuit having an open loop flyback topology, said circuit including a transformer having a primary and a secondary, said method comprising the steps of: generating a digital number representative of the magnitude of a source of DC electrical power; generating a digital representation of a sinusoidal waveform; determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU30## wherein D=duty cycle of PWM signal N=turns ratio of said transformer V.sub.IN =voltage level of said source of DC electrical power V.sub.OUT =digital representation of a sinusoidal waveform; and generating said PWM signal in response to the duty cycle generated by said processing means.
26. The method according to claim 25, wherein said step of generating a digital number comprises: comparing the magnitude of said source of DC electrical power with a converter signal and maintaining a count in response thereto; generating said converter signal in response to the magnitude of said count; and periodically latching the value of said count.
27. The method according to claim 26, wherein said step of comparing comprises: dividing said source of DC electrical power to generate a divided voltage; low pass filtering said converter signal and generating a filtered signal therefrom; and comparing said divided voltage with and said filtered signal and generating a compare signal therefrom.
28. The method according to claim 25, wherein said step of determining comprises: generating the product N.multidot.V.sub.IN ; generating the sum N.multidot.V.sub.IN +V.sub.OUT ; and dividing V.sub.OUT by said sum.
29. The method according to claim 25, further comprising the step of generating a sequence of pulses in response to both the positive and negative zero crossings of the output sine wave.
30. The method according to claim 25, further comprising the step of reducing the duty cycle of said PWM signal in response to an overcurrent condition in the output of said circuit.
31. The method according to claim 25, further comprising the step of suspending the generation of said PWM signal in response to a severe current overload or short circuit applied to the output of said circuit.
32. The method according to claim 25, further comprising the step converting a half wave sine function to a fill wave sine function.
33. The method according to claim 25, further comprising the step of generating an output PWM signal with suitable drive and load characteristics.
34. A method of controlling a DC to DC converter circuit having an open loop flyback topology, said circuit including a transformer having a primary and a secondary, said method comprising the steps of: generating a digital number representative of the magnitude of a source of DC electrical power; generating a digital representation of the desired output voltage; determining the duty cycle of a pulse width modulated (PWM) signal in accordance with the following equation ##EQU31## wherein D=duty cycle of PWM signal N=turns ratio of said transformer V.sub.IN =voltage level of said source of DC electrical power V.sub.OUT =digital representation of the desired output voltage; and generating said PWM signal in response to the duty cycle generated by said processing means.
35. The method according to claim 34, wherein said step of generating a digital number comprises: comparing the magnitude of said source of DC electrical power with a converter signal and maintaining a count in response thereto; generating said converter signal in response to the magnitude of said count; and periodically latching the value of said count.
36. The method according to claim 35, wherein said step of comparing comprises: dividing said source of DC electrical power to generate a divided voltage; low pass filtering said converter signal and generating a filtered signal therefrom; and comparing said divided voltage with and said filtered signal and generating a compare signal therefrom.
37. The method according to claim 34, wherein said step of determining comprises: generating the product N.multidot.V.sub.IN ; generating the sum N.multidot.V.sub.IN +V.sub.OUT ; and dividing V.sub.OUT by said sum.
38. The method according to claim 34, further comprising the step of reducing the duty cycle of said PWM signal in response to an overcurrent condition in the output of said circuit.
39. The method according to claim 34, further comprising the step of suspending the generation of said PWM signal in response to a severe current overload or short circuit applied to the output of said circuit.
40. The method according to claim 34, further comprising the step of generating an output PWM signal with suitable drive and load characteristics.
Patent Citations (13)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3739253 | 1973-06-01 | Humphrey et al. | |
| US4611097 | 1986-09-01 | Grimes | |
| US4881014 | 1989-11-01 | Okochi | |
| US5068590 | 1991-11-01 | Glennon et al. | |
| US5140630 | 1992-08-01 | Fry et al. | |
| US5216585 | 1993-06-01 | Yasumura | |
| US5260996 | 1993-11-01 | Dillon et al. | |
| US5289359 | 1994-02-01 | Ziermann | |
| US5307407 | 1994-04-01 | Wendt et al. | |
| US5321596 | 1994-06-01 | Hurst | |
| US5473530 | 1995-12-01 | Giuseppe | |
| US5485365 | 1996-01-01 | Dan-Harry | |
| US5701243 | 1997-12-01 | Youn |